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AP-4178E-RM
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swskit-sources/impdbg.mac
There are no other files named impdbg.mac in the archive.
;<3-MONITOR>IMPDBG.MAC.4, 8-Nov-77 17:43:52, EDIT BY CROSSLAND
;<3-MONITOR>IMPDBG.MAC.3, 7-Nov-77 13:02:27, EDIT BY KIRSCHEN
;MORE COPYRIGHT UPDATING...
;<3-MONITOR>IMPDBG.MAC.1, 6-Nov-77 18:09:05, EDIT BY CROSSLAND
;KLUDGE TO TEST FOR INTERRUPTS OF RIGHT TYPE
;<3-MONITOR>IMPANX.MAC.9, 2-Nov-77 23:04:39, EDIT BY CROSSLAND
;ADD IMPOFL BUGINF
;<3-MONITOR>IMPANX.MAC.8, 12-Oct-77 13:50:05, EDIT BY KIRSCHEN
;UPDATE COPYRIGHT FOR RELEASE 3
;<3-MONITOR>IMPANX.MAC.7, 4-Oct-77 11:01:57, EDIT BY MILLER
;CHANGE EXPRESSIONS WITH MSEC1 IN THEM
;<3-MONITOR>IMPANX.MAC.6, 29-Sep-77 02:22:14, EDIT BY CROSSLAND
;GET STAUS ON INPUT ERROR BEFORE TURNING OFF INPUT
;<3-MONITOR>IMPANX.MAC.5, 23-Jul-77 22:53:24, EDIT BY CROSSLAND
;MOVE BUFFERS TO ANBSEC SECTION
;<3-MONITOR>IMPANX.MAC.4, 17-Jun-77 05:38:12, EDIT BY CROSSLAND
;CONVERT TO EXTENDED ADDRESSING
;CHANGE TO IMPCHK,ININX0,IMIERR TO RECOVER FROM NO RFNIB NET HANG
;<3-MONITOR>IMPANX.MAC.3, 19-May-77 04:56:41, EDIT BY CROSSLAND
;FIX WRONG HOST BUGCHK
;<3-MONITOR>IMPANX.MAC.2, 10-May-77 19:08:56, EDIT BY HURLEY
;<101B-MONITOR>IMPANX.MAC.3, 29-Mar-77 10:08:33, EDIT BY CROSSLAND
;TCO 1763 - FIX MESSAGE SIZE.
;<A-MONITOR>IMPANX.MAC.2, 25-Jan-77 15:24:03, EDIT BY OPERATOR
; FIX TYPO IN IMPEI5 SITE ADDRESS CHECK
;<A-MONITOR>IMPANX.MAC.1, 21-Jan-77 18:00:21, EDIT BY CLEMENTS
;RECODE FOR AN10 INTERFACE. RENAME FILE TO BE IMPANX.MAC
;<CLEMENTS>IMPPHY.MAC.1, 19-Jul-76 16:18:47, EDIT BY CLEMENTS
;SEPARATED PHYSICAL IMP DRIVER FROM IMPDV.MAC
;THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY ONLY BE USED
; OR COPIED IN ACCORDANCE WITH THE TERMS OF SUCH LICENSE.
;
;COPYRIGHT (C) 1976, 1977, 1978 BY DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASS.
SEARCH PROLOG
SEARCH MACSYM,MONSYM
TTITLE (IMPPHY,IMPANX,< - IMP DRIVER FOR AN10 - R CLEMENTS>)
;HARDWARE DEFINITIONS FOR AN10 DEVICE INTERFACE
ANI=520 ;I/O DEVICE NUMBER FOR INPUT SIDE
ANO=524 ;I/O DEVICE NUMBER FOR OUTPUT SIDE
;BITS IN CONI FOR ANI
ANIMRQ==1B27 ;MSG REQUEST. IMP STARTING TO SEND TO HOST.
ANIBSY==1B26 ;BUSY. HOST IS ACCEPTING A MESSAGE
ANIM36==1B25 ;MESSAGE BEING ASSEMBLED INTO 36 BIT
; WORDS IF 1, 32 BIT WORDS IF 0.
ANIWCO==1B24 ;WD COUNT OVERFLOW. MESSAGE PORTION IS DONE.
ANIDON==1B23 ;DONE. IMP SENT LAST BIT.
ANIIID==1B19 ;IMP IS DOWN. (READY LINE OFF)
ANIIWD==1B18 ;IMP WAS DOWN. (READY LINE HAS BEEN OFF)
;BITS IN CONO FOR ANI
ANIRST==1B19 ;RESET THE WHOLE AN10 (EXCEPT HOST READY LINE)
ANICLE==1B18 ;CLEAR ERROR FLAGS IN LH OF CONI,
; CLR IMP WAS DOWN.
ANXCHS==IMPCHS ;TWO ADJACENT PI CHANNELS IN B30-35
;BITS IN CONI FOR ANO
ANOEND==1B27 ;END OF MSG. SEND "LAST" WHEN WD CNT RUNS OUT.
ANOBSY==1B26 ;BUSY. SEND WORDS TO THE IMP.
ANOM36==1B25 ;MODE 36. SEND ALL 36 BITS OF WORDS.
; ELSE, JUST SEND LEFT-HAND 32 BITS.
ANOWCO==1B24 ;WORD COUNT OVERFLOW. THIS MSG
; PORTION COMPLETED.
ANODON==1B23 ;ALL BITS INCLUDING "LAST" HAVE BEEN SENT.
ANOIID==1B19 ;IMP IS DOWN, SAME AS IN ANI
ANOIWD==1B18 ;IMP WAS DOWN, SAME AS IN ANI
;BITS IN CONO FOR ANO
ANOCLE==1B18 ;CLEAR ERROR BITS, IMP WAS DOWN BIT.
;REGISTER SELECT FIELD, IN BOTH ANO AND ANI CONO'S
; NOTE THESE AREN'T USED MUCH BECAUSE HARDWARE SWITCHES TO
; THE "RIGHT" REGISTER MOST OF THE TIME BY ITSELF.
ANXVAR==2B29 ;VECTOR INTERRUPT ADDRESS REGISTER
ANXWAR==1B29 ;WORD COUNT AND ADDRESS REGISTER
ANXDR==0B29 ;DATA REGISTER.
;BITS IN INPUT DEVICE VECTOR ADDRESS REGISTER
ANIHRL==1B10 ;HOST READY LINE. DATAO A 1 TO BECOME READY.
;MISCELLANEOUS VARIABLES
PIMSTK: IOWD NIMSTK,IMSTK ;IMP INTERRUPT STACK POINTER
DEFSTR IMWDCT,,12,12 ;WORD COUNT FOR WORD COUNT/ADDRESS REG.
DEFSTR IMBFAD,,35,23 ;ADDRESS FOR WORD COUNT/ADDRESS REG.
;INTERRUPT LOCATION
ANOVIL: XPCW ANOVI1 ;OUTPUT INTERRUPT LOCATION
ANIVIL: XPCW ANIVI1 ;INPUT INTERRUPT LOCATION
;CLOCK LEVEL CHECK ROUTINE
IMPCHK::MOVEI T2,^D1000
MOVEM T2,IMPTM2 ;CALL THIS EVERY SECOND
SKIPN IMPRDY ;NET ON?
RET ;NO.
CONSO ANI,ANIIWD ;IF IMP WAS DOWN CALL IMIERR AND RESET
CALL IMPRLQ ;IS IMP DOWN NOW OR RECENTLY?
SKIPL IMPRDT ;AND NOT ALREADY NOTICED?
RET ;NO. NO NEED TO SET ERROR FLAGS
CALL IMIERR ;BE SURE IT'S NOTICED
AOS IMPFLG ;CAUSE RUNNING OF NCP FORK
RET
;START INPUT
;CALLED FROM PROCESS LEVEL WHEN BUFFERS MADE AVAILABLE AND INPUT IS OFF
;AND FROM ENDIN PROCESSOR IF MORE BUFFERS ARE AVAILABLE
IMISRT::CALL IMPRLQ ;IS DEVICE UP AND IMP READY?
RET ;NO, DO NOTHING
SOSL IMPNFI ;SUB 1 FROM COUNT OF FREE INPUT BUFFERS
SKIPN T1,IMPFRI ;GET POINTER TO FREE INPUT BUFFER
BUG(HLT,IMPNII,<NO IMP INPUT BUFFERS>)
HLRZ T2,0(T1) ;GET NEXT FREE
HRLI T2,ANBSEC ;SET SECTION NUMBER
MOVEM T2,IMPFRI ;UPDATE POINTER TO FIRST FREE BUFFER
HRRZS 0(T1) ;CLEAR LINK OF CURRENT BUFFER
MOVEM T1,IMIB ;SAVE ADDRESS OF BUFFER
AOS T1 ;FIRST WORD TO READ INTO
TLO T1,(2B12) ;A WORD COUNT FIELD OF 2
MOVEM T1,IMPINP ;THIS IS THE FIRST DATAO TO ANXWAR
MOVE T1,[MSEC1,,IMIN0] ;SET STATE TO "WAITING FOR IMP TO GO"
MOVEM T1,IMIDSP
SETZM IMPIOV ;AND CLEAR "INPUT OVERFLOW" FLAG
CONSZ ANI,ANIIWD ;HAS IMP BEEN DOWN?
CALL IMIERR ;YES, BE SURE IT GETS NOTICED
CONO ANI,ANICLE+ANXWAR+ANXCHS ;TELL IMP WE ARE READY TO GO.
RET ;IT WILL INTERRUPT ON FIRST BIT TO US
;PI SERVICE FOR INPUT
;DISPATCHED AT IMPSV TO ONE OF THE FOLLOWING:
;IMIN0: FIRST BIT FLOWED, NEED TO SET WD CT AND ADDRESS.
;IMIN1: FIRST TWO WORDS OF MSG
;IMIN2: SECOND WORD OF MSG - NOT USED - IMIN1 READS TWO WORDS
;IMIN3: BODY OF MESSAGE HAS COME IN
;IF ANIDON IS ON, THEY GO TO IMPEIN FOR END OF INPUT HANDLING.
;IMIN0
;HERE WHEN INPUT HAS BEEN IDLE AND IMP STARTS TO SEND BITS. THIS
;FIRST INTERRUPT REQUIRES US TO SEND OVER WD COUNT AND ADDRESS.
;THE FIRST WORD COUNT WILL BE TWO, TO READ JUST THE IMP-TO-HOST
;LEADER PLUS SECOND 36 BITS.
IMIN0: CONSO ANI,ANIMRQ ;MESSAGE REQUEST IS ONLY VALID BIT
JRST IMIN0X ;IT WASN'T THAT. SOMETHING WIERD.
MOVEM T1,IMIDSP ;SAVE AC T1, PREPARE T