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; KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986 V2A(442) MICRO %37(277) Page TOC-1
; Table of Contents
; 1 KLX.MIC[4,24] 15:48 8-Mar-86
; 1 KL10 Microcode with KL Paging
; 12 EDHIS.MIC[4,24] 12:02 29-May-86
; 29 REVISION HISTORY
; 1228 DEFINE.MIC[4,24] 16:58 23-May-86
; 1229 CONDITIONAL ASSEMBLY VARIABLE DEFINITIONS
; 1316 HOW TO READ THE MICROCODE -- FORMATS & CONSTRUCTS
; 1519 MICROCODE LISTING TEMPLATE
; 1570 KL10 INSTRUCTION OPCODE MAP
; 1626 CONTROL RAM DEFINITIONS -- J, AD
; 1682 CONTROL RAM DEFINITIONS -- DATA PATH MIXERS
; 1750 CONTROL RAM DEFINITIONS -- 10-BIT LOGIC
; 1783 CONTROL RAM DEFINITIONS -- SHIFT, ARMM, VMA, TIME
; 1815 CONTROL RAM DEFINITIONS -- MEM SPECIAL FUNCTIONS
; 1838 CONTROL RAM DEFINITIONS -- SKIP/COND SPECIAL FUNCTIONS
; 1918 CONTROL RAM DEFINITIONS -- DISP/SPEC SPECIAL FUNCTIONS
; 1963 CONTROL RAM DEFINITIONS -- MAGIC NUMBER FIELD
; 2255 DISPATCH RAM DEFINITIONS
; 2308 MACRO.MIC[4,24] 11:59 29-May-86
; 2309 CRAM Macros--Miscellaneous and A
; 2348 CRAM Macros--AR
; 2572 CRAM Macros--AR Miscellaneous, ARL, and ARR
; 2651 CRAM Macros--ARX
; 2760 CRAM Macros--B, C, D
; 2839 CRAM Macros--E, F
; 2935 CRAM Macros--G, H, I, J, L
; 3043 CRAM Macros--M, N, O, P
; 3155 CRAM Macros--R
; 3211 CRAM Macros--S
; 3415 CRAM Macros--T, U, V, W, X
; 3506 DRAM Macros
; 3577 BASIC.MIC[4,24] 11:56 29-May-86
; 3578 THE INSTRUCTION LOOP
; 3679 NEXT INSTRUCTION DISPATCH
; 3810 EFFECTIVE ADDRESS COMPUTATION AND OPERAND FETCH
; 3847 WAIT FOR (E)
; 3891 TERMINATION
; 3944 MOVE GROUP, EXCH, XMOVEI, XHLLI
; 3998 Physical MOVE Instructions--PMOVE, PMOVEM
; 4027 DMOVE, DMOVN, DMOVEM, DMOVNM
; 4083 HALFWORD GROUP
; 4227 BOOLEAN GROUP
; 4374 SKPJMP.MIC[4,24] 11:57 29-May-86
; 4375 TEST GROUP
; 4483 COMPARE -- CAI, CAM
; 4509 ARITHMETIC SKIPS -- AOS, SOS, SKIP
; 4559 CONDITIONAL JUMPS -- JUMP, AOJ, SOJ, AOBJ
; 4615 AC DECODE JUMPS -- JRST
; 4722 HALT LOOP
; 4746 AC DECODE JUMPS -- JFCL
; 4764 MAP
; 4789 STACK INSTRUCTIONS -- PUSHJ, PUSH, POP, POPJ
; 4864 SUBROUTINE CALL/RETURN -- JSR, JSP, JSA, JRA
; 4897 UUO'S
; 5112 JSYS, ADJSP, XCT, PXCT
; KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986 V2A(442) MICRO %37(277) Page TOC-2
; Table of Contents
; 5151 SHIFT.MIC[4,24] 16:52 3-Apr-86
; 5152 Rotate and Logical Shift -- LSH, ROT
; 5199 Rotate and Logical Shift Combined (ROTC, LSHC)
; 5245 Arithmetic Shifts (ASH, ASHC) and JFFO
; 5339 ARITH.MIC[4,24] 16:07 19-Mar-86
; 5340 ADD, SUB
; 5365 MUL, IMUL
; 5421 MULTIPLY SUBROUTINE
; 5469 DIV, IDIV
; 5522 INTEGER DIVIDE SUBROUTINE
; 5585 BASIC DIVIDE LOOP
; 5634 DOUBLE INTEGER ARITHMETIC -- DADD, DSUB, DMUL, DDIV
; 5752 FP.MIC[4,24] 15:33 8-Feb-86
; 5753 SINGLE FLOATING ADD & SUB -- FAD, FADR, FSB, FSBR
; 5833 SINGLE FLOATING MULTIPLY -- FMP, FMPR
; 5877 SINGLE FLOATING DIVIDE -- FDV, FDVR
; 6004 UFA, DFN, FSC
; 6055 FIX, FIXR, FLTR
; 6101 SINGLE PRECISION FLOATING NORMALIZATION
; 6242 DOUBLE FLOATING ARITHMETIC -- DFAD, DFSB, DFMP, DFDV
; 6371 DOUBLE PRECISION NORMALIZATION
; 6417 EXTEXP.MIC[4,24] 15:33 8-Feb-86
; 6418 GFLT DOUBLE PRECISION ARITHMETIC
; 6536 GFLT MULTIPLY
; 6583 GFLT DIVIDE
; 6626 GFLT NORMALIZATION
; 6769 GFLT TO INTEGER CONVERSION
; 6895 GFLT DATA CONVERSION INSTRUCTIONS
; 7104 BLT.MIC[4,24] 16:34 23-May-86
; 7105 BLT - Neatly Optimized
; 7241 XBLT--Also Neatly Modernized
; 7333 BYTE.MIC[4,24] 17:29 14-Mar-86
; 7334 Single Byte Instructions: ILDB, LDB
; 7451 Single Byte Instructions: DPB, IDPB
; 7558 Single Byte Instructions: IBP, ADJBP
; 7765 Subroutines for Single Byte Instructions
; 7933 BYTSUB.MIC[4,24] 14:19 22-May-86
; 7934 BYTE GROUP -- Some Old Style Subroutines
; 7943 INCREMENT BYTE POINTER SUBROUTINE
; 7957 BYTE EFFECTIVE ADDRESS EVALUATOR - XADDR
; 7984 Load and Deposit Byte Subroutines
; 8030 EIS.MIC[4,24] 10:37 27-May-86
; 8031 EXTENDED INSTRUCTION SET DECODING
; 8171 ONE WORD GLOBAL BYTE POINTER SUBROUTINES FOR EXTEND
; 8234 EIS -- STRING MOVE
; 8353 EIS -- STRING COMPARE
; 8419 EIS -- DECIMAL TO BINARY CONVERSION
; 8488 EIS -- BINARY TO DECIMAL CONVERSION
; 8645 EIS -- SRCMOD SUBROUTINE TO GET MODIFIED SOURCE BYTE
; 8818 EIS -- EDIT FUNCTION
; 9016 IO.MIC[4,24] 15:27 17-Mar-86
; 9017 I/O INSTRUCTIONS
; 9116 EXTERNAL DEVICE I/O INSTRUCTIONS
; 9208 INTERNAL DEVICE FUNCTIONS -- APR, CCA
; 9262 INTERNAL DEVICE FUNCTIONS -- PI
; KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986 V2A(442) MICRO %37(277) Page TOC-3
; Table of Contents
; 9316 INTERNAL DEVICE FUNCTIONS -- PAG
; 9423 INTERNAL DEVICE FUNCTIONS -- TIM & MTR
; 9531 PRIORITY INTERRUPT PROCESSING
; 9682 KL-MODE PAGE REFILL LOGIC
; 10046 Page Fail Cleanup and Special Instruction Dispatch
; 10137 PAGE FAIL/INTERRUPT CLEANUP FOR SPECIAL INSTRUCTIONS
; Cross Reference Index
; DCODE Location / Line Number Index
; UCODE Location / Line Number Index
; KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986 V2A(442) MICRO %37(277) Page 1
; KLX.MIC[4,24] 15:48 8-Mar-86 KLX.MIC[4,24] 15:48 8-Mar-86
; 1 .TOC "KL10 Microcode with KL Paging"
; 2
; 3 .SET/SNORM.OPT=1
; 4 .SET/FPLONG=0
; 5 .SET/EXTEXP=1
; 6 .SET/MULTI=1 ;DOES NOT CACHE PAGE TABLE DATA
; 7 .SET/NOCST=1 ;DOES NOT DO AGE UPDATES, ETC. WITH CST = 0
; 8 .SET/OWGBP=1 ;ONE WORD GLOBAL BYTE POINTERS
; 9 .SET/IPA20=1 ;IPA20-L
; 10 .SET/GFTCNV=0 ;DO NOT DO GFLOAT CONVERSION INSTRUCTIONS [273]
; 11 ;SAVES 75 WORDS. MONITOR WILL TAKE CARE OF THEM.
; 12
; KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986 V2A(442) MICRO %37(277) Page 1
; EDHIS.MIC[4,24] 12:02 29-May-86 KLX.MIC[4,24] 15:48 8-Mar-86
; 13 .NOBIN
; 14
; 15 ; THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT
; 16 ; NOTICE AND SHOULD NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL
; 17 ; EQUIPMENT CORPORATION. DIGITAL EQUIPMENT CORPORATION ASSUMES NO
; 18 ; RESPONSIBITY FOR ANY ERRORS THAT MAY APPEAR IN THIS DOCUMENT.
; 19 ; THE SOFTWARE DESCRIBED IN THIS DOCUMENT IS FURNISHED TO THE
; 20 ; PURCHASER UNDER A LICENSE FOR USE ON A SINGLE COMPUTER SYSTEM AND
; 21 ; CAN BE COPIED (WITH INCLUSION OF DIGITAL'S COPYRIGHT NOTICE) ONLY
; 22 ; FOR USE IN SUCH SYSTEM, EXCEPT AS MAY OTHERWISE BE PROVIDED IN WRITING
; 23 ; BY DIGITAL.
; 24 ; DIGITAL EQUIPMENT CORPORATION ASSUMES NO RESPONSIBILITY FOR THE
; 25 ; USE OR RELIABILITY OF ITS SOFTWARE ON EQUIPMENT THAT IS NOT SUPPLIED
; 26 ; BY DIGITAL.
; 27 ; COPYRIGHT (C) 1975,1976,1977,1978,1979,1980,1981,1982,1983,1984,1985,1986 DIGITAL EQUIPMENT CORPORATION
; 28
; 29 .TOC "REVISION HISTORY"
; 30
; 31 ; The following collection of people have contributed to the
; 32 ; production and maintenance of this code. In reverse chronological
; 33 ; order:
; 34 ;
; 35 ; QQSV (Dick Wagman) -- beginning with edit 301
; 36 ; Sean Keenan
; 37 ; Don Dossa
; 38 ; Mike Newman
; 39 ; Jud Leonard
; 40 ;
; 41 .TITLE "KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986"
; 42 .VERSION/MAJOR=2/MINOR=1/EDIT=442/WHO=0
; 43 ;REV WHY
; 44 ;
; 45 ;442 29 May 86--Clean up the listing a bit in a few miscellaneous places.
; 46 ; Rewrite the SETCA group to use AR_AC0 COMP (looks more obvious than
; 47 ; the previous stuff). Avoid the write test for HRRZM, using the last
; 48 ; remaining microword to optimize it. This looks like the last edit
; 49 ; from QQSV. So long, everybody. It's been real!
; 50 ;441 27 May 86--An afterthought edit. Move DB2WD in line with CVTDBx
; 51 ; code, and use the space to make JUMPA fetch faster. This required
; 52 ; moving the TDN dispatch block as well due to DRAM constraints.
; 53 ;440 23 May 86--A final omnibus speedup edit. Add an instruction to allow
; 54 ; TLO/TSO/TLZ/TSZ/TLC/TSC to prefetch. Special case AOJ, AOJA, SOJ,
; 55 ; SOJA, AOS, and SOS to speed the next instruction fetch in all cases.
; 56 ; Allow JFCL 0, to take a fast path. Make MOVES, SKIP, HLLS, and HRRS
; 57 ; all use new code that starts the instruction fetch a fair amount
; 58 ; quicker in a few cases. Juggle the DRAM for all adjacent instructions,
; 59 ; and reconfigure the explicit CRAM addresses where necessary.
; 60 ;437 22 May 86--Make MOVSO and MOVST start the I FETCH a few micro-
; 61 ; instructions later when they abort. A page fault on the I FETCH was
; 62 ; leaving the SR set, and resulted in random garbage ending up in AC0.
; 63 ; Merge GTST and CNV2WD into TST2WD, saving a few words and a little bit
; 64 ; of time.
; 65 ;436 17 Apr 86--Back off optimization of JRSTF. Going to user mode doesn't
; 66 ; set USER in time for the FETCH to occur on the same microinstruction.
; 67 ;435 14 Apr 86--Install bit 4 of APRID as PMOVE present option bit.
; 68 ;434 7 Apr 86--Edit PMOVE and PMOVEM onto proper op codes.
; KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986 V2A(442) MICRO %37(277) Page 1-1
; EDHIS.MIC[4,24] 12:02 29-May-86 REVISION HISTORY
; 69 ;433 4 Apr 86--Edit new JFFO onto proper op code. Install prototype PMOVE
; 70 ; and PMOVEM, using op codes 100 and 101 for now.
; 71 ;432 1 Apr 86--Edit new ADJSP onto proper op code. Rewrite JFFO to isolate
; 72 ; the bit number within a group more quickly, and install it on op codes
; 73 ; 100 and 101 for debugging.
; 74 ;431 31 Mar 86--Rewrite ADJSP to start the I FETCH several cycles earlier
; 75 ; by not using PUSH code to set TRAP2.
; 76 ;430 20 Mar 86--Start the I FETCH for IMULB, IDIVB, and friends at ST2AC+1
; 77 ; by making it use the DSHIFT code. Eliminate the EXIT DBL macro as
; 78 ; obsolete. Move the op code 247 dispatch in with other UUOs in
; 79 ; SKPJMP. Knock a cycle out of SETMM and SETMB by making them go
; 80 ; directly to IFNOP and IFSTAC. (This is pretty useless, but
; 81 ; harmless and correct.) Make a few cosmetic edits.
; 82 ;427 18 Mar 86--Install rewritten XBLT in production form, and eliminate
; 83 ; old code. This makes the BLT file entirely new code. Make room
; 84 ; for this by rewriting effective address decodes for EXTEND sub
; 85 ; op and for byte pointer in string instructions, making use of
; 86 ; indirection decoder used for single byte instructions. (Note that
; 87 ; this could impact the PXCTability of EXTEND op codes, but since
; 88 ; only XBLT is supposed to be PXCTed, this should never matter.) In
; 89 ; the process, fix bug where indirection in byte pointer calculations
; 90 ; was taking interrupt without going to CLEAN first. Also fix bug in
; 91 ; LDB of an illegal OWG, where an LDB of an OWG with a P&S field of
; 92 ; (for example) 45 was not properly clearing the right half. This
; 93 ; was introduced when we rewrote SETZ.
; 94 ;426 13 Mar 86--Rewrite XBLT. Implement it on opcodes 100 and 101 for
; 95 ; debugging convenience.
; 96 ;425 8 Mar 86--Install optimized BLT. Eliminate obsolete conditionals
; 97 ; BACK.BLT, BLT.PXCT, and RPW (not related) in the process.
; 98 ;424 17 Feb 86--Remove IMULM and IMULB from IMULx optimization, allowing
; 99 ; IMUL and IMULI to begin their I FETCH one microinstruction earlier.
; 100 ; Fix ADJBP of a TWG with byte size zero to correctly load both
; 101 ; halves of the byte pointer (at TWGCPY+1). Reedit BYTSUB.MIC to
; 102 ; remove a few extraneous words that are no longer needed now that
; 103 ; the single byte instructions have been rewritten.
; 104 ;423 13 Feb 86--Install upgraded ASH code. Reedit ASHC to remove code
; 105 ; used only by ASH previously.
; 106 ;422 29 Jan 86--Rework speeded IDIVx code onto the proper opcodes, and
; 107 ; delete old IDIVx code. Reedit a few instructions in that vicinity
; 108 ; to clean up the listing, and remove references to NODIVD label by
; 109 ; making those instructions do SET NO DIVIDE on their own.
; 110 ;421 23 Jan 86--Force the SETZ group to use HLLZ code, saving a word.
; 111 ; Make sure DMOVNM loads both halves of AC1 when it starts.
; 112 ; Implement speeded up IDIVx on opcodes 100 and 101 for easy debugging.
; 113 ;420 21 Jan 86--Add logic to the integer divide instructions to enable
; 114 ; generating the maximum negative number as a quotient. This is
; 115 ; in preparation for the IDIVx optimization.
; 116 ;417 10 Jan 86--Prevent ROT from (sometimes) clobbering the next
; 117 ; instruction in ARX on a short right rotation (the timing was
; 118 ; close, so it worked most of the time--very bad). Costs a
; 119 ; microword (sigh).
; 120 ;416 7 Dec 85--Rewrite IMULx to do what the old IMULI.OPT should have
; 121 ; done, namely, optimize IMULx of a positive by a positive when
; 122 ; we can be sure that no overflow will occur. Costs five words,
; 123 ; only two more than the original (broken) IMULI.OPT. Eliminate
; 124 ; that conditional as obsolete.
; KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986 V2A(442) MICRO %37(277) Page 1-2
; EDHIS.MIC[4,24] 12:02 29-May-86 REVISION HISTORY
; 125 ;415 7 Dec 85--Rewrite LSHC and ROTC (at a cost of one word), saving
; 126 ; some time, particularly on right rotates and shifts.
; 127 ;414 5 Dec 85--Rewrite the JRST group, not affecting speed very much
; 128 ; but saving many microwords in the process. Shuffle MOVMI dispatch
; 129 ; to make it identical to HRRZI, saving a bit of time. Work on UUO
; 130 ; code to save some space. Crack a couple of words out of JRA,
; 131 ; speeding it up (almost in spite of ourselves). Force old EIS
; 132 ; effective address dispatch to exit to 3177 instead of 3077, releasing
; 133 ; 3077 for other uses. Knock another word out of POPJ. Make PF24
; 134 ; go directly to PFPAR, saving a cycle for illegal indirect page
; 135 ; faults (and buying back three words in the process). Edits 234,
; 136 ; 242, and 271 appear ill conceived. Fix ARL IND and TIME fields
; 137 ; for second counting loop in JFFO, buying a little free speed.
; 138 ; Rework dispatches for FAD/FSB/FMP/FDV, and fix FPLONG conditional,
; 139 ; saving a couple of words and making FADL/FSBL/FMPL/FDVL work when
; 140 ; the conditional is turned on. Also twiddle definitions of EXP_SIGN
; 141 ; macros to fix a couple of conflicts. Make FMPRI and FDVRI go to
; 142 ; same spot, as well as FDVx and FMPx, saving a couple of words.
; 143 ;413 24 Sept 85--Continue the cleanup/speedup begun in 412. Rewrite LSH
; 144 ; and ROT, spending some CRAM for speed. Rework the DMOVxx group to
; 145 ; minimize the memory dead time for DMOVE and DMOVEM, particularly.
; 146 ; Prevent SETA from referencing memory (useless, but harmless and
; 147 ; correct). Squeeze words out of POP and POPJ. There are some old
; 148 ; tailings from the DMOVxx code left for use by floating point and
; 149 ; IO code; it would be nice to clean them up.
; 150 ;412 12 Sept 85--Freeze work on strings and start doing cleanup and
; 151 ; speedup on other (simpler) instructions. Move around DRAM and
; 152 ; first words of several instructions (e.g., BLT, EXTEND, XCT,
; 153 ; and several EXTEND sub ops) so that instructions don't jump around
; 154 ; from place to place so much. Decommit obsolete conditionals WRTST,
; 155 ; XADDR, EPT540, LONG.PC, MODEL.B, KLPAGE, SMP, SHIFT.MUUO, SXCT,
; 156 ; PUSHM, EXTEND, DIAG.INST, and DBL.INT--we haven't supported one
; 157 ; side or the other of these for a long time, in some cases.
; 158 ; Rework all noops and pure skips to use the same code as TRN and
; 159 ; TRNA. Make TRO, TDO, TRC, TDC, TRZ, and TDZ use the equivalent
; 160 ; boolean code. Make SETAM and SETAB equivalent to MOVEM. Save a
; 161 ; cycle in MOVN by having it exit directly without going through MOVE.
; 162 ; All of this involves moving some code around in a few cases. Clean
; 163 ; up the listings a bit.
; 164 ;411 24 July 85--Another try at the SMP fix. PI cycle 7 must go to
; 165 ; memory for interlock to work, so delete use of the cache on the
; 166 ; PHYS REF. This may have performance drawbacks for TOPS-20 and
; 167 ; TOPS-10 uniprocessor, so there may have to be two versions of
; 168 ; microcode (again!) to resolve this.
; 169 ;410 11 July 85--Force PI functions 3 and 7 to use RPW cycles, so
; 170 ; SMP will work properly. Save a couple words in the process.
; 171 ;407 18 June 85--Change macro ARX_2 to ARX_2+MQ0 and fix related bug
; 172 ; in ADJBP by clearing MQ on entry to instruction. This prevents
; 173 ; ADJBP from computing the wrong byte capacities for OWGs with
; 174 ; byte sizes of 6 and 18. Also reverse AC1 and AC2 in DB2WD.
; 175 ; That was causing CVTDBx to reverse the byte pointer halves if
; 176 ; an OWG was used, ruining things entirely.
; 177 ;406 11 Mar 85--Define R17 as HARDPFW, and save the hard page fail word
; 178 ; there for TOPS-10, thus protecting it from getting clobbered by a
; 179 ; later soft page fail.
; 180 ;405 15 Jan 84--Finish initial installation of rewritten MOVSLJ and
; KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986 V2A(442) MICRO %37(277) Page 1-3
; EDHIS.MIC[4,24] 12:02 29-May-86 REVISION HISTORY
; 181 ; MOVSO code. Also, remove obsolete conditional code for SXCT and
; 182 ; SHIFT.MUUO, and for the .IFNOT cases of LONG.PC, MODEL.B, XADDR,
; 183 ; DBL.INT, EXTEND, and EPT540. Remove some code from IBPS (not
; 184 ; needed by DTE support), and an obsolete constraint above PGRST1.
; 185 ; Also put all statistics code into separate assembly. As currently
; 186 ; implemented, the statistics code won't fit into CRAM without removing
; 187 ; something else.
; 188 ;404 12 Oct 84--Fix THAW so that source VMA doesn't get complemented
; 189 ; for OWGs.
; 190 ;403 9 Oct 84--Special case the null destination length so that the
; 191 ; byte pointers don't get clobbered when nothing gets done.
; 192 ;402 5 Oct 84--Fix byte counting in OWG decode subroutine so that
; 193 ; references to the zeroth byte don't force the pointer forward
; 194 ; one word (shifting P can't easily sign extend here). Do this by
; 195 ; forcing PLOOP to loop one extra time.
; 196 ;401 5 Oct 84--Add code to support OWGs for version 2 MOVSLJ.
; 197 ;400 9 Aug 84--Initial first edit number for releasable version 2.0.
; 198 ;377 9 Aug 84--All of these are reserved (somewhat paranoically, I think)
; 199 ; . for version 1 as well. The likelihood of them actually being used
; 200 ;360 is vanishingly small!
; 201 ;357 9 Aug 84--Add the 136 location constraint (forgotten in 356).
; 202 ;356 8 Aug 84--Make the # field of location 136 contain the major and
; 203 ; minor version numbers. Grab a random instruction with no # field
; 204 ; in use to do this.
; 205 ;355 29 May 84--Make BPEA hang on to the original Y field when doing
; 206 ; the EA calculation for an OWL which does not overflow to the next
; 207 ; word. Untangle copy length calculation, which was confusing
; 208 ; source and destination lengths. Fix generation of fill count in
; 209 ; loop (a decimal number used where octal was needed). Make sure
; 210 ; that the fill character gets stored the first time through the fill
; 211 ; loop. Build the final source count from the proper numbers (not
; 212 ; from a byte pointer!). Fix the test for storing the final buffer
; 213 ; if no filling was required. Force the final destination byte pointer
; 214 ; Y field to the proper value by making IDSTMA be the actual first
; 215 ; destination VMA, saving two words in the process.
; 216 ;354 25 May 84--Implement recoded version of MOVSLJ. Temporarily
; 217 ; decommit the G floating instructions in order to make room for it.
; 218 ;353 21 May 84--LDB and DPB in version 1 were leaving state register bit
; 219 ; 3 set when the byte word was loaded, resulting in the page fault
; 220 ; handler treating it as if it were a string instruction and trying
; 221 ; to back up a byte pointer in AC1 when the reference page faulted.
; 222 ; Cure it by reseting the state register in GBYTE. (Sure hope this
; 223 ; is the last bug in version 1!)
; 224 ;352 4 Apr 84--It turns out that the string instructions had the same
; 225 ; problem as the byte instructions in 351! Copy AR to ARX one
; 226 ; cycle earlier in both GRSC2 and IDST to fix it. Also make sure
; 227 ; that all byte pointers default to PC section by initializing VMA
; 228 ; to PC on all calls to both of these routines. This cleans up edit
; 229 ; 300.
; 230 ;351 12 Mar 84--When ILDB or IDPB incremented a one word local pointer
; 231 ; in such a way that the low half word changed sign, the section
; 232 ; computation for the byte address would get screwed up if the
; 233 ; index AC had a global address. Fix this by copying the updated
; 234 ; pointer into ARX, thus forcing EA MOD DISP to look at the proper
; 235 ; bit in ARX18.
; 236 ;350 15 Feb 84--Fix indexed indirection byte pointer effective address
; KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986 V2A(442) MICRO %37(277) Page 1-4
; EDHIS.MIC[4,24] 12:02 29-May-86 REVISION HISTORY
; 237 ; calculations to load the indirect word into both AR and ARX.
; 238 ;347 20 Jan 84--Rewrite the MVST and CMPS dispatches to test for illegal
; 239 ; bits in the lengths before BRX gets smashed. UUO was reporting a
; 240 ; bogus op code in these situations.
; 241 ; Turn on BIG.PT by default, since it should work with both old and
; 242 ; new software and hardware.
; 243 ;346 18 Jan 84--Fix the .IFNOT variation of BIG.PT to clear the Keep
; 244 ; bit if anybody sets it. This was introduced in 343.
; 245 ; Add the DDT.BUG conditional. Under it, rewrite APRID to move
; 246 ; bit 23 to bit 5 if it is set in the serial number. This is a
; 247 ; piece of garbage which I hope can disappear soon (it seems EDDT
; 248 ; used the serial number to test for a KS-10!).
; 249 ; Fix the time field on the page map word type dispatch (the assembler
; 250 ; default was too high). Also make the PAGCNT conditional hang on
; 251 ; to the original AR value after it counts the PFH entry (this would
; 252 ; only matter for an AR parity error). Rename AR and ARX defaults to
; 253 ; MEM for the AR_MEM and ARX_MEM macros, respectively.
; 254 ;345 6 Dec 83--Clean up all the pieces and integrate the new byte
; 255 ; instruction implementation into the rest of the microcode. Also
; 256 ; add the FIN LOAD macro (more mnemonic than FIN XFER, its equivalent)
; 257 ; and include AR/AR on AR_MEM and ARX/ARX on ARX_MEM, as those macros
; 258 ; really don't work unless those fields take their default. This
; 259 ; version marks the first time that major chunks of code have been
; 260 ; bodily replaced; accordingly, with this edit the major version has
; 261 ; been bumped to 2.
; 262 ;344 1 Dec 83--Save CVTBDx fill character address, which was getting lost
; 263 ; if OWGBPs were in use, in a manner similar to that used in CMPSx
; 264 ; (see edit 310). Also, fix some conditionals for EXPMSK constant
; 265 ; generation, so that OWGBPs will assemble with EXTEXP off.
; 266 ;343 18 Nov 83--Install new code for IBP and ADJBP, saving time and
; 267 ; microwords.
; 268 ;342 8 Nov 83--Change definition of CLR PT LINE to be consistent with
; 269 ; new paging board (see also 333). Also, redefine bit 3 of effective
; 270 ; word to reverse keep sense (so unkept only pages are cleared when
; 271 ; bit 3 is set).
; 272 ;341 28 Sep 83--Force the ARX to contain the first byte pointer word on
; 273 ; exit from INCRBP so that subsequent EA MOD DISP wil work. Force
; 274 ; OWGs to explicitly wait for store to complete after increment
; 275 ; (unfortunately there is no implicit MB WAIT in MEM/EA CALC. Sorry!).
; 276 ;340 The OWG/OWL test for the byte instructions had the sense of the
; 277 ; test backwards in several places. Rework LDBDSP, INCRBP, and
; 278 ; DPBDSP. This makes it impossible for DPEA to test for a byte
; 279 ; off the top of a word on its return, so it has been desubroutinized.
; 280 ;337 15 Sep 83--Start work on a complete rewrite of all byte and character
; 281 ; instructions. Begin by installing initial versions of LDB, ILDB,
; 282 ; DPB, and IDPB. All of these are designed to make one word global
; 283 ; byte pointers run faster by loading their shift counts from CRAM
; 284 ; dispatch tables. Also, reduce time for DISP/SH0-3 to three ticks.
; 285 ; Move CDBLST into FP to allow EXTEXP conditional to be turned off.
; 286 ; Also, shuffle conditional placement to prevent EXTEXP shutoff from
; 287 ; turning off XBLT as well.
; 288 ;336 9 Aug 83--Back off 330 for a bit, since TOPS-10 7.02 must be tested
; 289 ; and OWGs in section 0 fail for string instructions (they get converted
; 290 ; to TWGs, which are illegal in section 0). For now, we will maintain
; 291 ; both sources.
; 292 ;335 Force memory to be released for SMP case of DPB if P > 36 causes no
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; EDHIS.MIC[4,24] 12:02 29-May-86 REVISION HISTORY
; 293 ; actual data to be stored. Make an OWG reference to an address >
; 294 ; 37,,777777 cause a page fail (GBYTE was stripping the excess bits).
; 295 ;334 Fix conflict generated in CLRPT by 333 by creating new subroutine
; 296 ; ARSWAP which is just AR_AR SWAP. Make several other routines call it,
; 297 ; thus saving a few words.
; 298 ;333 Add new conditional BIG.PT. Under it, add code to implement the "Keep
; 299 ; me" bit for paging as bit 5 of the page table, and to move it to page
; 300 ; map bit 23 during page refill. Also make DATAO PAG not clear Kept
; 301 ; pages if bit 3 of the word is off.
; 302 ;332 Redefine all bank 7 ACs as R0,...,R17, and all bank 6 ACs as P0,...,
; 303 ; P17. Change all other alias definitions to refer to these. This
; 304 ; gives us a uniform cross reference for all scratch register references.
; 305 ; Put all macro definitions into alphabetical order, making it easier
; 306 ; to look up a macro definition. Split the edit history into its own
; 307 ; file. There are no functional changes from 331.
; 308 ;331 Allow XSFM anywhere. Clean up the code a bit in the process. There
; 309 ; still remain a number of references to XSFM or XPCW distinctions,
; 310 ; and these could almost certainly be cleaned up further.
; 311 ;330 Allow one word global byte pointers in section zero. This includes
; 312 ; changes in BYTE, EIS, and FP. Change GBYTE and CNV2WD to return 2;
; 313 ; eliminate GTST as obsolete. Also shuffle the calls to these routines
; 314 ; to conform to the new calling conventions, and put the OWG test at
; 315 ; the beginning of IBP, ILDB, IDBP, LDB, DPB, and ADJBP.
; 316 ;327 Add PAGCNT conditional. Under it, include control to count entry
; 317 ; into PFH code and DATAO PAG with bit 2 set.
; 318 ;326 Change VMA restoration in INC2WD and CNV2WD (see edits 320 and 307)
; 319 ; to use RSTR VMA_MQ in order to keep the global/local sense of the
; 320 ; reference. This was causing ILDBs of OWGs in shadow memory to
; 321 ; save the incremented byte pointer in the ACs instead of memory.
; 322 ;325 Add VMA/LOAD to local indexed EA computation for EXTEND E1 to make
; 323 ; it read the section number from VMA instead of PCS (!) if the index
; 324 ; is section local.
; 325 ;324 Force the XADDR conditional to use RPW type references for DPB and
; 326 ; IDPB if the SMP conditional is on, even if one word globals are not
; 327 ; active.
; 328 ;323 Add missing constraint near NOT.WR, accidentally broken by 322.
; 329 ;322 Generate the A(cessible) bit in a page fail word caused by a read
; 330 ; violation if the page is otherwise accessible and if no CST is present.
; 331 ; This could be fixed for the CST present case as well, but has been
; 332 ; deferred since we are tight on space and no one seems to need it
; 333 ; anyway.
; 334 ;321 Prevent statistics microcode from losing traps by forcing NICOND
; 335 ; dispatch 11 to ignore the statistics and take the trap.
; 336 ;320 Restore the VMA again in INC2WD (broken by 307), since the state
; 337 ; register bits may have changed in the interim. This was causing
; 338 ; PXCT to do surprising things (mostly bad).
; 339 ;317 Originally, this was an attempt to uncount multiply counted op
; 340 ; codes which resulted from interrupts during long instructions.
; 341 ; That project has been shelved for now. Instead, the second
; 342 ; NICOND dispatch during op code counting has had its final constraint
; 343 ; fixed.
; 344 ;316 Make counting only version compatible with time and counting by making
; 345 ; counting only version use TRX2 and TRX3, removing physical contiguity
; 346 ; requirement.
; 347 ;315 Op code counting lives again! The setup code activated by DATAO PI
; 348 ; was attempting to write the TRX registers with data fresh from memory,
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; EDHIS.MIC[4,24] 12:02 29-May-86 REVISION HISTORY
; 349 ; resulting in parity checks when it was used (see edit 73, for example).
; 350 ; Juggle code to overlap next address calculation with parity wait.
; 351 ;314 Add CST.WRITE conditional to facilitate assembly of microcode
; 352 ; without the CST writable bit (see edit 303).
; 353 ;313 Put TIME/3T on XFERW, as the assembler was getting the wrong
; 354 ; value with both AR_MEM and ARX_MEM macros present.
; 355 ;312 Fix definition of BYTE RPW to include a write test. This was
; 356 ; causing the SMP version of DPB to hang when memory was readable
; 357 ; but not writable.
; 358 ;311 Make all IOP function 7 style of references look in the cache.
; 359 ;310 Improve the fix in 307 to save the computed E0+1 in FILL during
; 360 ; OWGBP conversion and to restore the VMA from there when done.
; 361 ; Also, make sure that the VMA is initialized to PC for all cases
; 362 ; when doing effective address calculations for two word globals
; 363 ; in string instructions. 307 was not enough to clean up the
; 364 ; CMPSx fill problem, since VMA HELD was never loaded.
; 365 ; Force EXT2WD to prereference AC4 and AC5 so that glitch discovered
; 366 ; for second edit 210 will not be activated.
; 367 ;307 Restore VMA from MQ at end of CNV2WD (and remove it from INC2WD,
; 368 ; saving a word in the process). This was causing CMPSx to load
; 369 ; a random fill word and MOVSLJ to store to a random place when the
; 370 ; source length was zero if one word globals were in use.
; 371 ; Force page fail code to look for ARX as well as AR parity errors
; 372 ; (now possible with BYTE RPW implemented).
; 373 ; Make sign extension of E1 go to right place in EXTEND decoding of
; 374 ; offset instructions (broken in 301).
; 375 ;306 Add University of Essex code to statistics (TRACKS) code to make
; 376 ; it work with address break enabled.
; 377 ;305 Fix CST write bit logic to not test bit 18 when reading.
; 378 ;304 Switch byte read interlock from LDB to DPB (broken in 303).
; 379 ;303 Implement bit 18 of a CST entry as a write enable bit in addition
; 380 ; to all the other write enable functions.
; 381 ; Knock one cycle out of byte deposit where the byte is being
; 382 ; deposited into the high order byte of a word.
; 383 ; Implement the SMP conditional for extended addressing by
; 384 ; replicating all the byte effective address calculation code for
; 385 ; DPB. This is unfortunate, but necessary due to the huge dispatch
; 386 ; table that ends this subroutine.
; 387 ;302 Move XFERW out of EIS (which no longer absolutely requires it
; 388 ; in line) into SKPJMP (more in the heart of things). Also
; 389 ; juggle comment lines and code layout to reduce the listing
; 390 ; size a bit and to force some of the .TOC lines into the table
; 391 ; of contents (even though the code nearby may be suppressed).
; 392 ;301 Fix ADJBP so that instructions which occur at the last word on
; 393 ; a page do not cause a page failure of some random type (one cycle
; 394 ; too many between I FETCH and NICOND).
; 395 ; Fix effective address calculation for EXTEND so that only offset
; 396 ; instructions (and not GSNGL, for example) will have E1 sign
; 397 ; smeared.
; 398 ; Implement XJRST. Also force JSP and JSR to do full 30 bit
; 399 ; effective address calculations.
; 400 ;300 ADD LOAD OF VMA FROM PC IN PUTDST TO GET THE SECTION ADDRESS
; 401 ; CORRECT ON THE STRING INSTRUCTIONS.
; 402 ;277 Add EA CALC table for SMP configurations of extended addressing
; 403 ; for TOPS-10. (TOPS-20 paging)
; 404 ;276 Force global EA CALC for EXTEND instructions in PUTDST.
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; EDHIS.MIC[4,24] 12:02 29-May-86 REVISION HISTORY
; 405 ;275 FIX THE ERROR CODE IN STRING COMPARE FOR ILLEGAL BITS IN THE
; 406 ; LENGTH FIELD. WAS CAUSING AR PARITY ERRORS.
; 407 ;274 SAVE THE API FUNCTION WORD ON AN IO PAGE FAIL INSTEAD OF THE
; 408 ; PAGE FAIL WORD. THIS TAKES PLACE IN BOTH THE AC BLK 7 AC 2
; 409 ; AND THE MONITOR.
; 410 ;273 PUT CONDITIONALS AROUND 4 GFLOAT CONVERSION INSTRUCTIONS.
; 411 ; THEY WILL ACT AS MUUO'S AND MONITOR WILL TAKE CARE OF THEM.
; 412 ;272 CONO APR 200000 AT TIMES WAS NOT GENERATING EBUS RESET OF A
; 413 ; SUFFICIENT LENGTH TO CLEAR DTE REGISTERS. ADDED ANOTHER
; 414 ; MICROWORD SO THAT CONO APR IS NOW UP FOR TWO FULL WORDS WHICH
; 415 ; GETS AROUND THE HARDWARE PROBLEM.
; 416 ;271 ILLEGAL INDIRECT PAGE FAIL (24) WAS NOT ALLOWING USER TO BE SET.
; 417 ;270 WHEN IN SECTIONS > 1, AN UPDATED OWGBP WOULD BE WRITTEN INTO
; 418 ; MEMORY INSTEAD OF THE AC'S.
; 419 ;267 CHANGED TESTS FOR OWGBP TO TEST FOR PC SEC0 FIRST. SAVES 33 NS.
; 420 ;266 CONDITIONALS ON FOR TOPS-20 DEVELOPMENT.
; 421 ;265 REMOVED EDIT 244. SOFTWARE ENGINEERING WILL SUPPLY MONITOR
; 422 ; CODE TO TAKE CARE OF PROBLEM. CODE COSTS TOO MUCH TIME IN
; 423 ; THE INSTRUCTION EXECUTION.
; 424 ;264 ADDED CONDITIONALS TO CODE FOR IPA20, OWGBP AND NO CST UPDATE IF
; 425 ; CBR IS ZERO. THIS IS FOR RELEASE 5 OF TOPS-20.
; 426 ;263 IBP DID NOT CLEAR FPD ON EXIT.
; 427 ;262 ALLOW XBLT TO BE VALID IN SECTION 0.
; 428 ;261 FIX CODE AT END OF ADJBP CODE TO CLEAR STATE REG. IF ILDB
; 429 ; WITH 2 WD GLOBAL POINTER POINTING TO ADDRESS NOT IN CORE
; 430 ; CLEAN DISPATCHES TO WRONG CODE BECAUSE SR LEFT OVER FROM
; 431 ; ADJBP.
; 432 ;260 FIX FM PARITY ERRORS AT MVF1: ADDED NULL CALL TO RET2:
; 433 ; AT MVST: TO TAKE CARE OF EXTRA TICK FOR PARITY.
; 434 ;257 MAKE SURE THAT THE UPDATED ONE WORD GLOBAL BYTE POINTER IS
; 435 ; WRITTEN BACK INTO THE CORRECT CONTEXT.
; 436 ;256 MAKE ANOTHER ATTEMPT TO FIX PXCT OF ONE WORD GLOBAL BYTE POINTERS.
; 437 ; THE GIBP CODE GETS THE SAME CHANGES AS EDIT 255.
; 438 ;255 MAKE ONE WORD GLOBAL BYTE POINTERS WORK WITH PXCT. THE STATE
; 439 ; REGISTER BITS ON MCL4 (NOT TO BE CONFUSED WITH CON3), WERE NOT
; 440 ; BEING SET PROPERLY TO ALLOW PREVIOUS ENA AND USER ENA TO BE SET.
; 441 ; GUARANTEE THAT THESE SR BITS ARE SET PRIOR TO THE LOAD OF THE VMA.
; 442 ;254 FIX PROBLEM WITH OWGBP WHERE FPD DOES NOT EFFECT
; 443 ; INC OF POINTER AFTER PAGE FAIL
; 444 ;253 FIXED ADDRESSING FOR SH DISP AT GADJL0:
; 445 ;252 MOVE STRING INSTRUCTIONS DO NOT GET THE CORRECT DATA ON
; 446 ; LOCAL POINTERS IN NON 0 SECTIONS
; 447 ;251 ADD CODE FOR ONE WORD GLOBAL BYTE POINTERS.
; 448 ; TOOK OUT EDITS 243 AND 250 TO GET ENOUGH SPACE IN CRAM
; 449 ; FOR THIS EDIT. OWGBP WITH EXTEND INSTRUCTIONS WILL NOT
; 450 ; RETURN A OWGBP. THEY WILL RETURN A TWO WORD GLOBAL BP.
; 451 ;250 ALLOW SMP SWITCH TO EFFECT TOPS-20 MODEL B TO DO RPW IN
; 452 ; BYTE INSTRUCTIONS.
; 453 ;247 DO NOT DO A CST UPDATE OR AGE UPDATE IF THE CBR IS ZERO.
; 454 ;246 EXTEND OP CODE DECODE FOR MODEL A WAS ACCEPTING MODEL B
; 455 ; OP CODES (20-31). ADDED CONDITIONALS TO CODE TO FIX.
; 456 ;245 FIX 2 WORD GLOBAL BYTE POINTER BUG WITH IBP INSTRUCTION
; 457 ; WITH EXTENDED ADDRESSING OUT OF SECTION 0
; 458 ;244 FIX MOVST EXTEND INST. SO THAT ILLEGAL (> 36) S FIELD
; 459 ; DOES NOT CAUSE STOP CODE TO CRASH SYSTEM FOR TOPS-10 MODEL B.
; 460 ;243 WRTIME TRIED TO DO MEM WRITE EVEN THOUGH THE INSTRUCTION
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; EDHIS.MIC[4,24] 12:02 29-May-86 REVISION HISTORY
; 461 ; DOES NOT DO ANYTHING TO MEMORY. CAUSED PROBLEMS IF THE MEMORY
; 462 ; LOCATION WAS NOT WRITABLE.
; 463 ;242 FIX CODE FROM EDIT 234 TO GET PF CODE OF 24.
; 464 ;241 FIX DFAD AND DFMP FOR ROUNDING OCCURS PROPERLY. ADDED STICKY
; 465 ; BIT FOR LEAST SIGNIFICANT BITS OF THE RESULT.
; 466 ;240 FIX GFLT INSTRUCTIONS GFIX AND DGFIX SO THEY WILL TRUNCATE NEGATIVE
; 467 ; NUMBERS IN THE CORRECT DIRECTION. THE MQ MUST BE ZERO BEFORE
; 468 ; THE ARX_2 MACRO IS INVOKED OR THE ARX MIGHT GET A 3 FROM MQ00.
; 469 ;237 ADD OPTION BIT FOR PV CPU IN THE APRID WORD AS IT IS DOCUMENTED
; 470 ; IN ALL OF THE HARDWARE DOCUMENTATION. SET THE BIT ACCORDING
; 471 ; TO THE MODEL.B OPTION SWITCH. IT WILL BE MAGIC NUMBER BIT 3.
; 472 ;236 ALLOW THE INTEGER DIVIDE OF THE LARGEST NEGATIVE NUMBER BY
; 473 ; PLUS ONE TO SUCCEED. THIS USED TO BE A DOCUMENTED RESTRICTION
; 474 ; THAT THIS OPERATION WOULD CAUSE AN OVERFLOW AND NO DIVIDE.
; 475 ;235 FIX JRA SO IT DOESN'T FALL INTO SECTION ZERO FROM A NON-ZERO
; 476 ; SECTION EVERY TIME BY WRITING THE PC SECTION INTO THE VMAX.
; 477 ;234 BUILD A PAGE FAIL CODE OF 24 WHEN AN ILLEGAL INDIRECT WORD
; 478 ; IS FOUND DURING THE EFFECTIVE ADDRESS CALCULATION IN
; 479 ; A NON-ZERO SECTION. THE PAGE FAIL CODE WAS PREVIOUSLY NOT
; 480 ; BEING REPORTED.
; 481 ;233 SAVE THE IOP FUNCTION WORD THAT APPEARS ON THE EBUS WHEN AN
; 482 ; EXTERNAL DEVICE INTERRUPTS THE CPU. SAVE THIS INFORMATION
; 483 ; ON EVERY INTERRUPT IN AC BLOCK 7, AC 3. THE CONTENTS
; 484 ; OF THIS AC WILL BE PRESERVED UNTIL THE NEXT INTERRUPT.
; 485 ; OPERATING SYSTEMS SHOULD SAVE THIS INFORMATION AS SOON AS POSSIBLE
; 486 ; IF ITS CONTENTS ARE TO BE RELIABLE AND MEANINGFUL.
; 487 ;232 ADDS 13 NEW INSRUCTIONS FOR SUPPORTING FORTRAN78 ON MODEL
; 488 ; B MACHINES. THESE INSTRUCTIONS ARE:
; 489 ; OPCODE SYMBOL
; 490 ; ====== ======
; 491 ; 102 GFAD AC,E
; 492 ; 103 GFSB AC,E
; 493 ; 106 GFMP AC,E
; 494 ; 107 GFDV AC,E
; 495 ; EXTEND INSTRUCTIONS EXTEND OPCODE
; 496 ; ====== ============ ====== ======
; 497 ; EXTEND AC,[GSNGL 0,E] 21
; 498 ; EXTEND AC,[GDBLE 0,E] 22
; 499 ; EXTEND AC,[DGFIX 0,E] 23
; 500 ; EXTEND AC,[GFIX 0,E] 24
; 501 ; EXTEND AC,[DGFIXR 0,E] 25
; 502 ; EXTEND AC,[GFIXR 0,E] 26
; 503 ; EXTEND AC,[DGFLTR 0,E] 27
; 504 ; EXTEND AC,[GFLTR 0,E] 30
; 505 ; EXTEND AC,[GFSC 0,E] 31
; 506 ;231 FIX IN PROBLEM IN EDIT 215 TO XDPB THAT PREVENTED THE KL
; 507 ; FROM HANDLING INTERRUPTS WHILE EVALUTAING AN INDEXED INDIRECT CHAIN.
; 508 ; AN "=0" WAS MISSING BY BYTEIP.
; 509 ;230 TO PRESERVE COMPATABILITY WITH THE KS10 AND BECAUSE OF SPACE
; 510 ; LIMITATIONS IN TOPS20 MODEL A, THE SPECIFICATION FOR THE
; 511 ; CVTDBX INSTRUCTIONS HAVE BEEN CHANGED TO ELIMINATE THE NEED
; 512 ; FOR AN OVERFLOW TEST DURING THE CONVERSION. THIS CHANGE
; 513 ; EFFECTIVELY REMOVES EDIT 221.
; 514 ;227 DELETE EDIT 222 AND RETURN THE CVTBDX INSTRUCTIONS TO THEIR
; 515 ; OLD, BROKEN FUNCTIONALITY SINCE ANY ATTEMPT TO PREVENT THE
; 516 ; FLAGS FROM BEING CHANGED PREMATURELY HAS TO CONTEND WITH
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; EDHIS.MIC[4,24] 12:02 29-May-86 REVISION HISTORY
; 517 ; INTERRUPTABILITY PROBLEMS. THE HARDWARE REFERENCE MANUAL
; 518 ; HAS A FOOTNOTE ABOUT THE FLAG PROBLEM SO THE CURRENT FUNCTIONALITY
; 519 ; IS DOCUMENTED FOR USERS.
; 520 ;226 PREVENT AR PARITY ERRORS WHEN INCREMENTING BYTE POINTERS IN THE ACS.
; 521 ;225 THE CODE TO SUPPORT THE MX20 VIA THE SBUS DIAG LOOP MECHANISM
; 522 ; DOES NOT TIME OUT CORRECTLY BECAUSE THE LOOP COUNTER IS BEING
; 523 ; REINITIALIZED EVERY TIME THROUGH THE LOOP. FIX THIS PROBLEM
; 524 ; EVEN THOUGH THE CODE IS NOT ASSEMBLED IN CURRENT RELEASES.
; 525 ;224 FIX BUG IN EDIT 223 THAT CAUSED THE WRONG PAGE FAIL
; 526 ; WORD TO BE WRITTEN WHEN AN I/O PAGE FAIL OCCURS.
; 527 ;223 WHEN A MEMORY PARITY ERROR OCCURRS AT PI LEVEL, AS EVIDENCED
; 528 ; BY AN AR DATA PARITY ERROR, THE DTE MAY BE WAITING FOR A
; 529 ; RESPONSE. IF IT IS, A DEX FAILURE WILL OCCUR UNLESS WE CAUSE
; 530 ; DEMAND TO WIGGLE. WE CAN DO THIS BY FORCING THE DATA IN THE
; 531 ; AR OVER THE EBUS.
; 532 ;222 CVTBDX IS NOT SUPPOSED TO CHANGE THE CONTENTS OF THE ACS
; 533 ; OR MEMORY IF THE CONVERTED NUMBER WILL NOT FIT INTO THE
; 534 ; DESTINATION FIELD. IT WAS, HOWEVER, CHANGING THE FLAGS
; 535 ; BEFORE IT KNEW IF THE NUMBER WOULD FIT.
; 536 ;221 THE CVTDBX WERE FAILING TO SET OV AND TRAP1 WHEN THE
; 537 ; CONVERTED DECIMAL NUMBER WOULD NOT FIT INTO A
; 538 ; DOUBLE WORD.
; 539 ;220 THE TRANSLATE INSTRUCTIONS WERE USING A 15 BIT WIDE
; 540 ; FIELD FOR THE REPLACEMENT BYTE IN THE TRANSLATE TABLE
; 541 ; WHILE THE SPECIFICATION STATED THAT THE TRANSLATE
; 542 ; INSTRUCTIONS WOULD USE ONLY 12 BITS.
; 543 ;217 PREVENT CRAM PARITY ERRORS CAUSED BY DISPATCHING TO LOCATION
; 544 ; 3042 WHEN INDEXING IS SPECIFIED IN THE EFFECTIVE ADDDRESS
; 545 ; CALCULATION OF E1 WHEN THE EXTEDED OPCODE IS ZERO (ILLEGAL).
; 546 ; THE FIX IS TO PUT A JUMP TO UUO AT 3042.
; 547 ;216 CHANGE THE DEFAULT VALUE FOR THE SMP SWITCH TO BE ONE. THIS
; 548 ; CAUSES THE MICROCODE TO INCLUDE SMP SUPPORT BY DEFAULT.
; 549 ;215 CHANGES DPB INSTRUCTION TO R-P-W CYCLE ON DATA FETCH PORTION OF
; 550 ; INSTRUCTION TO SOLVE AN INTERACTION PROBLEM IN AN SMP OPERATING
; 551 ; SYSTEM. THIS CHANGE ONLY APPLIES TO MICROCODES FOR TOPS-10
; 552 ; AND TOPS-20, MODEL A.
; 553 ;214 ADDED CHANGES FOR XADR, RELEASE 4 AS FOLLOWS.
; 554 ; STORE PREVIOUS CONTEXT SECTION (PCS) IN FLAGS WORD (BITS 31-35)
; 555 ; IF EXEC MODE AND XSFM OR XPCW INSTRUCTION,MUUO OR PAGE FAIL.
; 556 ; RESTORE PCS FROM FLAGS WORDS (BITS 31-35) WHEN XJRSTF OR XJEN
; 557 ; IS EXECUTED IN EXEC MODE AND THE NEW PC IS ALSO IN EXEC MODE.
; 558 ;213 SET/FPLONG=0 PARAMETER ADDED TO TOPS-10 MICROCODE FOR KL MODEL
; 559 ; A AND MODEL B.
; 560 ;212 CHANGE THE CODE AT LDIND: TO TEST FOR USER MODE IF USER MODE
; 561 ; TURN OFF SPECIAL CYCLE THAT MAY STILL BE ON. THE MICROCODE WILL DEPEND
; 562 ; ON KERNAL PROGRAMS TO NOT GET IN PAGE POINTER
; 563 ; LOOPS. INSTRUCTIONS EXECUTED FROM THE CONSOLE WILL NOT WORK.
; 564 ; PI INSTRUCTIONS GET A RESTRICTION TO NOT GET INDIRECT PAGE POINTERS
; 565 ; IN THEIR PAGING CHAIN AS DO EXAMINES AND DEPOSITS AND BYTE TRANSFERS.
; 566 ;211 CHANGE THE TEST FOR INDIRECT POINTERS TO NOT HAPPEN ON SECTION
; 567 ; POINTERS AND JUST ON INDIRECT PAGE POINTERS. AT LDIND:+1 AND LDIMM:+2
; 568 ;210 MAKE ALL AC+# MICROINSTRUCTIONS HAVE THE # FIELD THE SAME IN THE
; 569 ; PREVIOUS MICROINSTRUCTION TO SOLVE A TIMONG GLITCH IN THE HARDWARE.
; 570 ; MAKE EXCHANG MARK AND DESTINATION POINTERS UUO IF THEY DO NOT
; 571 ; HAVE BYTE POINTERS OF EQUAL LENGTH. CHANGES PERVASIVE IN EIS ALSO IN PF
; 572 ; RECOVERY IN IO.
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; EDHIS.MIC[4,24] 12:02 29-May-86 REVISION HISTORY
; 573 ; MAKE THE LOAD OF AN INDIRECT POINTER CLEAR PI CYCLE IF SET.
; 574 ; THIS MEANS THAT THE MONITOR CANNOT USE KERNAL CYCLE, INSTR ABORT
; 575 ; INH PC+1 OR HALT IN A PI CYCLE IF AN INDIRECT POINTER CAN
; 576 ; BE A PART OF THE REFILL. ALSO NOTE THE POSSIBILITY OF GETTING AN
; 577 ; INTERUPT BEFOR THE PI INSTRUCTION COMPLETES. (NEVER CONTINUES PI
; 578 ; INSTRUCTION) CHANGES AT LDIND.
; 579 ;207 CHANGE SBUS DIAG CODE FOR MOS PUT IT IN MOS CONDITIONAL /MOS=1
; 580 ; IF ON SBUS DIAG TRIES AT LEAST 8 TIMES TO GET A RESPONSE
; 581 ; OTHER THAN -1 IF IT GOT -1 ALL THOSE TIMES THE MICROCODE
; 582 ; GIVES UP AND RETURNS 0
; 583 ;206 FINAL FIXES TO PUSHM AND POPM
; 584 ;205 FIX BUG IN INDEX CALCULATION OF E1 FOR EXTENDED ADDRESSING.
; 585 ; INDEXING REQUIRED THAT AN AREAD BE PERFORMED IN ORDER TO LOAD
; 586 ; THE AR WITH A CORRECT FINAL RESULT. THE EFFECTIVE ADDRESS CALCULATION
; 587 ; AROUND EXTLA: GOT A NEW MACRO ADDED FOR INDEXING THAT DOES THE AREAD.
; 588 ; ABSOLUTE LOCATIONS IN THE RANGE 3040 GET USED AS TARGETS FOR THIS
; 589 ; AREAD THEN THE CODE REJOINS THE OLD CODE AT EXT2:
; 590 ; THE AREAD WAS NECESSARY FOR THE HARDWARE MAGIC TO LOAD PARTS OF THE
; 591 ; AR DEPENDING ON THE INDEX REGISTER AND OTHER EXTENDED ADRESSING
; 592 ; PARAMETERS.
; 593 ;204 ADD AUTOMATIC VERSION NUMBER
; 594 ; ADD CODE TO DO SBUS DIAG TESTING REQUIRED BY MOS
; 595 ;203 PUT THE BLKO PAG, CHANGE IN 201 IN A KLPAGING CONDITIONAL
; 596 ; KIPAGING GETS TANGLED IN AR PARITY ERRORS AND IN GENERAL DOES
; 597 ; THE WRONG THINGS
; 598 ;202 TURN OFF IMULI OPTIMIZATION IT GETS THE SIGN BIT AND THE OVERFLOW
; 599 ; FOULED UP (TURNED OFF FOR MODEL B ONLY WAS OFF IN MODEL A)
; 600 ;201 CHANGE BLKO PAG, TO INVALIDATE ONLY ONE ENTRY BY CLEARING IT
; 601 ; CHANGES AT PAGBO PAGBO+1 AND CLRPT+3 CLRPT+3 GETS SETUP THAT USED
; 602 ; TO BE AT PAGBO+1, PAGBO+1 NOW CLEARS ENTRY AND QUITS
; 603 ; KLPAGE ERROR CHECK FOR TOPS 10 MODEL A TO CAUSE ERROR
; 604 ; IF SWITCH SETTINGS ARE IN CONFLICT DIDDLED
; 605 ;200 CHANGE ALL EXEC REF TRACKS FEATURES BACK TO PHYS REF
; 606 ; ON SUSPICION THAT PAGE FAULTS ARE NOT HANDLED PROPERLY
; 607 ; MAKE NON TRACKS INSTR STAT FEATURES GET FOUR PHYSICAL
; 608 ; PAGE NUMBERS FROM FIRST FOUR LOCATIONS IN THE PAGE PRESENTED
; 609 ; IN THE DATAO PI, THE CODE ALSO USES THAT PAGE FIRST
; 610 ; LOCATION TO PUT THE INITIAL JUNK INTO ON STARTUP
; 611 ;177 FIX SOME BUGS IN OPCODE TIMING CODE AT OPTM0: AND BEYOND
; 612 ;176 ADD TO THE TIME COUNTING CODE CODE THAT COUNTS FREQUENCY
; 613 ; OF EACH OPCODE IN PAGE+2 AND PAGE+3
; 614 ;175 FIX TIME COUNTING CODE TO ACOUNT FOR EACH OPCODE IN THE
; 615 ; USER OR EXEC MODE IT WAS SEEN IN, EDGE COUNTS WERE DONE IN
; 616 ; WRONG MODE CHANGES UNDER OP.TIME CONDITONALS (PERVASIVE)
; 617 ;174 CHANGE TRACKS AND TIME COUNTING TO USE EXEC VIRTUAL SPACE
; 618 ; INSTEAD OF PHYSICAL SPACE
; 619 ;173 SEPERATE OUT THE DISMISS AT 626: BECAUSE OF SUSPECTED BUG
; 620 ;172 THE FACT THAT XJEN DISMISSES BEFORE READING NEW PC WORDS CAUSES
; 621 ; A PROBLEM FOR TOPS 20. REHASH THE CODE AT 600: TO 637: TO MAKE
; 622 ; XJEN READ THE TWO WORDS FIRST AND THEN DISMISS.
; 623 ;171 CAUSE IO PAGE FAIL FIX IN 170 TO SHIFT AT END GETTING CORRECT
; 624 ; PAGE FAIL WORD CHANGE AT IOPGF:
; 625 ;170 MAKE CLRFPD: GO DIRECT TO FINI: INSTEAD OF THROUGH NOP: THIS WAS
; 626 ; COSTING 2 TICS IN BYTE INSTRUCTIONS
; 627 ; CHANGE IO PAGE FAIL TO SAVE A VIRTUAL ADDRESS IN THE AC BLOCK 7
; 628 ; LOCATION 2 INSTEAD OF THE DATA THAT WAS ON THE EBUS CHANGES AT
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; EDHIS.MIC[4,24] 12:02 29-May-86 REVISION HISTORY
; 629 ; PGF4:+1 AND IOPGF:
; 630 ;167 CHANGE DEFAULT ON ADB MIXER SELECTS. NO DEFAULT NOW SUBFIELD U23
; 631 ; IS DEFAULTED TO 1 TO AVOID SELECTING FM AND NEEDING TO WAIT FOR PARITY.
; 632 ; THIS LEAVES THE OTHER BIT OF THE FIELD AVAILABLE FOR PARITY
; 633 ; EPT MOVED TO 540 USING SWITCH IN KLX,KLL (KLA,KLB NOW DEFUNCT)
; 634 ;166 CHANGE FIELD DEFINITION FORMAT CHANGE THE WAY THE OPTIONS FIELD
; 635 ; GETS ITS VALUES ASSIGNED. EACH BIT GETS A FIELD DEFINITION.
; 636 ;165 BUG IN 161 TO 164 WAS MISSING AC0 AT POP2: PARITY BIT WAS PUT THERE
; 637 ; IN THE NEWER MICROCODES
; 638 ; INSTALL MANY THINGS TO MAKE WORD STRING MOVES WORK START AT
; 639 ; MOVWD1 AND UNTILL BMVWD1 ALSO ASSORTED MACROS ARE ADDED
; 640 ; THESE ARE INSTALLED IN A SEPERATED EIS FILE (WDEIS) FOR THE MOST PART
; 641 ; THERE ARE SOME NEW MACROS AND THE CLEAN+17 LOCATION IS USED FOR
; 642 ; THIS CASE UNDER MODEL B CONDITIONAL INTERRUPTS DO NOT WORK YET
; 643 ; IN THIS CODE BUT ALL DATA TRANSFERS ARE CORRECT. INTERRUPTS ARE
; 644 ; TAKEN SO SUSPECT THE PROBLEM IS IN THE CLEANUP CODE.
; 645 ;164 LEAVE IN ONLY MAP FIX
; 646 ;163 TAKE OUT MAP FIX LEAVING XHLLI IN AND JRSTF IN
; 647 ;162 PUT XHLLI BACK IN TAKE OUT JRSTF ONLY IN SEC 0 CODE
; 648 ;161 XHLLI OUT TO DEBUG ADD RSTF0: TO MAKE TEST FOR JRSTF IN NON
; 649 ; 0 SECTIONS TEST IN ALL CASES
; 650 ;157 INSTALL XHLLI MAKE JRSTF UUO ON NON ZERO SECTIONS
; 651 ; ALSO MAKE MAP DOING A REFILL PAGE FAIL RIGHT THIS MEANS THAT AFTER
; 652 ; CLEAN IT CANNOT DO ANYTHING INTERESTING IF AN INTERRUPT IS PENDING
; 653 ; CHANGES AT MAP2:
; 654 ;156 REINSERT A SKP INTRPT IN THE PAGE FAULT HANDLER TO HAVE INDIRECT
; 655 ; POINTER CHAINS INTERRUPTABLE. AT PGRF6:+6
; 656 ;155 ABORTIVE MAP FIX FIX REMOVED PROBLEM MUST BE FIXED IN HARDWARE.
; 657 ;154 ADD TESTS FOR AC'S IN PHYSICAL REFERENCES FOR EXAMINES AND DEPOSITS
; 658 ; PHYS REFS GO TO MEMORY, NOT AC'S AFTER PROBLEM SHEET 1675
; 659 ; CHANGES AT PILD+3 PIFET+2 PSTOR PHYS1 PHYS2 PHYS3
; 660 ; ADD CHANGES IN TRACKS TO MAKE MODEL A WORK AT TRK2+2 AND +3
; 661 ;153 ADD SPECIAL CODE FOR PXCT OF BLT THIS HOPEFULLY CAN GO AWAY
; 662 ; WHEN THE EXTENDED ADDRESSING MONITOR DOES NOT USE PXCT ANYMORE
; 663 ; IT IS UNDER .IF/BLT.PXCT CONDITIONAL AND COSTS 12 WORDS
; 664 ;152 CHANGE WHAT BLT DOES TO MATCH THE SPEC SR_BLT(XXX) IS CHANGED TO
; 665 ; NOT FORCE GLOBAL ADDRESSING THE LOAD VMA(EA)_ARX+BR AND
; 666 ; STORE VMA(EA)_ARX MACROS ARE ADDED TO FORCE THE GLOBAL/LOCAL PARAMETERS
; 667 ; TO BE THE SAME AS THOSE OF THE EFFECTIVE ADDRESS
; 668 ;151 PUT THE EPT AND UPT AT 540 UNDER SWITCH CONTROL .IF/EPT540
; 669 ;150 VERSION NUMBER BACKED UP TO PRESERVE SPACE IN VERSION NUMBER FIELD
; 670 ;304 EXTEND 0 WOULD GET A JUMP TO AN UNUSED MICROLOCATION IN MODEL.B
; 671 ; ONLY THIS WAS BECAUSE LOCATION 2002: IN MODEL.A SHOULD BE AT 3002:
; 672 ; IN MODEL.B 3002: AND 3003: PUT IN WHERE 2002: AND 2003: ARE UNDER
; 673 ; CONDITIONALS.
; 674 ;303 CHANGE THE NUMBER FIELD OF THE SR_BLT(XXX) MACROS TO GIVE THE
; 675 ; BIT 0 OFF ALL THE TIME. THIS GIVES BLT MORE THE FORM OF THE OTHER
; 676 ; EXTENDED ADDRESSING STUFF IN HOW IT REFERS TO THE SHADOW AC'S.
; 677 ; IT IS STILL BELIEVED TO BE BROKEN BUT IS BETTER THAN IT WAS.
; 678 ;302 ADD LONGER ADDRESS CONSTRAINTS FOR THE NEW MICROASSEMBLER. EVERY
; 679 ; LOCATION THAT THE DISPATCH RAM CAN JUMP TO IS EFFECTED. THE
; 680 ; CONSTRAINTS THATUSED TO LOOK LIKE =00**** MUST NOW LOOK LIKE
; 681 ; =0****00**** THIS IS BECAUSE THE MODEL B MACHINE CAN AND DID
; 682 ; REALLY SET THAT BIT. THE CHANGE MAKES THE MICROCODE INCOMPATIBLE
; 683 ; WITH THE OLD ASSEMBLER.
; 684 ;301 HALT IS CLEARING THE RUN FLOP WITH HARDWARE MUST CHECK FOR
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; EDHIS.MIC[4,24] 12:02 29-May-86 REVISION HISTORY
; 685 ; KERNAL MODE BEFOR THE HALT MACRO SO USER IOT MODE WILL
; 686 ; NOT BE ABLE TO HALT. THIS TAKES ONE MICROWORD AT 1017:
; 687 ; THE SENSE OF THE SKIP IS REVERSED AGAIN SO 1016: IS BACK TO
; 688 ; BEING THE UUO AND CHALT: IS NOW A SEPERATE WORD AFTER 1017:.
; 689 ;300 REPLACE HALT CODE AGAIN BUT THIS TIME GET THE SENSE OF THE
; 690 ; SKIP RIGHT BY SWAPPING THE CONTENTS OF LOCATIONS 1016: AND 1017:
; 691 ; PUT THE 1: ADDRESS CONSTRAINT ON CONT:.
; 692 ;277 PUT HALT BACK THE WAY IT WAS SKP USER HAS THE INVERSE SKIP SENSE
; 693 ; AND HENCE DOES THE WRONG THING. HALT TO BE FIXED LATER.
; 694 ;276 YET ANOTHER TRY AT THE BLKO PROBLEM BLK1: SHOULD HAVE HAD A
; 695 ; J/BLK2.
; 696 ;275 THE LONG PC CHANGES HAD XSFM1: BEFOR THE ADDRESS CONSTRAINT THUS
; 697 ; GIVEING THE WRONG ADDRESS. THE =0 IS PUT BEFOR THE LABEL.
; 698 ;274 FIX THE DIAG.INST CONDITIONALS TO BEHAVE PROPERLY WITH THE
; 699 ; CONSTRAINTS OF DRAM LOCATIONS MAP DIED BECAUSE IT NEVER WAS
; 700 ; REACHED OUT OF A DISPATCH.
; 701 ;273 INSERT THE DIAG.INST FEATURE FOR THE DIAGNOSTICS PEOPLE.
; 702 ; CHANGES AT DCODE 104:, 106: AND AT XCT: SHOULD NOT EFFECT OTHER
; 703 ; ASSEMBLIES.
; 704 ;272 THE FIX TO THE GARBAGE IN THE LEFT HALF OF VMA IN 265 FORGOT TO
; 705 ; LOAD THE VMA IN BLK3:+1 PUT THAT IN. ALSO ON JUD'S RECOMENDATION
; 706 ; PUT A COPY OF THE NOP MICROINSTRUCTION AFTER CLRFPD: TO MAKE
; 707 ; ENOUGH TIME IN THE SKIP CASE. IT SEEMED TO WORK WITHOUT THIS
; 708 ; AND IF SPACE GETS TIGHT IT SOULD BE REMOVED.
; 709 ;271 FIX IN 267 PGF4:+4 DOES NOT WORK, CANNOT PUT VMA_# THERE. POSSIBLY BECAUSE
; 710 ; VMA_# CONFLICTS IN SOME ESOTERIC WAY WITH STORE? THAT CHANGE
; 711 ; IS TAKEN OUT AND AT PGF1 THE VMA IS GIVEN 500 OR 501. THIS IS SLIGHTLY
; 712 ; LESS DESIREABLE AND FURTHER EFFORT COULD BE SPENT IN THE UCODE TO
; 713 ; MAKE PAGE FAILS LESS UNWEILDY FOR THE SOFTWARE ROUTINE THAT CONVERTS
; 714 ; THEM TO MODEL B FORM.
; 715 ;270 CHANGE HALT TO CHECK FOR USER MODE INSTEAD OF IO LEGAL. A JOB
; 716 ; IN USER IOT SHOULD NOT BE ABLE TO HALT THE MACHINE.
; 717 ;267 ADD NEW CONDITIONAL SHIFT.MUUO TO PROVIDE THE SHIFTED DOWN MUUO
; 718 ; DATA BLOCKS MORE SIMILAR TO THE XADDR TYPES. CONDITIONAL IS USED
; 719 ; AT 1003: AND PGF4:+4 TO PROVIDE A DIFFERENT STARTING ADDRESS.
; 720 ;266 FIX PILD+3 TO LOAD THE VMA AT THE SAME TIME THUS ENABLING
; 721 ; THE MODEL HACK FIX TO LOAD THE LONG VMA.
; 722 ;265 HAIR UP THE ALREADY HAIRY BLKXX CODE TO CLOBBER THE LEFT HALF OF AR
; 723 ; BEFOR USING IT AS AN ADDRESS. CLOBBERED ARL AT BLK2 AND LOADED
; 724 ; VMA AT BLK3.
; 725 ;264 ADD J/CLRFPD AT BFIN TO MAKE IT THE SAME AS IT WAS. BFIN GOT
; 726 ; MOVED TO A DIFFERENT PLACE IN THE LAST EDIT AND THIS J FIELD
; 727 ; WAS NOT FIXED.
; 728 ;263 ADD THE MIT FIXES. IOTEND AND THE BLK1 TO BLK4 GROUP ARE CHANGED
; 729 ; EXTENSIVELY. CLRFPD IS PUT JUST BEFORE FINI CONSTRAINT ON IOFET
; 730 ; IS CHANGED.
; 731 ; ADD THE LONG PC FORMAT UNDER A NEW CONDITIONAL LONG.PC THE
; 732 ; CONDITIONAL IS TURNED ON BY XADDR. CONDITIONALS ARE ADDED TO THE
; 733 ; LONG PC CODE TO MAKE IT SMALLER WHEN ONLY SECTION 0 IS POSSIBLE.
; 734 ; ADD COMMENTS TO THE MICROCODE OPTIONS FIELD.
; 735 ; RESTORE SXCT CODE FROM VERSION 131. TO BE USED ONLY IN MODEL A
; 736 ; NON KLPAGING CODE.
; 737 ;262 PUT WORD AT INDR1+1 UNDER SXCT CONDITIONAL SO WHEN SXCT IS OFF WE
; 738 ; GET AN ADDITIONAL SAVINGS OF ONE WORD.
; 739 ;261 ADD PHYS REFS AT PGRF6+4 AND PIDISP+4 TO MAKE MODEL.A LOAD A LONG
; 740 ; VMA. PART OF THIS CODE IS NOT UNDER CONDITIONAL BECAUSE IT SHOULD NOT MATTER
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; EDHIS.MIC[4,24] 12:02 29-May-86 REVISION HISTORY
; 741 ; TO A MODEL.B MACHINE. PIDISP+4 ALSO GETS THE LOAD OF THE SAME DATA
; 742 ; REPEATED SO THE PHYS REF HAS SOMETHING TO WORK ON.
; 743 ; FLUSH THE NOW USELESS CODE AT CHALT TO GENERATE THE LD AR.PHYS
; 744 ; CONSTANTS.
; 745 ; CURRENTLY THERE IS SORT OF A BUG IN THAT THE SBR AND THE CBR
; 746 ; CAN NOT BE ABOVE 256K IN A MODEL.A MACHINE. THIS DOES NOT BOTHER
; 747 ; THE CURRENT MONITORS AT ALL IN THAT THESE TABLES ARE IN VERY LOW CORE.
; 748 ; IF THAT CHANGES THE LOCATIONS SECIMM+3 SECIMM+7, LDIND, PGRF5, LDSHR
; 749 ; AND LDPT1+1 MUST ALL GET FIXED UP. THE GENERAL FIX IS TO GET A PHYS REF
; 750 ; IN THE MICROINSTRUCTION THAT LOADS THE VMA. THIS CAN BE DONE BY
; 751 ; POSTPONING THE LOAD OF THE VMA ONE MICROINSTRUCTION IN ALL OF THESE
; 752 ; PLACES, BUT, SINCE THAT CAUSES A PERFORMANCE DEGRADATION IT WAS NOT
; 753 ; DONE.
; 754 ;260 DIVERGANT CHANGES TO MAKE KLPAGING PHYS REFS THE OLD WAY
; 755 ; CAUSE ALL CASES OF VMA_XXX+LD AR.PHYS TO GO BACK TO THE
; 756 ; OLD PHYS REF WAY
; 757 ;257 IN MODEL B MACHINES AT LDPT+1 THE VMA IS GETTING GARBAGE IN THE
; 758 ; LEFT HALF BECAUSE IT ADDED IN JUNK THAT WAS IN AR LEFT. FIX IS TO
; 759 ; CLEAR ARL AFTER LDPT AND TO DO THE SHUFFLE PERFORMED THERE ONE
; 760 ; MICROINSTRUCTION LATER.
; 761 ;****** A HACK FIX IS USED HERE THAT TAKES TWO WORDS. THIS WAS DONE BECAUSE
; 762 ; OF EXTREEM TIME PRESSURE TO DEBUG >256K MODEL B. THERE OUGHT TO BE
; 763 ; A WAY TO REDUCE THIS FIX TO ONLY ONE WORD IN SPACE AND TIME, OR
; 764 ; EVEN LESS.
; 765 ;256 EDIT JUMPED TO RANDOMNESS WITH AN EXTRA RETURN. THIS HAPPENED
; 766 ; BECAUSE THERE WAS NO CALL AT EDSFLT IN THE MODEL B NON XADDR CODE
; 767 ; ADDED CALL TO EDSFLT.
; 768 ;255 SAVE EDIT FROM GETTING AN EXTRA STORE CYCLE AT EDSSIG BY SENDING
; 769 ; IT ALWAYS TO THE EDFLT1 LOCATION INSTEAD OF EDFLT THIS ONLY
; 770 ; CHANGES WHAT HAPPENS IN MODEL B NON XADDR BECAUSE IN MODEL A
; 771 ; EDFLT AND EDFLT1 ARE THE SAME LOCATION ANYWAY
; 772 ;254 CAUSE THE A INDRCT CHANGE IN 253 TO BE ONLY FOR NON EXTENDED
; 773 ; ADDRESSING MACHINES. THIS THROWS DOUBT ON THE WORD SAVINGS
; 774 ; THAT MIGHT HAVE BEEN POSSIBLE
; 775 ;253 CHANGE A INDRCT TO LOAD BOTH THE AR AND ARX, IN THE EXTENDED
; 776 ; INSTRUCTION SET THIS HAPPENED TO BE DEPENDED ON AT EXT2+2 AND
; 777 ; EXT2+3. THE DEFINITION OF A IND IN EA CALC/ WAS FIXED TO
; 778 ; LOAD THE AR AND THE ARX
; 779 ; I THINK THIS PERMITS THE SAVINGS OF AN EXTRA WORD AND SOME
; 780 ; TIME ON ALL INDIRECTS. CHECK OUT FLUSHING INDR1 AND MAKING INDRCT
; 781 ; DO THE DISPATCH AND GO TO COMPEA
; 782 ; FORCE ADB TO GENERATE AR*4 AS DEFAULT THIS DISABLES PARITY
; 783 ; CHECKING ON THE FM WHEN IT IS NOT BEING READ FIXED IN
; 784 ; DEFINITION OF ADB THIS WILL ALSO SPEED UP THE MACHINE BY SOME
; 785 ; BECAUSE THE ADB FIELD CAN NO LONGER FORCE 3 TICS WITHOUT REALLY
; 786 ; NEEDING THAT LONG
; 787 ;252 SAVE A WORD AT IOPGF+1 BY MAKING IT PILD+3 THIS ADDS THE SET
; 788 ; ACCOUNT ENABLE TO AN UNDEFINED CASE.
; 789 ;251 TURNING ON PAGING CAUSED A HANG THIS WAS BECAUSE OF A MISIMPLIMENTED
; 790 ; FIX IN 250. THE ATTEMPT TO PUT THAT FIX IN NO SPACE FAILED AND IT TOOK
; 791 ; ONE WORD. AT LDPT+1 ADD BR/AR AT GTCST1 RECOVER THE AR FROM THE BR
; 792 ; THIS SEEMS LIKE IT SHOULD BE ABLE TO BE BUMMED BUT I CANNOT
; 793 ; FIGURE OUT HOW
; 794 ; ALSO FIX A PLACE WHERE A PHYS REF WAS LEFT IN THE MODEL A CODE
; 795 ; AT PGRF6+4 MODEL B CONDITIONAL IS AS IT WAS MODEL A IS NEW TO USE
; 796 ; LD AR.PHYS MECHANISM
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; EDHIS.MIC[4,24] 12:02 29-May-86 REVISION HISTORY
; 797 ;250 LOADING HIGH ORDER GARBAGE TO THE VMA WITH THE FIX FOR
; 798 ; >256K CAUSES FUNNY THINGS TO HAPPEN. BITS GET CLOBBERED
; 799 ; WITH AR0-8_SCAD 14 LINES AFTER SECIMM. ACTUALLY IS MORE
; 800 ; HAIR BECAUSE OF CONFLICTING FIELDS. CODE ABOVE AND BELOW
; 801 ; THAT GOT REARRANGED TO SIMPLER MODEL A AND MODEL B CONDITIONALS
; 802 ; SINCE NOW ALL LINES ARE DIFFERENT. SHUFFLING OF FE IS DONE
; 803 ; TO PROVIDE ROOM FOR A CONSTANT ON THE CORRECT SIDE OF THE SCAD
; 804 ; AT LDPT A SIMILAR
; 805 ; RECODING IS NEEDED. 4 LINES OF CODE ARE REDONE IN MODEL
; 806 ; A CONDITIONAL AND CONDITIONALS ARE RESHUFFLED TO HAVE
; 807 ; SIMPLER FORMAT
; 808 ; NEW MACROS ARE ADDED GEN AR0-8, GEN FE AND AR0-8
; 809 ; VMA_AR+LD AR.PHYS AND ITS FRIENDS ARE TAKEN OUT OF KLPAGING
; 810 ; CONDITIONAL THEY ARE USED TO DO EXAMINES AND DEPOSITS NOW
; 811 ;247 FIX ST AR.PHYS TO GIVE BIT 4 INSTEAD OF BIT 5 AT CHALT
; 812 ; AT PSTORE CHECK FOR AC REF AND IF SO WRITE FM MUST DO THIS
; 813 ; BECAUSE LOAD AD FUNC DOES NOT SET MCL STORE AR
; 814 ;246 FIX MUUO, IN EXTENDED ADDRESSING, TO GET NEW PC BEFORE CLOBBERING
; 815 ; THE USER AND PUBLIC FLAGS THAT TELL WHERE TO GET IT. FIX CONDITIONAL
; 816 ; ASSEMBLY AT INDRCT TO DO EA TYPE DISP IN MODEL A, NOT MODEL B.
; 817 ;245 ADDITIONAL FIXES FOR THE 256K PROBLEM, TO MAKE EXAMINE AND
; 818 ; DEPOSIT WORK. CHANGES AT CHALT TO CREATE CONSTANT "ST AR.PHYS",
; 819 ; AND EXTENSIVELY NEAR PICYC1, PIDATI, AND PIDATO. CHANGES ARE ALL
; 820 ; UNDER MODEL B CONDITIONAL, BECAUSE MODEL B HARDWARE WORKS OK, AND
; 821 ; THE FIX IS REGARDED AS CROCKISH.
; 822 ;244 WAIT FOR COMPLETION OF INDIRECT REFERENCE AT BYTEI+1 AND EXTI+1
; 823 ; EVEN THOUGH INTERRUPT REQUEST HAS BEEN SEEN, SO AS NOT TO CONFUSE MBOX.
; 824 ;243 VARIOUS FIXES TO MAKE THESE SOURCES WITH MODEL.B SWITCH OFF
; 825 ; EQUIVALENT TO MODEL A SOURCES, SO WE CAN DISCARD MODEL A SOURCES
; 826 ; THE FIXES ARE:
; 827 ; 1) SWITCH SNORM.OPT, TO SAVE SPACE IN SINGLE PRECISION
; 828 ; FLOATING NORMALIZATION.
; 829 ; 2) CREATION OF LD AR.PHYS MAGIC CONSTANT, TO SOLVE HARDWARE
; 830 ; PROBLEMS GENERATING ADDRESSES ABOVE 256K.
; 831 ;242 FIX AT SECPTR+1 TO PRESERVE AR LEFT UNTIL WE CAN CHECK
; 832 ; FOR BITS 12-17 NON ZERO CORRECT ADDRESS CONSTRAINTS AT
; 833 ; SECIMM+1 & +2 TO GET BRANCHING RIGHT FOR SHARED AND INDIRECT
; 834 ; SECTION POINTERS. FIX AT LDIMM+1 TO CLEAR LH OF AR BEFORE
; 835 ; LOADING VMA WITH SPT ADDRESS, TO PREVENT PAGE FAULT ON SPT
; 836 ; REFERENCE.
; 837 ;241 MORE FIXES AT START: AND NEWPC:, FOR SAME PROBLEM AS 240.
; 838 ; MUST LOAD FLAGS AND CLEAR VMAX, THEN LOAD VMA INTO PC TO CLEAR
; 839 ; PCX, THEN RELOAD VMA TO GET EFFECT OF NEW FLAGS AND CLEARED
; 840 ; PCX. (MODEL A ONLY).
; 841 ;240 FIXES AT START: AND NEWPC: TO LOAD 23-BIT ADDRESS RATHER
; 842 ; THAN 30-BIT, SINCE OTHER BITS ARE PC FLAGS. AT SAME TIME AND
; 843 ; PLACE, FIX MODEL A CODE TO CLEAR PC SECTION NUMBER.
; 844 ;237 CHANGE CONDITIONALS AROUND PUSH AND POP CODE FROM XADDR TO
; 845 ; MODEL.B. COULD SIMPLIFY IFNOT XADDR.
; 846 ;236 FIX ADDRESS CONSTRAINTS ON USES OF EA MOD DISP IN MODEL
; 847 ; B MACHINE WITH EXTENDED ADDRESSING OFF. PROBLEMS AT COMPEA,
; 848 ; BFETCH, AND EXT2.
; 849 ;235 SLIGHTLY CLEANER FIXES FOR PROBLEMS IN 234 TO AVOID WASTING TIME
; 850 ; AND SPACE. BYTE READ MACRO NEEDS TO SET VMA/LOAD, AND VMA_VMA
; 851 ; HELD MACRO DOESN'T USE MEM FIELD UNLESS MODEL B AND KL PAGING.
; 852 ; ALSO FIX CONDITIONAL ASSEMBLY STUFF TO AVOID SPURIOUS ERRORS.
; KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986 V2A(442) MICRO %37(277) Page 1-15
; EDHIS.MIC[4,24] 12:02 29-May-86 REVISION HISTORY
; 853 ;234 INSTALL FIXES FOR SOME PLACES WHERE MODEL B CODE CAUSES CONFLICT
; 854 ; WITH THE OLD NON KLPAGING NON EXTENDED ADDRESSING CODE
; 855 ; THESE ARE AT BFETCH, PGF3-1, PGF6, EXT1+2
; 856 ;233 FIX THE FOLLOWING PROBLEMS:
; 857 ; KL PAGING SHOULD PRODUCE A PAGE FAILURE WHEN BITS
; 858 ; 12-17 OF A PRIVATE SECTION POINTER ARE NON 0
; 859 ; FIXED AT SECPTR ETC.
; 860 ; EDIT DOES NOT ALLOW INTERUPTS
; 861 ; FIXED AT EDNXT1 AND AFTER THAT
; 862 ; MAP SHOULD NOT BE LEGAL IN USER MODE
; 863 ; FIXED AT MAP2 AND CLEAN+15
; 864 ; MOVMI IS SHORTENED BY MAKING IT THE SAME AS MOVEI
; 865 ; AT DON LEWINES SUGGESTION THIS IS IN DCODE 215
; 866 ;232 MERGE THE SECOND ORDER STATISTICS GATHERING CODE WITH THIS
; 867 ; CODE INTENT IS TO KEEP IT HERE
; 868 ;231 CHANGE THE LOAD CCA DEFINITION TO REFLECT THE NEW HARDWARE
; 869 ; THIS IS ENABLED WHEN THE MODEL.B ASSEMBLY SWITCH IS ON
; 870 ;230 THIS IS THE POINT WHERE MICHAEL NEWMAN TAKES OVER THE MICROCODE
; 871 ; MAINTENCE SEVERAL BUG FIXES GET EDITED INTO 126 AT THIS POINT
; 872 ; TWO SETS OF PARALLEL CODE WILL BE MAINTAINED FOR A WHILE.
; 873 ; FIX THE CMPS PARODY ERROR PROBLEM WHEN ILLEGAL BITS ARE FOUND IN
; 874 ; THE LENGTHS.
; 875 ;227 FIX PIBYTE TO GET DTE# CORRECT ON TO-10 TRANSFERS. FIX MTRREQ
; 876 ; CYCLES TO WAIT FOR STORE TO FINISH BEFORE RE-ENABLING ACCOUNT.
; 877 ; FIX ADJSP OF LONG STACK POINTERS TO FETCH NEXT INSTR.
; 878 ;226 FIX EXMD TO LOAD AR, RATHER THAN ARX, WITH MARK POINTER, AS
; 879 ; EXPECTED BY THE HANDLER. FIX EDIT, SEVERAL PLACES, TO IGNORE
; 880 ; LEFT HALF OF MARK & PATTERN ADDRESSES WHEN PC SECTION IS ZERO.
; 881 ; FIX EDIT TO MAKE EXTENDED REFERENCE FOR PATTERN BYTES.
; 882 ; FIX ADJSP TO BE MEANINGFUL WITH LONG STACK POINTERS
; 883 ;225 FIX BYTEA NOT TO CLOBBER FE ON INDIRECTS, FIX EXMD TO BACK
; 884 ; UP VMA AFTER STORING DSTP2 AND BEFORE STORING DSTP. FIX EDIT TO
; 885 ; COUNT THE WHOLE PATTERN ADDRESS IF PC SECTION NOT ZERO.
; 886 ;224 FIX EXTEND ADDRESS CALCULATION TO RECOVER E0 FROM MQ, AND
; 887 ; FIX EXTEND OPCODE TEST TO DISALLOW OPS >20.
; 888 ; FIXES TO HANDLE NEW ENCODING OF AC-OP ON APR BOARD.
; 889 ;223 COMPLETE 222. P HAS TO GO TO SC AS WELL AS AR0-5. CREATE
; 890 ; SUBROUTINE RESETP TO DO IT. GET CODE IN SYNC WITH HARDWARE AND
; 891 ; MOST RECENT SPEC FOR MEANING OF PXCT AC BITS IN EXTEND. THUS
; 892 ; UNDO COMMENT IN 221: WE SHOULD LOOK AT PXCT B11. ALSO FIX
; 893 ; EXTEND TO USE CORRECT ENCODING OF BITS 9, 11, AND 12 FOR PXCT
; 894 ; OF STRING OPERATIONS. FIX DATAI PAG SO IT DOESN'T LOSE THE
; 895 ; PREVIOUS CONTEXT AC BLOCK WHEN LOADING PREVIOUS SECTION #.
; 896 ; INSERT CHANGE CLAIMED FOR EDIT 55, TO INHIBIT INTERRUPT DURING
; 897 ; PI CYCLES.
; 898 ;222 FIX BYTE POINTER UPDATE ROUTINES GSRC & IDST IN EIS CODE
; 899 ; TO UPDATE P WHEN INCREMENTING SECOND WORD. JUST FORGOT TO. TRY
; 900 ; AGAIN TO CONTROL EIS REFERENCES OFF E0, FOR EXTENDED OR NOT.
; 901 ;221 COMPLETE FIX OF 220, TO KEEP SR CORRECT THROUGH RELOAD OF IR
; 902 ; IN EXTEND DECODING, AND TO CONTROL SR CORRECTLY FOR XBLT DST
; 903 ; REFERENCES. (WE WERE LOOKING AT PXCT B11, SHOULD BE B12).
; 904 ;220 FIXES SEVERAL PLACES TO USE "EA" IN DRAM A FIELD INSTEAD OF "I",
; 905 ; NOTABLY BLT, WHICH WAS USING WRONG SECTION. FIX EXTEND TO
; 906 ; CONTROL VMA EXTENDED BEFORE FETCHING EXTEND-OP, SO AS NOT TO
; 907 ; LOOK "UNDER" THE AC'S. FIX XBLT FOREWARD TO STOP WHEN AC GOES
; 908 ; TO ZERO, NOT -1. ALSO CONTROL SR BEFORE INITIAL STORE TO GET
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; EDHIS.MIC[4,24] 12:02 29-May-86 REVISION HISTORY
; 909 ; CORRECT CONTEXT.
; 910 ;217 CODE CHANGES TO MAKE SECOND WORD OF BYTE POINTER WORK RIGHT
; 911 ; WHETHER EFIW OR IFIW, BY CONTROLLING CRY18 OR CRY6.
; 912 ;216 RECODE EXTENDED INSTRUCTION SET DECODING & EFFECTIVE ADDRESS
; 913 ; CALCULATION. FIX UUO CODE TO INCREMENT VMA AFTER STORING PC.
; 914 ; FIX ADJBP TO GET 36 BIT ADDRESS ADJUSTMENT IF B12 SET.
; 915 ;215 REARRANGE CONDITIONAL ASSEMBLY DEFAULTS TO BE MORE LOGICAL
; 916 ; INSERT FORM FEEDS AND COMMENTS TO HELP BEAUTIFY THE LISTING.
; 917 ; REWORK THE NEW JRST'S, TO MAKE THEM SMALLER, FASTER, AND TEST
; 918 ; IO LEGAL BEFORE DISMISSING. PUT IN XBLT.
; 919 ;214 MODIFY ADJBP AND UUO'S FOR EXTENDED ADDRESSING. REWORK PARITY
; 920 ; ERROR HANDLING, IN A FRUITLESS ATTEMPT TO MAKE IT SMALLER,
; 921 ; BUT SUCCESSFULLY MAKING IT CLEARER. FIX ASSEMBLY ERRORS IN EIS
; 922 ; DUE TO AC4 CHANGES, AND ADD CODE TO HANDLE LONG BYTE POINTERS
; 923 ; IN AC'S. PUT IN CODE TO GIVE PAGE FAIL 24 ON ILLEGAL FORMAT
; 924 ; INDIRECT WORD.
; 925 ;213 FIX LDB & DPB TO TEST POINTER BIT 12 ON CALL TO BYTEA.
; 926 ;212 MODIFY JSP, JSR TO STORE FULL PC WITHOUT FLAGS IN NON-ZERO SEC
; 927 ; SEPARATE CONDITIONALS FOR "MODEL B" MACHINE FROM THOSE FOR
; 928 ; EXTENDED ADDRESSING MICROCODE.
; 929 ;211 REMOVE UNNECESSARY DIDDLING OF VMA USER BIT DURING PAGE REFILL,
; 930 ; AND ELIMINATE SPECIAL CASE FOR MAP INSTRUCTION, WHEN EXTENDED
; 931 ; ADDRESSING HARDWARE EXISTS TO SOLVE THESE PROBLEMS.
; 932 ; FIX SEVERAL CASES OF SIGNS DISP WITH INADEQUATE CONSTRAINT.
; 933 ;210 FIX DEFINITION OF "SKP LOCAL AC REF", WHICH CONFUSED "AC
; 934 ; REF" WITH "LOCAL AC REF".
; 935 ;207 FIX JRSTF (AND ITS DERIVATIVES) TO LOAD FLAGS INTO AR AFTER
; 936 ; DOING EA MOD DISP, WHICH WOULD OTHERWISE CLOBBER THEM. FIX
; 937 ; COMPEA CODE TO LET AREAD HARDWARE LOAD AR. OTHERWISE GET SEC #.
; 938 ;206 FIX PCTXT ROUTINE TO GET PREVIOUS CONTEXT SECTION.
; 939 ;205 FIX POPJ TO LOAD HALFWORD OR FULLWORD PC ACCORDING TO PC SECT
; 940 ;204 FIX CONDITIONALS AROUND LOC 47, WRONG IN 202. FIX DEFINITION
; 941 ; OF A INDRCT, DOESN'T NEED #07. FIX STACK INSTRUCTIONS FOR
; 942 ; EXTENDED ADDRESSING. MUST NOT LOAD VMA FROM FULL AD.
; 943 ;203 INCLUDE CODE AT NEXT+2 TO GENERATE ADDRESS MASK (LOW 23 BITS)
; 944 ; AT HALT TIME, AND CODE IN PICYCLE TO USE IT TO GET 23 BIT ADDR
; 945 ; OUT OF IOP FUNCTION WORD.
; 946 ;202 MOVE "40+A" LOCATIONS TO "A" UNDER EXTENDED ADDRESSING. CHANGE
; 947 ; ALL CALL MACROS TO GENERATE CALL BIT INSTEAD OF SPECIAL FUNC'S.
; 948 ;201 BEGIN EXTENDED ADDRESSING CHANGES IN EARNEST. INTEGRATE NEW
; 949 ; EFFECTIVE ADDRESS COMPUTATION CODE, AND REVISE INSTRUCTION
; 950 ; ROUTINES AS NECESSARY.
; 951 ;126 FIX STRAC3-2, WHERE COMMA GOT LEFT OFF WHEN IFETCH MOVED
; 952 ;125 REMOVE NXT INSTR FROM STAC1, STRAC3, & STAC4, MAKING THEM JUMP
; 953 ; TO FINI INSTEAD. PROBLEM INVOLVES A RACE IF PAGE FAIL OCCURS
; 954 ; WHILE WRITING FM. IF FM ADDRESS CHANGES BEFORE COND/FM WRITE
; 955 ; GOES FALSE, APR BOARD MAY GRONK PARITY BIT OF SOME FM LOC'N.
; 956 ; THIS RESULTS IN SOME SOME PATHS FROM FETCH TO NICOND BECOMING
; 957 ; LONGER THAN 6 TICKS, SO THE FETCHES GOT SHUFFLED IN SOME PLACES.
; 958 ; MICROCODE PATCH ELIMINATES MOST PROBABLE CAUSE, WHICH IS PAGE
; 959 ; FAIL AT NICOND TIME WHILE WRITING AC OTHER THAN 0. IT DOES NOT
; 960 ; TAKE CARE OF THE POSSIBILITY THAT COND/FM WRITE WILL GLITCH AT
; 961 ; INSTR 1777 TIME.
; 962 ;124 FIXES IN SEVERAL PLACES TO SET AND CLEAR ACCOUNT ENABLE SO AS
; 963 ; TO GET REPEATABLE ACCOUNTING MEASURES OF USEFUL WORK DONE. THE
; 964 ; ENABLE IS NOW CLEARED FOR METER UPDATE CYCLES AND KL PAGE REFILL
; KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986 V2A(442) MICRO %37(277) Page 1-17
; EDHIS.MIC[4,24] 12:02 29-May-86 REVISION HISTORY
; 965 ; CYCLES. THE HARDWARE ALREADY TAKES CARE OF PI CYCLES.
; 966 ;123 CORRECT 122 TO CONSTRAIN LOC "UNHALT", AND TO LOAD ARX FROM AR,
; 967 ; SO AS TO LET "SKP AR EQ" WORK. PROBLEM AROSE BECAUSE MACRO ALSO
; 968 ; TESTS ARX00-01. FIX EDIT, WHEN STORING DEST POINTER ON SELECT
; 969 ; SIGNIFICANCE START, TO ELIMINATE AMBIGUITY IN DEST P FIELD.
; 970 ;122 SPEC CHANGE TO EXIT FROM HALT LOOP, SO THAT AR0-8=0 WITH AR9-35
; 971 ; NON-ZERO LOADS AR INTO PC TO START PROCESSOR. THIS IS DIFFERENT
; 972 ; FROM EXECUTING JRST BECAUSE PC FLAGS ARE CLEARED.
; 973 ;121 FIX TO 120 TO ALLOW A CYCLE BETWEEN FILLER FROM MEMORY AND
; 974 ; WRITING IT INTO FM (THUS PARITY CAN BE COMPUTED). ALSO CLEAR
; 975 ; STATE REGISTER IN EDIT BEFORE GETTING NEXT PATTERN BYTE.
; 976 ;120 FIX EIS TO TOLERATE PAGE FAIL ON READ OF FILL BYTE IN MOVSRJ
; 977 ; OR B2D CONVERSION. REQUIRES GETTING FILLER BEFORE STORING DLEN
; 978 ; ALSO INTEGRATE OPCODE COUNTING/TIMING CODE UNDER CONDITIONALS
; 979 ;117 FIX PARITY ERROR CODE TO WRITEBACK AR ON RPW ERROR.
; 980 ;116 REWRITE OF DDIV, SO THAT THE NO-DIVIDE TEST IS ON THE MOST
; 981 ; SIGNIFICANT HALF OF THE MAGNITUDE OF THE DIVIDEND, RATHER THAN
; 982 ; THE MAGNITUDE OF THE MOST SIGNIFICANT HALF. IN THE PROCESS,
; 983 ; SAVE TIME AND SPACE. ALSO PUT IN CONDITIONAL ASSEMBLY VARIABLE
; 984 ; "WRTST" TO INHIBIT WRITE TEST CYCLE FOR INSTRUCTIONS WHICH
; 985 ; APPEAR NOT TO NEED IT, AND THUS TO SPEED THEM UP.
; 986 ;115 FIX SBDIAG TO SET MCL REG FUNC TO INHIBIT EBOX MAY BE PAGED.
; 987 ;114 RECODE STRING COMPARE TO SAVE SPACE AND TIME. CHANGE DEFAULTS
; 988 ; FOR KLPAGING TO INCLUDE EIS, EXCLUDE TRACKS FEATURE. CHANGE
; 989 ; KLPAGING (NEW SPEC) TO KEEP "LOGICALLY WRITABLE" IN SOFTWARE BIT
; 990 ;113 RECODE KL PAGING TO ELIMINATE PROBLEM OF WRITING HARDWARE
; 991 ; PAGE TABLE BEFORE CHECKING FOR AGE TRAP, AND THEREFORE LEAVING
; 992 ; THE PAGE ACCESSIBLE AFTER THE TRAP. THE RECODING ALSO IMPROVES
; 993 ; THE ALGORITHM IN THAT THE HARDWARE ENTRY INCLUDES THE W BIT SET
; 994 ; IF THE CORE TABLES ALLOWED WRITE AND THE CST INDICATES WRITTEN,
; 995 ; EVEN IF THE CURRENT REFERENCE WAS NOT A WRITE.
; 996 ; ALSO FIX CODE WHICH WRITES PT DIR, TO GET WRITE REF BIT FROM
; 997 ; VMA HELD INTO BIT 5 OF SAVED PAGE FAIL WORD.
; 998 ;112 FIX PAGE FAIL CODE FOR USE WITH PROB SHEET 1396, WHICH LOADS
; 999 ; PC IF PAGE FAIL OCCURS ON NICOND. THUS CODE NEEDN'T CHECK FOR
; 1000 ; FETCH AT CLEAN, WHICH CAUSED OTHER PROBLEMS ON PARITY ERRORS.
; 1001 ; CLEAR FE AND SC IN NXT INSTR MACRO (JUST CLEANLINESS).
; 1002 ;111 PATCH SEVERAL ROUTINES WITH THE FOLLOWING MACRO --
; 1003 ; FETCH WAIT "MEM/MB WAIT"
; 1004 ; TO PREVENT SEQUENCES IN WHICH PAGE FAIL INFO CAN GET LOST
; 1005 ; BECAUSE OF LONG TIME FROM REQUEST TO MB WAIT. THESE PATCHES
; 1006 ; SHOULD BE REMOVED AFTER AN ECO HAS BEEN INSTALLED TO FIX.
; 1007 ; IN ADDITION, EBUSX SUBROUTINE HAS BEEN MODIFIED TO PREVENT RACE
; 1008 ; CONDITION WHEN SETTING UP IO FUNCTION WITH COND/EBUS CTL AND
; 1009 ; MAGIC # BIT 4. MUST NOT CHANGE #5 THROUGH #8 ON NEXT CYCLE.
; 1010 ; FIX KLPAGING CODE TO GO BACK TO AREAD ON MAP REF, BECAUSE
; 1011 ; MEM/AD FUNC DOESN'T CORRECTLY RESTORE APR REG FUNC. ALSO MAKE
; 1012 ; THE CODE SMARTER ON NO MATCH CONDITION, SO REQUEST DOESN'T HAVE
; 1013 ; TO BE RESTARTED AND IMMEDIATELY FAIL AGAIN.
; 1014 ;110 GIVE UP ON THE OLD STRING COMPARE CODE, INSTALLING MIKE NEWMAN'S
; 1015 ; VERSION. SOMEWHAT SLOWER, BUT GIVES THE RIGHT ANSWERS.
; 1016 ; FIX LDB CODE TO WAIT FOR MEM WORD EVEN IF INTERRUPT REQUEST
; 1017 ; SEEN, SO AS NOT TO GET CONFUSED WHEN IT ARRIVES OR PAGE FAILS.
; 1018 ; ALSO IMPROVE CLRPT ROUTINE USED BY CONO AND DATAO PAG TO START
; 1019 ; LOOP WITH VMA CLEARED AND PT WR SELECTION SETUP CORRECTLY.
; 1020 ;107 FIX STRING COMPARES TO CHECK FOR INTERRUPT. THIS INVOLVED
; KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986 V2A(442) MICRO %37(277) Page 1-18
; EDHIS.MIC[4,24] 12:02 29-May-86 REVISION HISTORY
; 1021 ; CHECKING DURING GSRC ROUTINE, WHICH ELIMINATES NEED FOR CHECK
; 1022 ; IN SRCMOD (WHICH CALLS GSRC). IT ALSO REQUIRED CLEARING SFLGS
; 1023 ; AT STARTUP, AND ADJUSTING DLEN UPDATE CODE IN DEST FILL TO GET
; 1024 ; VALID LENGTH STORED ON INTERRUPT.
; 1025 ;106 ELIMINATE RACE IN DECODING OF # FIELD ON MTR BOARD BY HOLDING
; 1026 ; LOW 3 BITS THROUGH NEXT MICROINSTRUCTION.
; 1027 ; FIX LUUO AND MUUO TO ALLOW INTERRUPTS.
; 1028 ; FIX B2D OFFSET TO SIGN-EXTEND E1 AFTER INTERRUPT. FINISH 105,
; 1029 ; TO GET ENTIRE AR LOADED WHILE CLEARING MQ (ARL WAS HOLDING).
; 1030 ; FIX KL PAGING TO USE VMA/1 INSTEAD OF VMA/AD WHEN RESTORING VMA
; 1031 ; FROM VMA HELD OR COPIES THEREOF.
; 1032 ; FIX UFA NOT TO ALWAYS GET UNDERFLOW ON NEGATIVE RESULTS.
; 1033 ; SAME FIX AS EDIT 103 OF BREADBOARD. WHERE DID IT GET LOST?
; 1034 ;105 FIX KL PAGING AS REVISED BY EDIT 103 TO CORRECTLY RESTORE
; 1035 ; BR ON NO-MATCH CONDITION
; 1036 ; ANOTHER FIX TO B2D, TO CLEAR MQ ON ENTRY. BUG INVOLVED GARBAGE
; 1037 ; FROM MQ SHIFTING INTO ARX DURING DEVELOPMENT OF POWER OF TEN.
; 1038 ;104 FIX BINARY TO DECIMAL CONVERSION, WHICH WAS NOT GOING TO CLEAN
; 1039 ; ON FINDING AN INTERRUPT, AND ON RESTART WITH FPD SET, WAS NOT
; 1040 ; SETTING UP SLEN. TSK, TSK. CORRECT CLEANUP FOR DEST FILL IN
; 1041 ; MOVSRJ, WHICH WAS INCREMENTING BOTH SLEN AND DLEN, SHOULD
; 1042 ; HAVE BEEN NEITHER. FIX JSR, BROKEN BY EDIT 103. JUMP MUST BE
; 1043 ; TO E+1, NOT E.
; 1044 ;103 CREATE CONDITIONAL ASSEMBLY FOR EXTENDED ADDRESSING. UNDER IT,
; 1045 ; CREATE MEM FIELD DEFINITIONS, SUPPRESS SXCT.
; 1046 ; SAVE A WORD IN JSR BY USING JSTAC IN COMMON WITH PUSHJ.
; 1047 ; FORCE TIME FIELD IN CASES WHERE ASSEMBLER DEFAULT SCREWS UP.
; 1048 ; ADD INTERRUPT TESTS IN KL PAGING CODE TO PREVENT HANGS, AND
; 1049 ; REVISE PAGE FAIL WORD TO ELIMINATE THE NEW FAIL CODES.
; 1050 ;102 ATTEMPT ANOTHER FIX OF MOVSRJ, CVTBDX FILL. EDIT 71 LOSES
; 1051 ; DUE TO INCONSISTENCY -- DLEN UPDATE MUST NOT PRECEED CLEANUP.
; 1052 ; CREATE CONDITIONAL ASSEMBLY SWITCHES TO CONTROL EXTENDED
; 1053 ; INSTRUCTION SET, DOUBLE INTEGER ARITHMETIC, AND ADJBP. CHANGE
; 1054 ; DEFAULT OF IMULI.OPT, WHICH CAN GET SIGN WRONG ON OVERFLOW.
; 1055 ;101 FIX METER REQUEST CODE TO "ABORT INSTR" EVEN IF NOT SETTING
; 1056 ; PI CYCLE. THIS SHOULD FIX OCCASIONAL LOSS OF TRAPS PROBLEM.
; 1057 ;100 FIXES TO KL PAGING CODE TO PREVENT LOADING VMA FROM AD WHILE
; 1058 ; REQUESTING PHYSICAL REF. FIX JSR TO PREVENT FM PARITY STOP
; 1059 ; ON STORE TO AC. FIX 1777 TO FORCE RECIRCULATION OF AR/ARX,
; 1060 ; EVEN IF MBOX RESP STILL TRUE.
; 1061 ;77 FIX DDIV TO GET MQ SHIFTED LEFT ONE PLACE, WITHOUT INTRODUCING
; 1062 ; AN EXTRA BIT, AT DDVX1. THIS INVOLVES INHIBITING ADA TO PREVENT
; 1063 ; AD CRY0 FROM COMMING INTO MQ35.
; 1064 ;76 FIX UFA TO ALLOW AN EBOX CYCLE BETWEEN FETCH AND NICOND WHEN
; 1065 ; FRACTION SUM IS ZERO, AT UFA3.
; 1066 ;75 PUT BACK INSTRUCTION "MBREL" REMOVED BY EDIT 64. NECESSARY TO
; 1067 ; ENSURE THAT EBOX REQUEST FOR FETCH DOESN'T COME UP WHILE
; 1068 ; REGISTER FUNCTION IS IN PROGRESS, WHICH WOULD CONFUSE MBOX ON
; 1069 ; STARTING THE FETCH.
; 1070 ;74 CHANGES TO EIS FOR NEW-SPEC AC USAGE. CHANGES TO KL PAGING FOR
; 1071 ; INDIRECT, IMMEDIATE SECTION POINTERS
; 1072 ;73 FIX JRA TO PREVENT WRITING AC WITH DATA FRESH FROM MEMORY (ALLOW
; 1073 ; A CYCLE FOR PARITY CHECK). FIX DPB CODE TAKE ONLY 3 TICKS ON
; 1074 ; RETURN FROM BYTEA, SO THAT CACHE DATA DOESN'T ARRIVE INTO AR
; 1075 ; AND ARX UNTIL DPB1, WHEN THE BYTE HAS GOTTEN OUT TO MQ.
; 1076 ;72 FIX DEFINITION OF SP MEM/UNPAGED TO INHIBIT VMA USER. FIX
; KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986 V2A(442) MICRO %37(277) Page 1-19
; EDHIS.MIC[4,24] 12:02 29-May-86 REVISION HISTORY
; 1077 ; PAGE FAIL CODE TO CHECK FOR VMA FETCH BEFORE LOOKING AT
; 1078 ; INTERRUPT REQUEST. PROBLEM WAS INTERRUPT CONCURRENT WITH
; 1079 ; PAGE FAIL ON JRSTF TO USER. PC FLAGS GOT RESTORED, BUT VMA
; 1080 ; NEVER COPIED TO PC BECAUSE PAGE FAIL INHIBITED NICOND, AND
; 1081 ; INTERRUPT ABORTED PAGE FAIL HANDLING TO LOAD PC.
; 1082 ;71 DEFINE FMADR/AC4=6. FIX MOVFIL ROUTINE TO PUT AWAY UPDATED
; 1083 ; LENGTH DIFFERENCE WHEN INTERRUPTED, THUS AVOIDING RANDOMNESS
; 1084 ; IN MOVSRJ, CVTBDX. FIX CVTBD CALL TO MOVFIL TO PRESERVE SR.
; 1085 ; CHANGE STMAC AND PIDONE FROM "FIN XFER" TO "FIN STORE", BECAUSE
; 1086 ; STORE WAS IN PROGRESS, WHICH CAUSED FM WRITE IF AC REF, AND
; 1087 ; GOT A PARITY ERROR DUE TO ADB/FM.
; 1088 ;70 FIX PXCT 4,[POP ...], WHICH DIDN'T GET DEST CONTEXT SET FOR
; 1089 ; STORE. MUST USE SR_100 TO SET IT.
; 1090 ;67 FIX PROBLEM IN ADJBP BY WHICH BYTES/WORD WAS GETTING LOST
; 1091 ; WHEN DIVIDE ROUTINE LOADED REMAINDER INTO BR. SOLVED BY
; 1092 ; SAVING BYTES/WORD IN T1.
; 1093 ;66 FIX KL PAGING TO RESTORE VMA ON TRAP, SAVE ADDRESS OF POINTER
; 1094 ; CAUSING TRAP, AND NOT RESTORE ARX EXCEPT FOR BLT PAGE FAIL.
; 1095 ; ALSO SET TIME PARAMETER ON ADB/FM TO ALLOW TIME FOR PARITY
; 1096 ; CHECKING OF FM.
; 1097 ;65 FIX KL PAGING CODE TO DO MBWAIT AFTER DETERMINING THAT PARITY
; 1098 ; ERROR HAS NOT OCCURRED, SO AS TO GET CORRECT VMA TO SAVE.
; 1099 ; CREATE SYMBOLS FOR KL PAGE FAIL CODES. PUT CONDITIONAL
; 1100 ; ASSEMBLY AROUND IMULI OPTIMIZATION CODE, AND SXCT. CREATE
; 1101 ; SYMBOL "OPTIONS" IN # FIELD FOR MICROCODE OPTIONS.
; 1102 ;64 MICROCODE FOR KL10 PAGING (PAGE REFILL, MAP INSTR)...
; 1103 ; REMOVE UNNECESSARY INSTRUCTION MBREL: FROM SWEEP AND APRBO
; 1104 ; COSMETIC CHANGES TO KEEP COMMENTS & MACRO DEFINITIONS FROM
; 1105 ; OVERFLOWING LINE OF LISTING, AND INSERTION OF CONDITIONAL
; 1106 ; ASSEMBLY CONTROL OF LONG FLOATING POINT INSTRUCTIONS.
; 1107 ;63 IN MTR REQUEST ROUTINE, DON'T DISMISS WHEN PI CYCLE HASN'T
; 1108 ; BEEN SET.
; 1109 ;62 FIX RDMTR CODE TO PUT 35 IN SC BEFORE GOING TO DMOVEM CODE.
; 1110 ;61 FIX PIIBP ROUTINE TO USE CALL.M INSTEAD OF SPEC/CALL,
; 1111 ; WHICH GETS OVERRIDDEN BY P_P-S... IN MTR REQUEST SERVICE
; 1112 ; ROUTINE, DON'T SET PI CYCLE UNLESS REQUEST IS FOR VECTOR.
; 1113 ;60 FIX DATAO PAG TO DO MB WAIT AFTER STORING EBOX ACCT AND
; 1114 ; BEFORE CHANGING VMA.
; 1115 ;57 RE-CODE USES OF A@, B@ TO USE VMA/1, RATHER THAN VMA/AD,
; 1116 ; IN ORDER TO GET CORRECT CONTEXT ON INDIRECT WORD. SEE MCL4
; 1117 ;56 FIX SECOND PART OF PICYCLE (TAG NEXT:) TO ENSURE THAT
; 1118 ; PC+1 INH, KERNEL CYCLE, ETC REMAIN UP DURING 2ND PART.
; 1119 ; ALSO CHANGE SPEC/FLAG CTL FOR ECO 1261, WHICH REQUIRES
; 1120 ; #07 TO BE OPPOSITE OF #04 TO GENERATE SCD LEAVE USER.
; 1121 ;55 FIX SPEC INSTR/SET PI CYCLE TO INHIBIT INTERRUPTS
; 1122 ; (IN PARTICULAR, METER UPDATE REQUESTS). MAKE SURE VALID
; 1123 ; DATA SAVED ON IO PAGE FAIL AND PARITY ERRORS. REMOVE
; 1124 ; BACKWARDS BLT... IT BROKE TOO MANY PROGRAMS.
; 1125 ;54 FIX OVERFLOW CHECK IN IMULI OPTIMIZATION TO INH CRY 18
; 1126 ; UPDATE TO USE CONDITIONAL ASSEMBLY IN MICRO VERS 20.
; 1127 ;53 FIX T1,T2 PARAMETERS ON BYTE DISP, SIGNS DISP
; 1128 ;52 CORRECT SHIFT AMOUNT FOR IMULI OPTIMIZATION, AND FIX MACRO
; 1129 ; DEFINITIONS FOR SET SR?, WHICH WERE ALWAYS SETTING SR0.
; 1130 ;51 OPTIMIZE IMULI OF TWO POSITIVE OPERANDS (TO SPEED UP SUBSCRIPT
; 1131 ; CALCULATIONS) BY TAKING ONLY 9 MULTIPLY STEPS AND STARTING
; 1132 ; NEXT INSTRUCTION FETCH EARLIER. OPTIMIZATION CAN BE REMOVED
; KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986 V2A(442) MICRO %37(277) Page 1-20
; EDHIS.MIC[4,24] 12:02 29-May-86 REVISION HISTORY
; 1133 ; BY COMMENTING OUT TWO INSTRUCTIONS AT IMULI, AND ONE FOLLOWING
; 1134 ; IMUL. ALSO FIX APRBI/UVERS TO KEEP SERIAL # OUT OF LH.
; 1135 ;50 INTRODUCE SKIP/FETCH AND CODE IN PAGE FAIL RECOVERY TO LOAD
; 1136 ; PC FROM VMA IF PAGE FAIL OCCURED ON FETCH, BECAUSE NICOND
; 1137 ; CYCLE, WHICH SHOULD HAVE LOADED PC, GETS INHIBITED BY INSTR 1777
; 1138 ; ALSO INCLUDE EXTENDED INSTRUCTION SET.
; 1139 ;47 UNDO XCT CHANGES OF EDIT 46, WHICH BROKE XCT DUE TO INSUFFICIENT
; 1140 ; TIME FOR DRAM HOLD BEFORE USING "A READ". ALSO FIX VECTOR
; 1141 ; INTERRUPT CODE TO LOOK AT CORRECT BITS FOR CONTROLLER NUMBER.
; 1142 ;46 FOLLOW-ON TO EDIT 45, SAVING 2 WORDS AND A CYCLE
; 1143 ; ALSO MOVE JRST TO 600, JFCL TO 700, UUO'S TO 100X AS PREPARATION
; 1144 ; FOR EXTENDED INSTRUCTION SET
; 1145 ;45 FIX SXCT TO LOOK AT AC FIELD OF SXCT, NOT SUBJECT INSTRUCTION,
; 1146 ; WHEN DECIDING WHETHER TO USE BASE-TYPE ADDRESS CALCULATION.
; 1147 ;44 FIX PAGE FAIL LOGIC TO WORK FOR EITHER PAGE FAIL OR PARITY
; 1148 ; ERROR. EDITS 42 AND 43 BOTH WRONG. ALSO CORRECT RACE IN
; 1149 ; WRITING PERFORMANCE ANALYSIS ENABLES TO PREVENT SPURIOUS COUNTS.
; 1150 ;43 CORRECT USE OF PF DISP BY EDIT 42. LOW BITS ARE INVERTED
; 1151 ;42 FIX BUGS INTRODUCED BY EDIT 40, WHICH MADE FLTR OF 1B0 HANG
; 1152 ; TRYING TO NEGATE IT, AND FIX UP EXPONENT CORRECTION ON LONG
; 1153 ; SHIFT LEFT. ALSO PUT IN CODE TO HANDLE PARITY ERROR PAGE
; 1154 ; FAILURES, AND SET TIME CONTROLS ON 43-47.
; 1155 ;41 REWRITE OF VECTOR INTERRUPT PROCESSING TO MAKE DTE VECTORS
; 1156 ; GO TO 142+8N, WHERE N IS DTE#. RH20 GO TO PROGRAMMED ADDRESS
; 1157 ; IN EPT, EXTERNAL DEVICES USE EXEC VIRTUAL ADDRESSES.
; 1158 ;40 IMPROVEMENTS TO FLOATING NORMALIZATION TO MAKE LONG SHIFTS
; 1159 ; FASTER, PRIMARILY TO HELP FLTR
; 1160 ;37 FIX FLOATING DIVIDE SO THAT THE TRUNCATED FORM OF A NEGATIVE
; 1161 ; QUOTIENT IS EQUAL TO THE HIGH-ORDER PART OF THE INFINITE-
; 1162 ; PRECISION QUOTIENT. SEE COMMENTS IN THE CODE. ALSO BUM
; 1163 ; A CYCLE OUT OF FLOATING DIVIDE BY STARTING THE NORMALIZE
; 1164 ; WHILE MOVING THE QUOTIENT INTO AR.
; 1165 ; SEVERAL CHANGES TO MAKE TRACKS FEATURE WORK
; 1166 ;36 FIX CONO MTR TO PUT DATA ON BOTH HALVES, SO PI CAN SEE PIA
; 1167 ;35 FIX CONI PI TO READ BACK WRITE EVEN PARITY ENABLES
; 1168 ;34 FIX BLT USE OF SR, SO NO CORRECTION OF ARX NECESSARY
; 1169 ;33 FIX PAGE TABLE REFERENCES TO FORCE UNPAGED REF. FIX TRAP
; 1170 ; TO SET PC+1 INHIBIT.
; 1171 ;32 CORRECT SETTING OF SC FOR SHIFTING METER COUNTERS, TO GET
; 1172 ; 12 BITS UNUSED AT RIGHT WHEN IT GETS TO CORE.
; 1173 ;31 RECODE ASH AND ASHC TO SAVE SPACE
; 1174 ;30 FIX JFFO TO SHIFT AR CORRECTLY AT JFFO2. BUM ADJSP TO USE
; 1175 ; STMAC FOR UPDATING PDL POINTER.
; 1176 ;27 FIX CONI PAG TO READ EBUS. CORRECT DEFINITIONS OF MBOX
; 1177 ; REGISTER FUNCTIONS, WHICH HAD BITS 0 AND 3 INVERTED.
; 1178 ;26 FIX DEFINITIONS OF DIAG FUNC CONO MTR AND CONO TIM, WHICH
; 1179 ; WERE REVERSED
; 1180 ;25 FIX DECODING OF PHYSICAL DEVICE NUMBER IN PI FUNCTION CODE
; 1181 ; AND RE-CODE JFCL FOR FEWER MICROWORDS
; 1182 ;24 FIX JFFO TO SHIFT ON FIRST 6-BIT TEST STEP, AND JRSTF TO
; 1183 ; KEEP E AND XR DISTINCT. ALSO SET LOAD-ENABLE BITS IN
; 1184 ; DATAI PAG, WORD.
; 1185 ;23 FIX CONO PI, TO HOLD AR ONTO EBUS THRU REL EBUS, BECAUSE
; 1186 ; PI BOARD DELAYS CONO PI TO GET CONO SET EQUIVALENT.
; 1187 ;22 MORE JFCL FIXES. MUST USE FLAG CTL/JFCL WHILE CLEARING BITS,
; 1188 ; AS WELL AS WHILE TESTING THEM. BUM A WORD OUT OF JFFO BY
; KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986 V2A(442) MICRO %37(277) Page 1-21
; EDHIS.MIC[4,24] 12:02 29-May-86 REVISION HISTORY
; 1189 ; MAKING THE SIXBIT COUNT NEGATIVE. CHANGES SO SHIFT SUBR
; 1190 ; RETURNS 2, BYTEA 1. FIX SETMB TO STORE BACK AND FETCH.
; 1191 ;21 RE-WRITE JFCL TO KEEP LOW OPCODE BITS OUT OF AR0-1, BECAUSE
; 1192 ; PC00 GETS PROPAGATED LEFT TO ADA -1 AND -2.
; 1193 ;20 FIX BLT TO LOAD BR WITH SRC-DST ADDR
; 1194 ; ALSO SET TIME PARAMETERS ON CONDITIONAL FETCH FUNCTIONS
; 1195 ;17 CHANGE SWEEP ONE PAGE TO PUT PAGE # IN E, RATHER THAN ADDR.
; 1196 ; ALSO CHANGE COND/FM WRITE TO MATCH ECO #1068.
; 1197 ;16 FIX JUMP FETCH MACRO TO LOAD VMA FROM PC+1 (TEST SATISFIED
; 1198 ; OVERRIDES THIS TO HOLD VMA). ALSO BUM ONE MICROWORD FROM MUUO.
; 1199 ;15 INCLUDE PAGE FAIL DISP IN DISP/ FIELD
; 1200 ; ALSO MAKE MUUO STORE PROCESS CONTEXT WORD AT 426, AND SETUP
; 1201 ; PCS FROM PC EXTENSION, CWSX FROM SXCT
; 1202 ;14 FIX DEFINITIONS OF SKIP/IO LEGAL, AC#0, SC0, EVEN PAR
; 1203 ; ALSO FIX DATAO PAG, TO SEND LH DATA ON BOTH HALVES OF EBUS
; 1204 ;13 ALIGN SETEBR SO CALL TO SHIFT RETURNS CORRECTLY
; 1205 ;12 MAKE SURE AD COPIES AR DURING DATAO, CONO, AND CLEAR AR AT
; 1206 ; SET DATAI TIME.
; 1207 ;11 FIXES TO CONTINUE CODE SO CONSOLE WORKS, AND CORRECTIONS TO
; 1208 ; PROTECTED DEP/EXAM SO PROTECTION PROTECTS.
; 1209 ;10 FIX A READ MACRO TO VMA/PC+1. AD OVERRIDES UNLESS DRAM A=1
; 1210 ;07 RE-WRITE OF PI CYCLE CODE TO RECOGNIZE NEW EBUS SPEC.
; 1211 ;06 FIX DEFINITIONS OF SKIPS 40-57 BY COMPLEMENTING 3 LOW ORDER BITS
; 1212 ; FIX MULSUB TO CORRESPOND TO NEW CRA LOGIC
; 1213 ;05 FIX EBUS CTL DEFINITIONS TO GET F01 CORRECT. CORRECT FLAG CTL
; 1214 ; DEFINITIONS TO PREVENT LEAVE USER WHEN NOT WANTED, AND FIX
; 1215 ; JRST/JFCL TO HAVE FLAGS IN AR WHEN NEEDED.
; 1216 ;04 FIX RETURNS FROM MULSUB, PUT BETTER COMMENTS ON SNORM CODE,
; 1217 ; IMPROVE SNORM ALGORITHM TO MINIMIZE WORST-CASE TIME.
; 1218 ;03 FIX DISPATCH ADDRESS PROBLEMS, MOSTLY JRST/JFCL AND UUO'S.
; 1219 ;02 CHANGES PER INSTRUCTION SET REVIEW -- DELETE USE OF BIT12 OF
; 1220 ; BYTE POINTERS, CHANGE BLT TO PUT FINAL SRC,DST ADDRESSES IN AC,
; 1221 ; MAKE TRUNCATE FORM FLOATING POINT REALLY TRUNCATE, ELIMINATE
; 1222 ; LOCAL JSYS SUPPORT, DELETE PXCT OPCODE (XCT W/ NON-ZERO AC IN
; 1223 ; EXEC MODE), LUUO'S GO TO 40/41 OF CURRENT SPACE.
; 1224 ;01 UPDATES FOR .TITLE AND .TOC PSEUDO OPS,
; 1225 ; AND VARIOUS CHANGES FOR PROTO HARDWARE
; 1226 ;00 CREATION, BASED ON BREADBOARD AS OF EDIT 66
; 1227 .BIN
; 1228
; KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986 V2A(442) MICRO %37(277) Page 1
; DEFINE.MIC[4,24] 16:58 23-May-86 CONDITIONAL ASSEMBLY VARIABLE DEFINITIONS
; 1229 .TOC "CONDITIONAL ASSEMBLY VARIABLE DEFINITIONS"
; 1230 .NOBIN
; 1231
; 1232 ; [COST ESTIMATES IN BRACKETS INDICATE NUMBER OF ADDITIONAL
; 1233 ; MICROINSTRUCTIONS REQUIRED BY TURNING ON THE FEATURE SWITCH]
; 1234
; 1235 .DEFAULT/TRACKS=0 ;1 ENABLES STORING PC AFTER EVERY INSTRUCTION,
; 1236 ; & CREATES DATAI/O PI TO READ/SETUP PC BUFFER
; 1237 ;ADDRESS. [COST = 21 WDS]
; 1238
; 1239 .DEFAULT/OP.CNT=0 ;1 ENABLES CODE TO BUILD A HISTOGRAM IN CORE
; 1240 ; COUNTING USES OF EACH OPCODE IN USER & EXEC
; 1241
; 1242 .DEFAULT/OP.TIME=0 ;1 ENABLES CODE TO ACCUMULATE TIME SPENT BY
; 1243 ; EACH OPCODE
; 1244
; 1245 .DEFAULT/SO.CNT=0 ;SECOND ORDER COUNTING IN 128K STARTING AT LOC
; 1246 ; 400000 NOT DEBUGED [COST = 28 WDS]
; 1247
; 1248 .DEFAULT/SO2.CNT=0 ;SECOND ORDER COUNTING IN 128K STARTING AT LOC
; 1249 ; PRESENTED AT START DOES ONE MORE ADD THAN
; 1250 ; SO.CNT AND HENCE AN INSTRUCTION TAKES
; 1251 ; 120 NS LONGER THAN SO.CNT [COST = 28 WDS]
; 1252
; 1253 .DEFAULT/PAGCNT=0 ;Enable code to count entries into the PFH and
; 1254 ; number of DATAO PAGs with bit 2 set. [Cost =
; 1255 ; 6 words] [327]
; 1256
; 1257 .DEFAULT/FPLONG=1 ;1 ENABLES KA-STYLE DOUBLE PRECISION FLOATING
; 1258 ;POINT INSTRUCTIONS: FADL, FSBL, FMPL, FDVL,
; 1259 ; UFA, DFN. [COST = 49 WDS]
; 1260
; 1261 .DEFAULT/MULTI=0 ;1 IF MULTIPROCESSOR SYSTEM, TO SUPPRESS CACHE
; 1262 ;ON UNPAGED REF'S. PAGED REF'S ARE UP TO EXEC.
; 1263
; 1264 .DEFAULT/MOS.MULTI=0 ;1 if we have multiported MOS memory. This hardware
; 1265 ;project was abandoned before it was completed.
; 1266 ;[Cost = 5 wds.]
; 1267
; 1268 .DEFAULT/SNORM.OPT=0 ;1 ENABLES FASTER NORMALIZATION OF SINGLE-
; 1269 ; PRECISION RESULTS WHICH HAVE SEVERE LOSS OF
; 1270 ; SIGNIFICANCE [COST = 4 WDS]
; 1271
;;1272 .IF/TRACKS ;SETUP CONTROL FOR COMMON CODE
;;1273 .SET/INSTR.STAT=1
; 1274 .ENDIF/TRACKS
; 1275
;;1276 .IF/OP.CNT
;;1277 .SET/INSTR.STAT=1 ;ENABLE COMMON CODE, ERROR IF TRACKS TOO
; 1278 .ENDIF/OP.CNT
; 1279
;;1280 .IF/OP.TIME
;;1281 .SET/INSTR.STAT=1 ;ERROR IF TRACKS OR OP.CNT ALSO SET
; 1282 .ENDIF/OP.TIME
; 1283
;;1284 .IF/SO.CNT
; KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986 V2A(442) MICRO %37(277) Page 1-1
; DEFINE.MIC[4,24] 16:58 23-May-86 CONDITIONAL ASSEMBLY VARIABLE DEFINITIONS
;;1285 .SET/INSTR.STAT=1
; 1286 .ENDIF/SO.CNT
; 1287
;;1288 .IF/SO2.CNT
;;1289 .SET/INSTR.STAT=1
; 1290 .ENDIF/SO2.CNT
; 1291
; 1292 .DEFAULT/INSTR.STAT=0 ;IF NO STATISTICS, TURN OFF COMMON CODE
; 1293
;;1294 .IF/INSTR.STAT
;;1295 .SET/NONSTD=1 ;STATISTICS CODE IS NONSTANDARD
;;1296 .SET/TRXDEF=1 ;Make sure TRX registers get defined [327]
; 1297 .ENDIF/INSTR.STAT
; 1298
;;1299 .IF/PAGCNT
;;1300 .SET/NONSTD=1 ;All statistics are nonstandard
;;1301 .SET/TRXDEF=1 ;We need the TRX registers
; 1302 .ENDIF/PAGCNT
; 1303
; 1304 .DEFAULT/TRXDEF=0 ;Normally no TRX registers needed
; 1305
; 1306 .DEFAULT/NONSTD=0 ;NONSTANDARD MICROCODE IS NORMALLY OFF
; 1307 .DEFAULT/OWGBP=0 ;[264]
; 1308 .DEFAULT/IPA20=0 ;[264]
; 1309 .DEFAULT/NOCST=0 ;[264]
; 1310 .DEFAULT/CST.WRITE=1 ;[314] Enable CST writable bit
; 1311 .DEFAULT/BIG.PT=1 ;[333][347] Special code for big page table and Keep bit
; 1312 .DEFAULT/DDT.BUG=0 ;[346] If on, enable APRID hack to move bit 23
; 1313 .DEFAULT/GFTCNV=1 ;[273] GFLOAT CONVERSION INST.
; 1314 .DEFAULT/EDIT=1 ;Edit is usually here ****HACK****
; 1315
; KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986 V2A(442) MICRO %37(277) Page 2
; DEFINE.MIC[4,24] 16:58 23-May-86 HOW TO READ THE MICROCODE -- FORMATS & CONSTRUCTS
; 1316 .TOC "HOW TO READ THE MICROCODE -- FORMATS & CONSTRUCTS"
; 1317
; 1318 ;(1) FIELD DEFINITIONS
; 1319 ; THESE OCCUR AT THE BEGINNING OF THE LISTING, IN THE SOURCE FILE
; 1320 ; DEFINE.MIC (CONTROL AND DISPATCH RAM DEFINITIONS).
; 1321 ; THEY HAVE THE FORM:
; 1322 ; SYMBOL/=<L:R>M,J
; 1323 ;ANOTHER FORM ACCEPTED BY THE ASSEMBLER (FOR HISTORIC REASONS) IS:
; 1324 ; SYMBOL/=J,K,R,M ;THIS FORM HAS BEEN REMOVED FROM THIS CODE
; 1325 ; THE PARAMETER (J) IS MEANINGFUL ONLY WHEN "D" IS SPECIFIED
; 1326 ; AS THE DEFAULT MECHANISM, AND IN THAT CASE, GIVES THE DEFAULT VALUE OF
; 1327 ; THE FIELD IN OCTAL.
; 1328 ; THE PARAMETER (K) GIVES THE FIELD SIZE IN (DECIMAL) NUMBER
; 1329 ; OF BITS. THIS IS USED ONLY IN THE OUTDATED FORMAT.
; 1330 ; THE PARAMETER (L) GIVES THE BIT POSITION OF THE LEFTMOST BIT
; 1331 ;IN THE FIELD. THE SAME METHOD IS USED AS FOR (R) BELOW.
; 1332 ; THE PARAMETER (R) GIVES THE FIELD POSITION IN DECIMAL
; 1333 ; AS THE BIT NUMBER OF THE RIGHTMOST BIT OF THE FIELD. BITS ARE NUMBERED
; 1334 ; FROM 0 ON THE LEFT. NOTE THAT THE POSITION OF BITS IN THE MICROWORD
; 1335 ; SHOWN IN THE LISTING BEARS NO RELATION TO THE ORDERING OF BITS IN THE
; 1336 ; HARDWARE MICROWORD, WHERE FIELDS ARE OFTEN BROKEN UP AND SCATTERED.
; 1337 ; THE PARAMETER (M) IS OPTIONAL, AND SELECTS A DEFAULT
; 1338 ; MECHANISM FOR THE FIELD. THE LEGAL VALUES OF THIS PARAMETER ARE THE
; 1339 ; CHARACTERS "D", "T", "P", OR "+".
; 1340 ; "D" MEANS (J) IS THE DEFAULT VALUE OF THE FIELD IF NO EXPLICIT
; 1341 ; VALUE IS SPECIFIED.
; 1342 ; "T" IS USED ON THE TIME FIELD TO SPECIFY THAT THE VALUE OF THE
; 1343 ; FIELD DEPENDS ON THE TIME PARAMETERS SELECTED FOR OTHER FIELDS.
; 1344 ; THE VALUE OF A FIELD WITH THIS SPECIFICATION DEFAULTS TO THE
; 1345 ; MAX OF <SUM OF THE T1 PARAMETERS DEFINED FOR FIELD/VALUES
; 1346 ; SPECIFIED IN THIS MICROINSTRUCTION>, <SUM OF THE T2 PARAMETERS
; 1347 ; FOR THIS MICROINSTRUCTION>, <J PARAMETER OF THIS FIELD>.
; 1348 ; WITHIN THE KL10 MICROCODE, T1 PARAMETERS ARE USED TO SPECIFY
; 1349 ; FUNCTIONS WHICH DEPEND ON THE ADDER SETUP TIME, AND T2 PARAMETERS
; 1350 ; ARE USED FOR FUNCTIONS WHICH REQUIRE ADDITIONAL TIME FOR CORRECT
; 1351 ; SELECTION OF THE NEXT MICROINSTRUCTION ADDRESS.
; 1352 ; "P" IS USED ON THE PARITY FIELD TO SPECIFY THAT THE VALUE OF THE
; 1353 ; FIELD SHOULD DEFAULT SUCH THAT PARITY OF THE ENTIRE WORD
; 1354 ; IS ODD. IF THIS OPTION IS SELECTED ON A FIELD WHOSE SIZE (K) IS
; 1355 ; ZERO, THE MICRO ASSEMBLER WILL ATTEMPT TO FIND A BIT SOMEWHERE
; 1356 ; IN THE WORD FOR WHICH NO VALUE IS SPECIFIED OR DEFAULTED.
; 1357 ; "+" IS USED ON THE JUMP ADDRESS FIELD TO SPECIFY THAT THE DEFAULT
; 1358 ; JUMP ADDRESS IS THE ADDRESS OF THE NEXT INSTRUCTION ASSEMBLED (NOT,
; 1359 ; IN GENERAL, THE CURRENT LOCATION +1).
; 1360 ; IN GENERAL, A FIELD CORRESPONDS TO THE SET OF BITS WHICH PROVIDE
; 1361 ; SELECT INPUTS FOR MIXERS OR DECODERS, OR CONTROLS FOR ALU'S.
; 1362 ; EXAMPLES:
; 1363 ; AR/=<24:26>D,0 OR AR/=0,3,26,D
; 1364 ; THE MICROCODE FIELD WHICH CONTROLS THE AR MIXER (AND THEREFORE
; 1365 ; THE DATA TO BE LOADED INTO AR ON EACH EBOX CLOCK) IS THREE BITS WIDE
; 1366 ; AND THE RIGHTMOST BIT IS SHOWN IN THE LISTING AS BIT 26 OF THE
; 1367 ; MICROINSTRUCTION. IF NO VALUE IS SPECIFICALLY REQUESTED FOR THE FIELD,
; 1368 ; THE MICROASSEMBLER WILL ENSURE THAT THE FIELD IS 0.
; 1369 ; AD/=<12:17> OR AD/=0,6,17
; 1370 ; THE FIELD WHICH CONTROLS THE AD IS 6 BITS WIDE, ENDING ON
; 1371 ; BIT 17. THE FOURTH PARAMETER OF THE FIELD IS OMITTED, SO THE FIELD
; KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986 V2A(442) MICRO %37(277) Page 2-1
; DEFINE.MIC[4,24] 16:58 23-May-86 HOW TO READ THE MICROCODE -- FORMATS & CONSTRUCTS
; 1372 ; IS AVAILABLE TO THE MICROASSEMBLER (IF NO VALUE IS EXPLICITLY
; 1373 ; CALLED OUT FOR THE FIELD) FOR MODIFICATION TO ENSURE ODD PARITY IN THE
; 1374 ; ENTIRE WORD.
; 1375 ;
; 1376 ;(2) VALUE DEFINITIONS
; 1377 ; FOLLOWING A FIELD DEFINITION, SYMBOLS MAY BE CREATED IN THAT
; 1378 ; FIELD TO CORRESPOND TO VALUES OF THE FIELD. THE FORM IS:
; 1379 ; SYMBOL=N,T1,T2
; 1380 ; "N" IS, IN OCTAL, THE VALUE OF SYMBOL WHEN USED IN THE FIELD.
; 1381 ; T1 AND T2 ARE OPTIONAL, AND SPECIFY PARAMETERS IN THE TIME FIELD
; 1382 ; CALCULATION FOR MICROINSTRUCTIONS IN WHICH THIS FIELD/SYMBOL IS USED.
; 1383 ; THE MICROASSEMBLER COMPUTES THE SUMS OF ALL THE T1'S AND ALL THE T2'S
; 1384 ; SPECIFIED FOR FIELD/SYMBOL SPECIFICATIONS IN A WORD, AND USES THE MAX
; 1385 ; OF THE TWO SUMS AS THE DEFAULT VALUE FOR THE FIELD WHOSE DEFAULT
; 1386 ; MECHANISM IS "T". EXAMPLES:
; 1387 ; AD/=<12:17> ;FIELD DEFINITION IN WHICH FOLLOWING SYMBOLS EXIST
; 1388 ; XOR=31
; 1389 ; A+B=6,1
; 1390 ; HERE THE SYMBOLS "XOR" AND "A+B" ARE DEFINED FOR THE "AD" FIELD.
; 1391 ; TO THE ASSEMBLER, THEREFORE, WRITING "AD/XOR" MEANS PUT THE VALUE 31
; 1392 ; INTO THE 6-BIT FIELD ENDING ON BIT 17 OF THE MICROWORD. THE SYMBOLS
; 1393 ; ARE CHOSEN FOR MNEMONIC SIGNIFICANCE, OF COURSE, SO ONE READING
; 1394 ; THE MICROCODE WOULD INTERPRET "AD/XOR" AS "THE OUTPUT OF AD SHALL BE THE
; 1395 ; EXCLUSIVE OR OF ITS A AND B INPUTS". SIMILIARLY, "AD/A+B" IS READ AS
; 1396 ; "AD PRODUCES THE SUM OF A AND B". THE SECOND PARAMETER IN THE DEFINITION
; 1397 ; OF "A+B" IS A CONTROL TO THE MICRO ASSEMBLER'S TIME-FIELD CALCULATION,
; 1398 ; WHICH TELLS THE ASSEMBLER THAT THIS OPERATION TAKES LONGER THAN THE
; 1399 ; BASIC CYCLE, AND THEREFORE THAT THE TIME FIELD SHOULD BE INCREASED.
; 1400 ; AR/=<24:26>D,0 ;FIELD DEFINITION FOR FOLLOWING SYMBOLS
; 1401 ; AR=0
; 1402 ; AD=2
; 1403 ; HERE THE SYMBOLS "AR" AND "AD" ARE DEFINED FOR THE FIELD NAMED
; 1404 ; "AR", WHICH CONTROLS THE AR MIXER. WE COULD WRITE AR/AR TO MEAN THAT
; 1405 ; THE AR MIXER SELECT INPUTS WOULD BE 0, WHICH IN THE
; 1406 ; HARDWARE SELECTS THE AR OUTPUT FOR RECIRCULATION TO THE REGISTER. IN
; 1407 ; PRACTICE, HOWEVER, WE WANT THIS TO BE THE DEFAULT CASE, SO THAT AR
; 1408 ; DOES NOT CHANGE UNLESS WE SPECIFICALLY REQUEST IT, SO THE FIELD
; 1409 ; DEFINITION SPECIFIES 0 AS THE DEFAULT VALUE OF THE FIELD. IF WE
; 1410 ; WANT AR LOADED FROM THE AD OUTPUT, WE WRITE "AR/AD" TO SET THE
; 1411 ; MIXER SELECTS TO PASS THE AD OUTPUT INTO THE AR.
; 1412 ;
; 1413 ;(3) LABEL DEFINITIONS
; 1414 ; A MICRO INSTRUCTION MAY BE LABELLED BY A SYMBOL FOLLOWED BY COLON
; 1415 ; PRECEDING THE MICROINSTRUCTION DEFINITION. THE ADDRESS OF THE
; 1416 ; MICROINSTRUCTION BECOMES THE VALUE OF THE SYMBOL IN THE FIELD NAMED "J".
; 1417 ; EXAMPLE:
; 1418 ; FOO: J/FOO
; 1419 ; THIS IS A MICROINSTRUCTION WHOSE "J" FIELD (JUMP ADDRESS) CONTAINS
; 1420 ; THE VALUE "FOO". IT ALSO DEFINES THE SYMBOL "FOO" TO BE THE ADDRESS
; 1421 ; OF ITSELF. THEREFORE, IF EXECUTED BY THE MICROPROCESSOR, IT WOULD
; 1422 ; LOOP ON ITSELF.
; 1423 ;
; 1424 ;(4) COMMENTS
; 1425 ; A SEMICOLON ANYWHERE ON A LINE CAUSES THE REST OF THE LINE
; 1426 ; TO BE IGNORED BY THE ASSEMBLER. THIS TEXT IS AN EXAMPLE OF COMMENTS.
; 1427 ;
; KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986 V2A(442) MICRO %37(277) Page 2-2
; DEFINE.MIC[4,24] 16:58 23-May-86 HOW TO READ THE MICROCODE -- FORMATS & CONSTRUCTS
; 1428 ;(5) MICROINSTRUCTION DEFINITION
; 1429 ; A WORD OF MICROCODE IS DEFINED BY SPECIFYING A FIELD NAME,
; 1430 ; FOLLOWED BY SLASH (/), FOLLOWED BY A VALUE. THE VALUE MAY BE A
; 1431 ; SYMBOL DEFINED FOR THAT FIELD, AN OCTAL DIGIT STRING, OR A DECIMAL
; 1432 ; DIGIT STRING (DISTINGUISHED BY THE FACT THAT IT CONTAINS "8" AND/OR
; 1433 ; "9" AND/OR IS TERMINATED BY A PERIOD). SEVERAL FIELDS MAY BE SPECIFIED
; 1434 ; IN ONE MICROINSTRUCTION BY SEPARATING FIELD/VALUE SPECIFICATIONS WITH
; 1435 ; COMMAS. EXAMPLE:
; 1436 ; ADB/BR,ADA/AR,AD/A+B,AR/AD
; 1437 ; THE FIELD NAMED "ADB" IS GIVEN THE VALUE NAMED "BR" (TO
; 1438 ; CAUSE THE MIXER ON THE B SIDE OF AD TO SELECT BR), FIELD "ADA" HAS VALUE
; 1439 ; "AR", FIELD "AD" HAS VALUE "A+B", AND FIELD "AR" HAS VALUE "AD".
; 1440 ;
; 1441 ;(6) CONTINUATION
; 1442 ; THE DEFINITION OF A MICROINSTRUCTION MAY CONTINUED ONTO TWO OR
; 1443 ; MORE LINES BY BREAKING IT AFTER ANY COMMA. IN OTHER WORDS, IF THE
; 1444 ; LAST NON-BLANK, NON-COMMENT CHARACTER ON A LINE IS A COMMA, THE
; 1445 ; INSTRUCTION SPECIFICATION IS CONTINUED ON THE FOLLOWING LINE.
; 1446 ; EXAMPLE:
; 1447 ; ADB/BR,ADA/AR, ;SELECT AR & BR AS AD INPUTS
; 1448 ; AD/A+B,AR/AD ;TAKE THE SUM INTO AR
; 1449 ; BY CONVENTION, CONTINUATION LINES ARE INDENTED AN EXTRA TAB.
; 1450 ;
; 1451 ;(7) MACROS
; 1452 ; A MACRO IS A SYMBOL WHOSE VALUE IS ONE OR MORE FIELD/VALUE
; 1453 ; SPECIFICATIONS AND/OR MACROS. A MACRO DEFINITION IS A LINE CONTAINING
; 1454 ; THE MACRO NAME FOLLOWED BY A QUOTED STRING WHICH IS THE VALUE OF THE
; 1455 ; MACRO. EXAMPLE:
; 1456 ; AR_AR+BR "ADB/BR,ADA/AR,AD/A+B,AR/AD"
; 1457 ; THE APPEARANCE OF A MACRO IN A MICROINSTRUCTION DEFINITION IS EQUIVALENT
; 1458 ; TO THE APPEARANCE OF ITS VALUE. MACROS FOR VARIOUS FUNCTIONS
; 1459 ; ARE DEFINED IN "MACRO.MIC".
; 1460 ;
; 1461 ;(8) PSEUDO OPS
; 1462 ; THE MICRO ASSEMBLER HAS 10 PSEUDO-OPERATORS:
; 1463 ;.DCODE AND .UCODE SELECT THE RAM INTO WHICH SUBSEQUENT MICROCODE WILL
; 1464 ;BE LOADED, AND THEREFORE THE FIELD DEFINITIONS AND MACROS WHICH ARE
; 1465 ;MEANINGFUL IN SUBSEQUENT MICROCODE
; 1466 ;.TITLE DEFINES A STRING OF TEXT TO APPEAR IN THE PAGE HEADER, AND
; 1467 ;.TOC DEFINES AN ENTRY FOR THE TABLE OF CONTENTS AT THE BEGINNING.
; 1468 ;.SET DEFINES THE VALUE OF A CONDITIONAL ASSEMBLY PARAMETER,
; 1469 ;.CHANGE REDEFINES A CONDITIONAL ASSEMBLY PARAMETER,
; 1470 ;.DEFAULT ASSIGNS A VALUE TO AN UNDEFINED PARAMETER.
; 1471 ;.IF ENABLES ASSEMBLY IF THE VALUE OF THE PARAMETER IS NOT ZERO,
; 1472 ;.IFNOT ENABLES ASSEMBLY IF THE PARAMETER VALUE IS ZERO, AND
; 1473 ;.ENDIF RE-ENABLES ASSEMBLY IF SUPPRESSED BY THE PARAMETER NAMED.
; 1474 ;
; 1475 ;(9) LOCATION CONTROL
; 1476 ; A MICROINSTRUCTION "LABELLED" WITH A NUMBER IS ASSIGNED TO THAT
; 1477 ; ADDRESS.
; 1478 ; THE CHARACTER "=" AT THE BEGINNING OF A LINE, FOLLOWED BY
; 1479 ; A STRING OF 0'S, 1'S, AND/OR *'S, SPECIFIES A CONSTRAINT ON THE
; 1480 ; ADDRESS OF FOLLOWING MICROINSTRUCTIONS. THE NUMBER OF CHARACTERS
; 1481 ; IN THE CONSTRAINT STRING (EXCLUDING THE "=") IS THE NUMBER OF LOW-ORDER
; 1482 ; BITS CONSTRAINED IN THE ADDRESS. THE MICROASSEMBLER ATTEMPTS TO FIND
; 1483 ; AN UNUSED LOCATION WHOSE ADDRESS HAS 0 BITS IN THE POSITIONS
; KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986 V2A(442) MICRO %37(277) Page 2-3
; DEFINE.MIC[4,24] 16:58 23-May-86 HOW TO READ THE MICROCODE -- FORMATS & CONSTRUCTS
; 1484 ; CORRESPONDING TO 0'S IN THE CONSTRAINT STRING AND 1 BITS WHERE THE
; 1485 ; CONSTRAINT HAS 1'S. ASTERISKS DENOTE "DON'T CARE" BIT POSITIONS.
; 1486 ; IF THERE ARE ANY 0'S IN THE CONSTRAINT STRING, THE CONSTRAINT
; 1487 ; IMPLIES A BLOCK OF <2**N> MICROWORDS, WHERE N IS THE NUMBER OF 0'S
; 1488 ; IN THE STRING. ALL LOCATIONS IN THE BLOCK WILL HAVE 1'S IN THE ADDRESS
; 1489 ; BITS CORRESPONDING TO 1'S IN THE STRING, AND BIT POSITIONS DENOTED BY *'S
; 1490 ; WILL BE THE SAME IN ALL LOCATIONS OF THE BLOCK.
; 1491 ; IN SUCH A CONSTRAINT BLOCK, THE DEFAULT ADDRESS PROGRESSION IS
; 1492 ; COUNTING IN THE "0" POSITIONS OF THE CONSTRAINT STRING, BUT A NEW
; 1493 ; CONSTRAINT STRING OCCURING WITHIN A BLOCK MAY FORCE SKIPPING OVER
; 1494 ; SOME LOCATIONS OF THE BLOCK. WITHIN A BLOCK, A NEW CONSTRAINT
; 1495 ; STRING DOES NOT CHANGE THE PATTERN OF DEFAULT ADDRESS PROGRESSION, IT
; 1496 ; MERELY ADVANCES THE LOCATION COUNTER OVER THOSE LOCATIONS. THE
; 1497 ; MICROASSEMBLER WILL LATER FILL THEM IN.
; 1498 ; A NULL CONSTRAINT STRING ("=" FOLLOWED BY ANYTHING BUT "0",
; 1499 ; "1", OR "*") SERVES TO TERMINATE A CONSTRAINT BLOCK.
; 1500 ; EXAMPLES:
; 1501 ; =0
; 1502 ; THIS SPECIFIES THAT THE LOW-ORDER ADDRESS BIT MUST BE ZERO--
; 1503 ; THE MICROASSEMBLER FINDS AN EVEN-ODD PAIR OF LOCATIONS, AND PUTS
; 1504 ; THE NEXT TWO MICROINSTRUCTIONS INTO THEM.
; 1505 ; =11
; 1506 ; THIS SPECIFIES THAT THE TWO LOW-ORDER BITS OF THE ADDRESS MUST
; 1507 ; BOTH BE ONES. SINCE THERE ARE NO 0'S IN THIS CONSTRAINT, THE
; 1508 ; ASSEMBLER FINDS ONLY ONE LOCATION MEETING THE CONSTRAINT.
; 1509 ; =0*****
; 1510 ; THIS SPECIFIES AN ADDRESS IN WHICH THE "40" BIT IS ZERO. DUE
; 1511 ; TO THE IMPLEMENTATION OF THIS FEATURE IN THE ASSEMBLER, THE DEFAULT
; 1512 ; ADDRESS PROGRESSION APPLIES ONLY TO THE LOW-ORDER 5 BITS, SO THIS
; 1513 ; CONSTRAINT FINDS ONE WORD IN WHICH THE "40" BIT IS ZERO, AND DOES
; 1514 ; NOT ATTEMPT TO FIND ONE IN WHICH THAT BIT IS A ONE.
; 1515 ;THIS LIMITATION HAS BEEN CHANGED WITH NEWER ASSEMBLER VERSIONS.
; 1516 ;HOWEVER NONE OF THE LOCATIONS IN THE MICROCODE REQUIRE ANYTHING BUT THE
; 1517 ;CONSTRAINT MENTIONED ABOVE.
; 1518
; KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986 V2A(442) MICRO %37(277) Page 3
; DEFINE.MIC[4,24] 16:58 23-May-86 MICROCODE LISTING TEMPLATE
; 1519 .TOC "MICROCODE LISTING TEMPLATE"
; 1520 ;HERE IS A TEMPLATE WHICH CAN BE USED WITH THE MICROCODE
; 1521 ; LISTING TO IDENTIFY FIELDS IN THE OUTPUT --
; 1522
; 1523
; 1524 ; ---- ---- ---- ---- ---- ---- ---- ----
; 1525 ; [--] [--] []!! !!!! !!!! !![] [][] ![-]
; 1526 ; ! ! !!! !!!! !!!! !! ! ! ! ! + # = MAGIC NUMBERS
; 1527 ; ! ! !!! !!!! !!!! !! ! ! ! + MARK = SCOPE SYNC
; 1528 ; ! ! !!! !!!! !!!! !! ! ! !
; 1529 ; ! ! !!! !!!! !!!! !! ! ! + CALL, DISP/SPEC = SPEC FUNCTIONS
; 1530 ; ! ! !!! !!!! !!!! !! ! + SKIP/COND = SPECIAL FUNCTIONS
; 1531 ; ! ! !!! !!!! !!!! !! !
; 1532 ; ! ! !!! !!!! !!!! !! + TIME, MEM = UINST TIME & MEM FUNCTION
; 1533 ; ! ! !!! !!!! !!!! !+ VMA = VMA INPUT SELECT
; 1534 ; ! ! !!! !!!! !!!! + SH/ARMM = SH FUNCTION / ARMM SELECT
; 1535 ; ! ! !!! !!!! !!!!
; 1536 ; ! ! !!! !!!! !!!+ SC, FE = SC INPUT SELECT & FE LOAD
; 1537 ; ! ! !!! !!!! !!+ SCADB = SELECT FOR SCAD "B" INPUT
; 1538 ; ! ! !!! !!!! !+ SCADA = ENABLE AND SELECT FOR SCAD "A" INPUT
; 1539 ; ! ! !!! !!!! + SCAD = SC/FE ADDER FUNCTION
; 1540 ; ! ! !!! !!!!
; 1541 ; ! ! !!! !!!+ FM ADR = FAST MEMORY ADDRESS SELECT
; 1542 ; ! ! !!! !!+ BR, BRX, MQ = LOAD BR & BRX, SEL FOR MQ
; 1543 ; ! ! !!! !+ ARX = SELECT FOR ARX INPUT
; 1544 ; ! ! !!! + AR = SELECT FOR AR INPUT
; 1545 ; ! ! !!!
; 1546 ; ! ! !!+ ADB = SELECT FOR ADDER "B" INPUT
; 1547 ; ! ! !+ ADA = SELECT AND ENABLE FOR ADDER "A" INPUT
; 1548 ; ! ! + AD = OPERATION IN ADDER AND ADDER EXTENSION
; 1549 ; ! !
; 1550 ; ! + J = BASE ADDRESS TO WHICH THIS MICROINSTRUCTION JUMPS
; 1551 ; !
; 1552 ; + LOCATION IN CRAM INTO WHICH THIS WORD IS LOADED
; 1553 ;
; 1554 ; U/V = MICRO INSTRUCTION FOR CRAM
; 1555
; 1556 ;*******************************************************************
; 1557
; 1558 ; D = WORD FOR DRAM
; 1559 ;
; 1560 ; + LOCATION IN DRAM INTO WHICH THIS WORD IS LOADED
; 1561 ; !
; 1562 ; ! + A = OPERAND ACCESS CONTROL
; 1563 ; ! !+ B = INSTRUCTION "MODE"
; 1564 ; ! !! + P = PARITY FOR THIS WORD
; 1565 ; ! !! !
; 1566 ; ! !! ! + J = ADDRESS OF HANDLER FOR THIS INSTRUCTION
; 1567 ; [--] !! ! [--]
; 1568 ; ---- ---- ----
; 1569
; KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986 V2A(442) MICRO %37(277) Page 4
; DEFINE.MIC[4,24] 16:58 23-May-86 KL10 INSTRUCTION OPCODE MAP
; 1570 .TOC "KL10 INSTRUCTION OPCODE MAP"
; 1571
; 1572 ; 0 1 2 3 4 5 6 7
; 1573 ;100 (UUO) (UUO) GFAD GFSB JSYS ADJSP GFMP GFDV
; 1574 ;110 DFAD DFSB DFMP DFDV DADD DSUB DMUL DDIV
; 1575 ;120 DMOVE DMOVN FIX EXTEND DMOVEM DMOVNM FIXR FLTR
; 1576 ;130 (UFA) (DFN) FSC IBP ILDB LDB IDPB DPB
; 1577 ;140 FAD (FADL) FADM FADB FADR FADRI FADRM FADRB
; 1578 ;150 FSB (FSBL) FSBM FSBB FSBR FSBRI FSBRM FSBRB
; 1579 ;160 FMP (FMPL) FMPM FMPB FMPR FMPRI FMPRM FMPRB
; 1580 ;170 FDV (FDVL) FDVM FDVB FDVR FDVRI FDVRM FDVRB
; 1581 ; 0 1 2 3 4 5 6 7
; 1582 ;200 MOVE MOVEI MOVEM MOVES MOVS MOVSI MOVSM MOVSS
; 1583 ;210 MOVN MOVNI MOVNM MOVNS MOVM MOVMI MOVMM MOVMS
; 1584 ;220 IMUL IMULI IMULM IMULB MUL MULI MULM MULB
; 1585 ;230 IDIV IDIVI IDIVM IDIVB DIV DIVI DIVM DIVB
; 1586 ;240 ASH ROT LSH JFFO ASHC ROTC LSHC (UUO)
; 1587 ;250 EXCH BLT AOBJP AOBJN JRST JFCL XCT MAP
; 1588 ;260 PUSHJ PUSH POP POPJ JSR JSP JSA JRA
; 1589 ;270 ADD ADDI ADDM ADDB SUB SUBI SUBM SUBB
; 1590 ; 0 1 2 3 4 5 6 7
; 1591 ;300 CAI CAIL CAIE CAILE CAIA CAIGE CAIN CAIG
; 1592 ;310 CAM CAML CAME CAMLE CAMA CAMGE CAMN CAMG
; 1593 ;320 JUMP JUMPL JUMPE JUMPLE JUMPA JUMPGE JUMPN JUMPG
; 1594 ;330 SKIP SKIPL SKIPE SKIPLE SKIPA SKIPGE SKIPN SKIPG
; 1595 ;340 AOJ AOJL AOJE AOJLE AOJA AOJGE AOJN AOJG
; 1596 ;350 AOS AOSL AOSE AOSLE AOSA AOSGE AOSN AOSG
; 1597 ;360 SOJ SOJL SOJE SOJLE SOJA SOJGE SOJN SOJG
; 1598 ;370 SOS SOSL SOSE SOSLE SOSA SOSGE SOSN SOSG
; 1599 ; 0 1 2 3 4 5 6 7
; 1600 ;400 SETZ SETZI SETZM SETZB AND ANDI ANDM ANDB
; 1601 ;410 ANDCA ANDCAI ANDCAM ANDCAB SETM SETMI SETMM SETMB
; 1602 ;420 ANDCM ANDCMI ANDCMM ANDCMB SETA SETAI SETAM SETAB
; 1603 ;430 XOR XORI XORM XORB IOR IORI IORM IORB
; 1604 ;440 ANDCB ANDCBI ANDCBM ANDCBB EQV EQVI EQVM EQVB
; 1605 ;450 SETCA SETCAI SETCAM SETCAB ORCA ORCAI ORCAM ORCAB
; 1606 ;460 SETCM SETCMI SETCMM SETCMB ORCM ORCMI ORCMM ORCMB
; 1607 ;470 ORCB ORCBI ORCBM ORCBB SETO SETOI SETOM SETOB
; 1608 ; 0 1 2 3 4 5 6 7
; 1609 ;500 HLL HLLI HLLM HLLS HRL HRLI HRLM HRLS
; 1610 ;510 HLLZ HLLZI HLLZM HLLZS HRLZ HRLZI HRLZM HRLZS
; 1611 ;520 HLLO HLLOI HLLOM HLLOS HRLO HRLOI HRLOM HRLOS
; 1612 ;530 HLLE HLLEI HLLEM HLLES HRLE HRLEI HRLEM HRLES
; 1613 ;540 HRR HRRI HRRM HRRS HLR HLRI HLRM HLRS
; 1614 ;550 HRRZ HRRZI HRRZM HRRZS HLRZ HLRZI HLRZM HLRZS
; 1615 ;560 HRRO HRROI HRROM HRROS HLRO HLROI HLROM HLROS
; 1616 ;570 HRRE HRREI HRREM HRRES HLRE HLREI HLREM HLRES
; 1617 ; 0 1 2 3 4 5 6 7
; 1618 ;600 TRN TLN TRNE TLNE TRNA TLNA TRNN TLNN
; 1619 ;610 TDN TSN TDNE TSNE TDNA TSNA TDNN TSNN
; 1620 ;620 TRZ TLZ TRZE TLZE TRZA TLZA TRZN TLZN
; 1621 ;630 TDZ TSZ TDZE TSZE TDZA TSZA TDZN TSZN
; 1622 ;640 TRC TLC TRCE TLCE TRCA TLCA TRCN TLCN
; 1623 ;650 TDC TSC TDCE TSCE TDCA TSCA TDCN TSCN
; 1624 ;660 TRO TLO TROE TLOE TROA TLOA TRON TLON
; 1625 ;670 TDO TSO TDOE TSOE TDOA TSOA TDON TSON
; KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986 V2A(442) MICRO %37(277) Page 5
; DEFINE.MIC[4,24] 16:58 23-May-86 CONTROL RAM DEFINITIONS -- J, AD
; 1626 .TOC "CONTROL RAM DEFINITIONS -- J, AD"
; 1627 ;FIELDS ARRANGED FOR READABILITY, NOT COMPACTNESS
; 1628 ; IN THE PROCESSOR, BITS ARE SCATTERED IN ANOTHER ORDER
; 1629
; 1630 U0/=<0:0>D,0 ;BIT 0 UNUSED
; 1631 J/=<1:11>+ ;SYMBOLS WILL BE DEFINED BY TAGS (CRA1&CRA2)
; 1632
; 1633 ;MAIN ADDER CONTROLS. Bit 0 = carry in, bit 1 = boolean operation
; 1634 ; Bits 2-5 are S8-S1 of the 10181 ALU chip. For normal arithmetic,
; 1635 ; the AD and ADX are separated unless SPEC/AD LONG or equivalent is given.
; 1636
; 1637
; 1638 AD/=<12:17> ; (DP03, EXCEPT CARRY IN, ON CTL1)
; 1639 A+1=40,1
; 1640 A+XCRY=00,1
; 1641 ; A+ANDCB=01,1
; 1642 ; A+AND=02,1
; 1643 A*2=03,1
; 1644 A*2+1=43,1
; 1645 ; OR+1=44,1
; 1646 ; OR+ANDCB=05,1
; 1647 A+B=06,1
; 1648 A+B+1=46,1
; 1649 ; A+OR=07,1
; 1650 ORCB+1=50,1
; 1651 A-B-1=11,1
; 1652 A-B=51,1
; 1653 ; AND+ORCB=52,1
; 1654 ; A+ORCB=53,1
; 1655 XCRY-1=54,1
; 1656 ; ANDCB-1=15,1
; 1657 ; AND-1=16,1
; 1658 A-1=17,1
; 1659 ;ADDER LOGICAL FUNCTIONS
; 1660 SETCA=20
; 1661 ORC=21 ;NAND
; 1662 ORCA=22
; 1663 1S=23
; 1664 ANDC=24 ;NOR
; 1665 NOR=24
; 1666 SETCB=25
; 1667 EQV=26
; 1668 ORCB=27
; 1669 ANDCA=30
; 1670 XOR=31
; 1671 B=32
; 1672 OR=33
; 1673 0S=34
; 1674 ANDCB=35
; 1675 AND=36
; 1676 A=37
; 1677 ;BOOLEAN FUNCTIONS FOR WHICH CRY0 IS INTERESTING
; 1678 CRY A EQ -1=60,1 ;GENERATE CRY0 IF A=1S, AD=SETCA
; 1679 CRY A.B#0=36,1 ;CRY 0 IF A&B NON-ZERO, AD=AND
; 1680 CRY A#0=37,1 ;GENERATE CRY0 IF A .NE. 0, AD=A
; 1681 CRY A GE B=71,1 ;CRY0 IF A .GE. B, UNSIGNED; AD=XOR
; KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986 V2A(442) MICRO %37(277) Page 6
; DEFINE.MIC[4,24] 16:58 23-May-86 CONTROL RAM DEFINITIONS -- DATA PATH MIXERS
; 1682 .TOC "CONTROL RAM DEFINITIONS -- DATA PATH MIXERS"
; 1683
; 1684 ADA/=<18:20> ; (DP03)
; 1685 AR=0
; 1686 ARX=1
; 1687 MQ=2
; 1688 PC=3
; 1689 ADA EN/=<18:18> ;ADA ENABLE ALSO ENABLES ADXA (DP03)
; 1690 EN=0
; 1691 0S=1
; 1692 U21/=<21:21>D,0 ;BIT 21 UNUSED
; 1693 ADB/=<22:23> ;CONTROLS ADB AND ADXB (DP03)
; 1694 FM=0,,1 ;MUST HAVE TIME FOR PARITY CHECK
; 1695 BR*2=1 ;ADB35 is BRX0; ADXB35 is 0
; 1696 BR=2
; 1697 AR*4=3 ;ADB34,35 are ARX0,1; ADXB34,35 are 0
; 1698 U23/=<23:23>D,1 ;PREVENT DEFAULT SELECTION OF FM
; 1699 ;FORCE IT TO TAKE ONE OF THE SHORTER
; 1700 ;PATHS IF FM NOT NEEDED ALSO DISABLES
; 1701 ;PARITY CHECKING LOGIC
; 1702
; 1703 ;REGISTER INPUTS
; 1704
; 1705 AR/=<24:26>D,0 ; (DP01)
; 1706 AR=0
; 1707 ARMM=0 ;REQUIRES SPECIAL FUNCTION
; 1708 MEM=0 ;[346] MB WAIT will poke to 1 (CACHE) or 2 (AD)
; 1709 CACHE=1 ;ORDINARILY SELECTED BY HWARE
; 1710 AD=2
; 1711 EBUS=3
; 1712 SH=4
; 1713 AD*2=5 ;Low bit from ADX0
; 1714 ADX=6
; 1715 AD*.25=7
; 1716 ARX/=<27:29>D,0 ; (DP02)
; 1717 ARX=0 ;[345] BY DEFAULT
; 1718 MEM=0 ;[346] Gets poked by MB WAIT to 1 or 2
; 1719 CACHE=1 ;ORDINARILY BY MBOX RESP
; 1720 AD=2
; 1721 MQ=3
; 1722 SH=4
; 1723 ADX*2=5 ;Low bit from MQ0
; 1724 ADX=6
; 1725 ADX*.25=7 ;High bits from AD34,35
; 1726 BR/=<30:30>D,0 ;DEFAULT TO RECIRCULATE (DP04)
; 1727 AR=1
; 1728 BRX/=<31:31>D,0 ;DEFAULT TO RECIRCULATE (DP04)
; 1729 ARX=1
; 1730 MQ/=<32:32>D,0 ;DEFAULT TO RECIRCULATE (DP02)
; 1731 SH=1 ;LOAD FROM SHIFT MATRIX
; 1732 MQ*2=0 ;With SPEC/MQ SHIFT--Low bit from AD CRY -2
; 1733 MQ*.25=1 ;With SPEC/MQ SHIFT--High bits from ADX34, ADX35
; 1734 MQ SEL=0 ;WITH COND/REG CTL
; 1735 MQM SEL=1 ;WITH COND/REG CTL
; 1736
; KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986 V2A(442) MICRO %37(277) Page 7
; DEFINE.MIC[4,24] 16:58 23-May-86 CONTROL RAM DEFINITIONS -- DATA PATH MIXERS
; 1737 ;FMADR SELECTS THE SOURCE OF THE FAST MEMORY ADDRESS,
; 1738 ; RATHER THAN PROVIDING THE ADDRESS ITSELF
; 1739
; 1740 FMADR/=<33:35> ; (APR4&APR5)
; 1741 AC0=0 ;IR 9-12
; 1742 AC1=1 ;<IR 9-12>+1 MOD 16
; 1743 XR=2 ;ARX 14-17
; 1744 VMA=3 ;VMA 32-35
; 1745 AC2=4 ;<IR 9-12>+2 MOD 16
; 1746 AC3=5 ;<IR 9-12>+3 MOD 16
; 1747 AC+#=6 ;CURRENT BLOCK, AC+ MAGIC #
; 1748 #B#=7 ;BLOCK AND AC SELECTED BY # FIELD
; 1749
; 1750 .TOC "CONTROL RAM DEFINITIONS -- 10-BIT LOGIC"
; 1751
; 1752 SCAD/=<36:38> ; (SCD1)
; 1753 A=0
; 1754 A-B-1=1
; 1755 A+B=2
; 1756 A-1=3
; 1757 A+1=4
; 1758 A-B=5
; 1759 OR=6
; 1760 AND=7
; 1761 SCADA/=<39:41> ; (SCD1)
; 1762 FE=0
; 1763 AR0-5=1 ;BYTE POINTER P FIELD
; 1764 AR EXP=2 ;<AR 01-08> XOR <AR 00>
; 1765 #=3 ;SIGN EXTENDED WITH #00
; 1766 SCADA EN/=<39:39> ; (SCD1)
; 1767 0S=1
; 1768 U42/=<42:42>D,0 ;BIT 42 UNUSED
; 1769 SCADB/=<43:44> ; (SCD1)
; 1770 SC=0
; 1771 AR6-11=1 ;BYTE POINTER S FIELD
; 1772 AR0-8=2
; 1773 #=3 ;NO SIGN EXTENSION
; 1774 U45/=<45:45>D,0 ;BIT 45 UNUSED
; 1775 SC/=<46:46>D,0 ;RECIRCULATE BY DEFAULT (SCD2)
; 1776 FE=0 ;WITH SCM ALT
; 1777 SCAD=1
; 1778 AR SHIFT=1 ;WITH SCM ALT ;AR 18, 28-35
; 1779 FE/=<47:47>D,0 ;RECIRCULATE BY DEFAULT (SCD2)
; 1780 SCAD=1
; 1781 U48/=<48:48>D,0 ;BIT 48 UNUSED
; 1782
; KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986 V2A(442) MICRO %37(277) Page 8
; DEFINE.MIC[4,24] 16:58 23-May-86 CONTROL RAM DEFINITIONS -- SHIFT, ARMM, VMA, TIME
; 1783 .TOC "CONTROL RAM DEFINITIONS -- SHIFT, ARMM, VMA, TIME"
; 1784
; 1785 SH/=<49:50> ; (SH1)
; 1786 SHIFT AR!ARX=0 ;LEFT BY (SC)
; 1787 AR=1
; 1788 ARX=2
; 1789 AR SWAP=3 ;HALVES SWAPPED
; 1790 ARMM/=<49:50> ;SAME BITS AS SH CONTROL (SCD3)
; 1791 #=0 ;MAGIC # 0-8 TO AR 0-8
; 1792 EXP_SIGN=1 ;AR1-8 _ AR0
; 1793 SCAD EXP=2 ;AR0-8_SCAD
; 1794 SCAD POS=3 ;AR0-5_SCAD
; 1795 VMAX/=<49:50> ;SAME BITS AS SH CONTROL (VMA4)
; 1796 VMAX=0 ;VMA SECTION #
; 1797 PC SEC=1 ;PC SECTION #
; 1798 PREV SEC=2 ;PREVIOUS CONTEXT SECT
; 1799 AD12-17=3
; 1800 U51/=<51:51>D,0 ;BIT 51 UNUSED
; 1801 VMA/=<52:53>D,0 ;ALSO CONTROLLED BY SPECIAL FUNCTIONS
; 1802 VMA=0 ;BY DEFAULT
; 1803 PC=1 ;MAY BE OVERRIDDEN BY MCL LOGIC TO LOAD FROM AD
; 1804 LOAD=1 ; IF WE KNOW IT WILL BE OVERRIDDEN, USE THIS
; 1805 PC+1=2
; 1806 AD=3 ;ENTIRE VMA, INCLUDING SECTION
; 1807 TIME/=<54:55>T ;CONTROLS MINIMUM MICROINSTRUCTION EXECUTION
; 1808 ; TIME, COUNTING MBOX CLOCK TICKS (CLK)
; 1809 ;ASSEMBLER GENERALLY TAKES CARE OF THIS
; 1810 2T=0 ;2 TICKS
; 1811 3T=1 ;3 TICKS
; 1812 4T=2 ;4 TICKS
; 1813 5T=3 ;5 TICKS (COND/DIAG FUNC & #00, --> .5 USEC)
; 1814
; 1815 .TOC "CONTROL RAM DEFINITIONS -- MEM SPECIAL FUNCTIONS"
; 1816
; 1817 MEM/=<56:59>D,0 ;(MCL1, except MB WAIT on CON5 and CLK4)
; 1818 ;
; 1819 ; Note: MB WAIT is implicit whenever bit 58 is set.
; 1820 ;
; 1821 ; NOP=0 ;DEFAULT
; 1822 ARL IND=1 ;CONTROL AR LEFT MUX FROM # FIELD
; 1823 MB WAIT=2 ;WAIT FOR MBOX RESP IF PENDING
; 1824 RESTORE VMA=3 ;AD FUNC WITHOUT GENERATING A REQUEST
; 1825 A RD=4 ;OPERAND READ and load PXCT bits
; 1826 B WRITE=5 ;CONDITIONAL WRITE ON DRAM B 01
; 1827 FETCH=6 ;LOAD NEXT INSTR TO ARX (CONTROL BY #)
; 1828 REG FUNC=7 ;MBOX REGISTER FUNCTIONS
; 1829 AD FUNC=10 ;FUNCTION LOADED FROM AD LEFT
; 1830 EA CALC=11 ;FUNCTION DECODED FROM # FIELD
; 1831 LOAD AR=12
; 1832 LOAD ARX=13
; 1833 RW=14 ;READ, TEST WRITABILITY
; 1834 RPW=15 ;READ-PAUSE-WRITE
; 1835 WRITE=16 ;FROM AR TO MEMORY
; 1836 IFET=17 ;UNCONDITIONAL instruction FETCH
; 1837
; KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986 V2A(442) MICRO %37(277) Page 9
; DEFINE.MIC[4,24] 16:58 23-May-86 CONTROL RAM DEFINITIONS -- SKIP/COND SPECIAL FUNCTIONS
; 1838 .TOC "CONTROL RAM DEFINITIONS -- SKIP/COND SPECIAL FUNCTIONS"
; 1839
; 1840 SKIP/=<60:65>D,0 ;MICRO-PROGRAM SKIPS
; 1841 ; 40-57 DECODED ON (CRA2)
; 1842 ; SPARE=40
; 1843 EVEN PAR=41,,1 ;AR PARITY IS EVEN
; 1844 BR0=42 ;BR BIT 00
; 1845 ARX0=43 ;ARX BIT 00
; 1846 AR18=44 ;AR BIT 18
; 1847 AR0=45 ;AR BIT 00
; 1848 AC#0=46 ;IR9-12 .EQ. 0
; 1849 SC0=47 ;SC BIT 00
; 1850 PC SEC0=50
; 1851 SCAD0=51,,1 ;Sign of SCAD output--WRONG ON OVERFLOW FROM BIT 1!!!
; 1852 SCAD#0=52,,1 ;SCAD OUTPUT IS NON-ZERO
; 1853 ADX0=53,1 ;ADDER EXTENSION BIT 00
; 1854 AD CRY0=54,1 ;CARRY OUT OF AD BIT -2 (BOOLE IGNORED)
; 1855 AD0=55,1 ;ADDER BIT 00
; 1856 AD#0=56,1 ;AD BITS 00-35 CONTAIN SOME ONES
; 1857 -LOCAL AC ADDR=57 ;VMA18-31 =0 ON LOCAL REF IN SEC >1
; 1858
; 1859 ; 60-77 DECODED ON (CON2)
; 1860 FETCH=60 ;VMA FETCH (LAST CYCLE WAS A FETCH)
; 1861 KERNEL=61 ;PC IS IN KERNEL MODE
; 1862 USER=62 ;PC IS IN USER MODE
; 1863 PUBLIC=63 ;PC IS PUBLIC (INCLUDING SUPER)
; 1864 RPW REF=64 ;MIDDLE OF READ-PAUSE-WRITE CYCLE
; 1865 PI CYCLE=65 ;PI CYCLE IN PROGRESS
; 1866 -EBUS GRANT=66 ;PI HASN'T RELEASED BUS FOR CPU USE
; 1867 -EBUS XFER=67 ;NO TRANSFER RECIEVED FROM DEVICE
; 1868 INTRPT=70 ;AN INTERRUPT REQUEST WAITING FOR SERVICE
; 1869 -START=71 ;NO CONTINUE BUTTON
; 1870 RUN=72 ;PROCESSOR NOT HALTED
; 1871 IO LEGAL=73 ;KERNEL, PI CYCLE, USER IOT, OR DEVICE .GE. 740
; 1872 P!S XCT=74 ;PXCT OR SXCT
; 1873 -VMA SEC0=75 ;VMA SECTION NUMBER (13-17) IS NOT ZERO
; 1874 AC REF=76,,1 ;VMA .LT.20 ON READ OR WRITE
; 1875 -MTR REQ=77 ;INTERRUPT REQUEST NOT DUE TO METER
; 1876
; KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986 V2A(442) MICRO %37(277) Page 10
; DEFINE.MIC[4,24] 16:58 23-May-86 CONTROL RAM DEFINITIONS -- SKIP/COND SPECIAL FUNCTIONS
; 1877 ;SKIP/COND FIELD CONTINUED
; 1878
; 1879 COND/=<60:65>D,0 ;NON-SKIP SPECIAL FUNCTIONS
; 1880 ;0-7 DECODED ON (CTL2)
; 1881 ; NOP=0 ;BY DEFAULT
; 1882 LD AR0-8=1
; 1883 LD AR9-17=2 ;Gates VMAX into ARMM (see VMA4)
; 1884 LD AR18-35=3
; 1885 AR CLR=4
; 1886 ARX CLR=5
; 1887 ARL IND=6 ;CONTROL AR LEFT, CALL, AND CLEAR BITS FROM #
; 1888 REG CTL=7 ;CONTROL AR LOAD, EXP TST, AND MQ FROM #
; 1889 ; 10-37 DECODED ON (CON1)
; 1890 FM WRITE=10 ;WRITE AR INTO CURRENTLY ADDRESSED FM LOC
; 1891 PCF_#=11 ;SET PC FLAGS FROM # FIELD
; 1892 FE SHRT=12 ;SHIFT FE RIGHT 1
; 1893 AD FLAGS=13 ;SET PC CRY0, CRY1, OVRFLO, TRAP1 AS APPROPRIATE
; 1894 LOAD IR=14 ;LATCH AD OR CACHE DATA INTO IR, load PXCT bits
; 1895 SPEC INSTR=15 ;SET/CLR SXCT, PXCT, PICYC, TRAP INSTR FLAGS
; 1896 SR_#=16 ;CONTROL FOR STATE REGISTER and PXCT bits (CON3, MCL4)
; 1897 SEL VMA=17 ;READ VMA THROUGH ADA/PC
; 1898 DIAG FUNC=20 ;SELECT DIAGNOSTIC INFO ONTO EBUS
; 1899 EBOX STATE=21 ;SET STATE FLOPS
; 1900 EBUS CTL=22 ;I/O FUNCTIONS
; 1901 MBOX CTL=23
; 1902 ; SPARE=24
; 1903 LONG EN=25 ;THIS WORD CAN BE INTERPRETED AS LONG INDIRECT
; 1904 ; SPARE=26
; 1905 ; SPARE=27
; 1906 VMA_#=30
; 1907 VMA_#+TRAP=31
; 1908 VMA_#+MODE=32
; 1909 VMA_#+AR32-35=33
; 1910 VMA_#+PI*2=34
; 1911 VMA DEC=35 ;VMA_VMA-1
; 1912 VMA INC=36 ;VMA_VMA+1
; 1913 LD VMA HELD=37 ;HOLD VMA ON SIDE
; 1914
; 1915 CALL/=<66:66>D,0 ;CALL function--May not coexist with DISP/RETURN
; 1916 CALL=1 ;GOOD TO 15 LEVELS IN MODEL B
; 1917
; KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986 V2A(442) MICRO %37(277) Page 11
; DEFINE.MIC[4,24] 16:58 23-May-86 CONTROL RAM DEFINITIONS -- DISP/SPEC SPECIAL FUNCTIONS
; 1918 .TOC "CONTROL RAM DEFINITIONS -- DISP/SPEC SPECIAL FUNCTIONS"
; 1919
; 1920 DISP/=<67:71>D,10 ;0-7 AND 30-37 ARE DISPATCHES (CRA1&CRA2)
; 1921 DIAG=0
; 1922 DRAM J=1
; 1923 DRAM A RD=2 ;IMPLIES INH CRY18
; 1924 RETURN=3 ;POPJ return--may not coexist with CALL
; 1925 PG FAIL=4 ;PAGE FAIL TYPE DISP
; 1926 SR=5 ;16 WAYS ON STATE REGISTER
; 1927 NICOND=6 ;NEXT INSTRUCTION CONDITION (see NEXT for detail)
; 1928 SH0-3=7,,1 ;[337] 16 WAYS ON HIGH-ORDER BITS OF SHIFTER
; 1929 MUL=30 ;FE0*4 + MQ34*2 + MQ35; implies MQ SHIFT, AD LONG
; 1930 DIV=31,,1 ;FE0*4 + BR0*2 + AD CRY0; implies MQ SHIFT, AD LONG
; 1931 SIGNS=32,1 ;ARX0*8 + AR0*4 + BR0*2 + AD0
; 1932 DRAM B=33 ;8 WAYS ON DRAM B FIELD
; 1933 BYTE=34,,1 ;FPD*4 + AR12*2 + SCAD0--WRONG ON OVERFLOW FROM BIT 1!!
; 1934 NORM=35,2 ;See normalization for details. Implies AD LONG
; 1935 EA MOD=36 ;(ARX0 or -LONG EN)*8 + -(LONG EN and ARX1)*4 +
; 1936 ;ARX13*2 + (ARX2-5) or (ARX14-17) non zero; enable
; 1937 ;is (ARX0 or -LONG EN) for second case. If ARX18
; 1938 ;is 0, clear AR left; otherwise, poke ARL select
; 1939 ;to set bit 2 (usually gates AD left into ARL)
; 1940
; 1941 SPEC/=<67:71>D,10 ;NON-DISPATCH SPECIAL FUNCTIONS (CTL1)
; 1942 ; NOP=10 ;DEFAULT
; 1943 INH CRY18=11
; 1944 MQ SHIFT=12 ;ENABLE MQ*2, MQ SHRT2
; 1945 SCM ALT=13 ;ENABLE FE, ARSHIFT
; 1946 CLR FPD=14
; 1947 LOAD PC=15
; 1948 XCRY AR0=16 ;CARRY INTO AD IS XOR'D WITH AR00
; 1949 GEN CRY18=17
; 1950 STACK UPDATE=20 ;CONTROL CRY18 IF LOCAL STACK
; 1951 ; SUBR CALL=21 ;Obsolete--model A only
; 1952 ARL IND=22 ;# SPECIFIES ARL MIX, ENABLES, & CALL
; 1953 MTR CTL=23 ;# CONTROLS METERS
; 1954 FLAG CTL=24 ;FUNCTION ENCODED IN # FIELD
; 1955 SAVE FLAGS=25 ;TELLS PI CYCLE TO HOLD INTRPT
; 1956 SP MEM CYCLE=26 ;MEM REQUEST IS MODIFIED BY #
; 1957 AD LONG=27 ;AD BECOMES 72 BIT ALU
; 1958
; 1959 U73/=<72:73>D,0 ;BITS 72-73 UNUSED
; 1960
; 1961 MARK/=<74:74>D,0 ;FIELD SERVICE "MARK" BIT
; 1962
; KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986 V2A(442) MICRO %37(277) Page 12
; DEFINE.MIC[4,24] 16:58 23-May-86 CONTROL RAM DEFINITIONS -- MAGIC NUMBER FIELD
; 1963 .TOC "CONTROL RAM DEFINITIONS -- MAGIC NUMBER FIELD"
; 1964
; 1965 #/=<75:83>D,0 ;THE INFAMOUS "MAGIC NUMBERS"
; 1966
; 1967 MAJVER/=<75:80> ;[356] Major version number
; 1968 MINVER/=<81:83> ;[356] Minor version number
; 1969
; 1970 ;
; 1971 ; Options bits, designating different assemblies from the same sources
; 1972 ;
; 1973
; 1974 KLPAGE/=<75:75> ;KLPAGING
; 1975 OPTIONS=1
; 1976
; 1977 LONGPC/=<76:76> ;LONG PC FORMAT AS IN EXTENDED ADDRESSING
; 1978 OPTIONS=1 ;(The model A used a different format due
; 1979 ; to space limitations)
; 1980 NONSTD/=<77:77> ;NONSTANDARD (EG DIAGNOSTIC) MICROCODE
;;1981 .IF/NONSTD
;;1982 OPTIONS=1
; 1983 .IFNOT/NONSTD
; 1984 OPTIONS=0
; 1985 .ENDIF/NONSTD
; 1986
; 1987 PV/=<78:78> ;MODEL B - PV CPU
; 1988 OPTIONS=1
; 1989
; 1990 PMOVE/=<79:79> ;[435] Physical memory move instructions
; 1991 OPTIONS=1
; 1992
; 1993 ISTAT/=<83:83> ;STATISTICS GATHERING CODE (IE TRACKS)
;;1994 .IF/INSTR.STAT
;;1995 OPTIONS=1
; 1996 .IFNOT/INSTR.STAT
; 1997 OPTIONS=0
; 1998 .ENDIF/INSTR.STAT
; 1999
; 2000 PXCT/=<75:77> ;(MCL4) Loaded by CON/SR_#, CON/LOAD IR, and MEM/A RD
; 2001 ;Bit 0 enables the VMAX to not come from the AD when
; 2002 ; VMA/AD (allowing local AC refs, for example). Bits
; 2003 ; 1 and 2 select which PXCT bits a memory reference
; 2004 ; will select for possible previous context.
; 2005
; 2006 ACB/=<77:79> ;AC block number. Used with FMADR/#B#
; 2007 PAGB=6 ;AC block used for KL paging registers
; 2008 MICROB=7 ;AC block for general microcode scratch
; 2009
; 2010 AC#/=<80:83> ;AC number used with ACB or AC-OP (below)
; 2011
; 2012 ;
; 2013 ; Warning: when AC-OP is used with COND/FM WRITE, the previous micro-
; 2014 ; instruction must have the same # field as the current one. Otherwise
; 2015 ; the address lines won't make it in time for the write pulse. [210]
; 2016 ;
; 2017 AC-OP/=<75:79> ;CONTROLS AC #. AD functions < 40 all work
; 2018 AC+#=6
; KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986 V2A(442) MICRO %37(277) Page 12-1
; DEFINE.MIC[4,24] 16:58 23-May-86 CONTROL RAM DEFINITIONS -- MAGIC NUMBER FIELD
; 2019 #=32 ;JUST AC#
; 2020 OR=33 ;AC <OR> AC#
; 2021
; 2022 ;VARIOUS SPECIAL FUNCTIONS ENABLE SPECIAL DECODING OF THE
; 2023 ; "MAGIC #" FIELD, AS FOLLOWS:
; 2024
; 2025 ;SPECIAL DATA PATH CONTROLS
; 2026
; 2027 ;CALL/=<75:75> ;ENABLED BY ARL IND (CTL2)--Model A only
; 2028 ; CALL=1
; 2029 AR0-8/=<76:76> ;ENABLED BY ARL IND (CTL2)
; 2030 LOAD=1
; 2031 CLR/=<77:80> ;ENABLED BY ARL IND (CTL2)
; 2032 MQ=10
; 2033 ARX=4
; 2034 ARL=2
; 2035 ARR=1
; 2036 AR=3
; 2037 AR+ARX=7
; 2038 AR+MQ=13
; 2039 ARX+MQ=14
; 2040 AR+ARX+MQ=17
; 2041 ARL+ARX=6
; 2042 ARL+ARX+MQ=16
; 2043 ARR+MQ=11
; 2044 ARL/=<81:83> ;ENABLED BY ARL IND (CTL2)
; 2045 ARL=0
; 2046 ARMM=0 ;REQUIRES SPECIAL FUNCTION
; 2047 CACHE=1 ;ORDINARILY SELECTED BY HWARE
; 2048 AD=2
; 2049 EBUS=3
; 2050 SH=4
; 2051 AD*2=5
; 2052 ADX=6
; 2053 AD*.25=7
; 2054 AR CTL/=<75:77> ;ENABLED BY COND/REG CTL (CTL2)
; 2055 AR0-8 LOAD=4
; 2056 AR9-17 LOAD=2 ;Gates VMAX into ARMM (see VMA4)
; 2057 ARR LOAD=1
; 2058 ARL LOAD=6
; 2059 EXP TST/=<80:80> ;ENABLED BY COND/REG CTL (CTL1)
; 2060 AR_EXP=1
; 2061 MQ CTL/=<82:83> ;ENABLED BY COND/REG CTL (CTL2)
; 2062 ; MQ=0 ;WITH MQ/MQ SEL
; 2063 MQ*2=1 ;WITH MQ/MQ SEL--Low bit is ADX0
; 2064 ; MQ*.5=2 ; " (DROPS BITS 0,6,12,18,24,30)
; 2065 0S=3 ; "
; 2066 SH=0 ;WITH MQ/MQM SEL
; 2067 MQ*.25=1 ;WITH MQ/MQM SEL--High bits are ADX34, ADX35
; 2068 1S=2 ; "
; 2069 AD=3 ; "
; 2070
; KL10 Microcode--Copyright (C) Digital Equipment Corp., 29 May 1986 V2A(442) MICRO %37(277) Page 13
; DEFINE.MIC[4,24] 16:58 23-May-86 CONTROL RAM DEFINITIONS -- MAGIC NUMBER FIELD
; 2071 ;SPECIAL CONTROL OF EBOX FLAGS & FUNCTIONS
; 2072
; 2073 PC FLAGS/=<75:83> ;ENABLED BY COND/PCF_# (SCD4)
; 2074 ; OVERF=400 ;Any arithmetic overflow
; 2075 ; FLOVERF=200 ;Floating overflow
; 2076 FPD=100 ;SET FIRST PART DONE
; 2077 TRAP2=40 ;SET TRAP2 (PDL OVFLO)
; 2078 TRAP1=20 ;SET TRAP1 (ARITH OVFLO)
; 2079 ; EXPUND=10 ;Exponent underflow
; 2080 ; NO DIV=4 ;No divide
; 2081 AROV=420 ;SET ARITH OVFLO & TRAP1
; 2082 FLOV=620 ;SAME, PLUS FLOATING OVFLO
; 2083 FXU=630 ;FLOV + EXP UNDERFLOW
; 2084 DIV CHK=424 ;NO DIVIDE + AROV
; 2085 FDV CHK=624 ;FLOATING NO DIVIDE
; 2086 FLAG CTL/=<75:83> ;ENABLED BY SPEC/FLAG CTL (SCD5)
; 2087 RSTR FLAGS=420 ;AS IN JRSTF
; 2088 JFCL=602 ;FORCE PC 00 = AROV
; 2089 JFCL+LD=622 ;SECOND PART OF JFCL -- CLEAR TESTED FLAGS
; 2090 DISMISS=502 ;CLEAR PI CYCLE IF SET (CON5)
; 2091 ; ELSE DISMISS HIGHEST PI HOLD
; 2092 DISMISS+LD=522 ;LOAD FLAGS AND DISMISS
; 2093 HALT=442 ;STOP PROCESSOR IF LEGAL (CON2)
; 2094 SET FLAGS=20 ;AS IN MUUO
; 2095 PORTAL=412 ;CLEAR PUBLIC IF PRIVATE INSTR
; 2096 SPEC INSTR/=<75:83> ;ENABLED BY COND/SPEC INSTR
; 2097 SET PI CYCLE=714; (CON5)
; 2098 KERNEL CYCLE=200;MAKE IO LEGAL, EXEC ADDR SPACE (CON4)
; 2099 INH PC+1=100 ;TO MAKE JSR WORK IN TRAP, INTRPT (CON4)
; 2100 SXCT=40 ;START SECTION