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Trailing-Edge - PDP-10 Archives - BB-BL69D-SB_1986 - skpjmp.mic
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.TOC	"TEST GROUP"
	.DCODE
600:	I-PF,		J/NOP		;TRN--a noop
	I-PF,		J/NOP		;TLN <==> TRN
	I,	TNE,	J/TDXX		;TRNE
	I,	TNE,	J/TSXX		;TLNE
	I,	TNA,	J/TDX		;TRNA--unconditional skip
	I,	TNA,	J/TDX		;TLNA <==> TRNA
	I,	TNN,	J/TDXX		;TRNN
	I,	TNN,	J/TSXX		;TLNN

610:	R-PF,		J/NOP		;TDN--a noop that references memory
	R-PF,		J/NOP		;TSN <==> TDN
	R,	TNE,	J/TDXX		;TDNE
	R,	TNE,	J/TSXX		;TSNE
	R,	TNA,	J/TDX		;TDNA--skip with memory reference
	R,	TNA,	J/TDX		;TSNA <==> TDNA
	R,	TNN,	J/TDXX		;TDNN
	R,	TNN,	J/TSXX		;TSNN

620:	I-PF,	AC,	J/ANDCM		;TRZ <==> ANDCMI
	I-PF,	TZ-,	J/TLX		;TLZ [440]
	I,	TZE,	J/TDXX		;TRZE
	I,	TZE,	J/TSXX		;TLZE
	I,	TZA,	J/TDX		;TRZA
	I,	TZA,	J/TLXA		;TLZA
	I,	TZN,	J/TDXX		;TRZN
	I,	TZN,	J/TSXX		;TLZN

630:	R-PF,	AC,	J/ANDCM		;TDZ <==> ANDCM
	R-PF,	TZ-,	J/TLX		;TSZ [440]
	R,	TZE,	J/TDXX		;TDZE
	R,	TZE,	J/TSXX		;TSZE
	R,	TZA,	J/TDX		;TDZA
	R,	TZA,	J/TLXA		;TSZA
	R,	TZN,	J/TDXX		;TDZN
	R,	TZN,	J/TSXX		;TSZN

640:	I-PF,	AC,	J/XOR		;TRC <==> XORI
	I-PF,	TC-,	J/TLX		;TLC [440]
	I,	TCE,	J/TDXX		;TRCE
	I,	TCE,	J/TSXX		;TLCE
	I,	TCA,	J/TDX		;TRCA
	I,	TCA,	J/TLXA		;TLCA
	I,	TCN,	J/TDXX		;TRCN
	I,	TCN,	J/TSXX		;TLCN

650:	R-PF,	AC,	J/XOR		;TDC <==> XOR
	R-PF,	TC-,	J/TLX		;TSC [440]
	R,	TCE,	J/TDXX		;TDCE
	R,	TCE,	J/TSXX		;TSCE
	R,	TCA,	J/TDX		;TDCA
	R,	TCA,	J/TLXA		;TSCA
	R,	TCN,	J/TDXX		;TDCN
	R,	TCN,	J/TSXX		;TSCN
660:	I-PF,	AC,	J/IOR		;TRO <==> ORI
	I-PF,	TO-,	J/TLX		;TLO [440]
	I,	TOE,	J/TDXX		;TROE
	I,	TOE,	J/TSXX		;TLOE
	I,	TOA,	J/TDX		;TROA
	I,	TOA,	J/TLXA		;TLOA
	I,	TON,	J/TDXX		;TRON
	I,	TON,	J/TSXX		;TLON

670:	R-PF,	AC,	J/IOR		;TDO <==> OR
	R-PF,	TO-,	J/TLX		;TSO [440]
	R,	TOE,	J/TDXX		;TDOE
	R,	TOE,	J/TSXX		;TSOE
	R,	TOA,	J/TDX		;TDOA
	R,	TOA,	J/TLXA		;TSOA
	R,	TON,	J/TDXX		;TDON
	R,	TON,	J/TSXX		;TSON
	.UCODE

;MOST OF THESE 64 INSTRUCTIONS ARE DECODED BY MASK MODE (IMMEDIATE OR
; MEMORY) IN THE A FIELD, DISPATCH TO HERE ON THE J FIELD, AND RE-DISPATCH
; FOR THE MODIFICATION ON THE B FIELD.  A few of these are synonyms for
; other instructions, and use the synonym microcode for speed (see above).
; Those that never skip will always prefetch.
; ENTER WITH 0,E OR (E) IN AR, B FIELD BITS 1 AND 2 AS FOLLOWS:
; 0 0	NO MODIFICATION
; 0 1	ZEROS
; 1 0	COMPLEMENT
; 1 1	ONES
; THIS ORDER HAS NO SIGNIFICANCE EXCEPT THAT IT CORRESPONDS TO THE
; ORDER OF INSTRUCTIONS AT TGROUP.  THE HIGH ORDER BIT OF THE B FIELD
; (B0) IS XOR'D WITH AD CRY0 TO DETERMINE THE SENSE OF THE SKIP:
; 0	SKIP IF CRY0=1 (TXX- AND TXXN)
; 1	SKIP IF CRY0=0 (TXXA AND TXXE)

213:					;[412][440] Near TLXA/CAIM
TDX:	TEST FETCH,NO CRY,B DISP,J/TDN	;TDXA and TRXA
214:					;[412][440] Near TDX
TLXA:	AR_AR SWAP,TEST FETCH,NO CRY,	;TSXA and TLXA
	    B DISP,J/TDN
113:					;[440] Near ANDCM/XOR/IOR
TLX:	AR_AR SWAP,NO CRY,B DISP,J/TDN	;[440] TLX and TSX
=0****00***0				;[412]
TSXX:	AR_AR SWAP			;TSXE, TSXN, TLXE, AND TLXN
TDXX:	TEST AR.AC0,TEST FETCH,B DISP	;TDXE, TDXN, TRXE, AND TRXN
=
304:					;[412][441]
TDN:	J/FINI				;NO MODIFICATION
305:	AR_AR*AC0,AD/ANDCA,TIME/2T,J/STAC;[441] ZEROS
306:	AR_AR*AC0,AD/XOR,TIME/2T,J/STAC	;[441] COMP
307:	AR_AR*AC0,AD/OR,TIME/2T,J/STAC	;[441] ONES
.TOC	"COMPARE -- CAI, CAM"

	.DCODE
300:	I-PF,		J/NOP		;CAI <==> TRN
	I,	SJCL,	J/CAIM		;CAIL
	I,	SJCE,	J/CAIM		;CAIE
	I,	SJCLE,	J/CAIM		;CAILE
	I,	TNA,	J/TDX		;CAIA <==> TRNA
	I,	SJCGE,	J/CAIM		;CAIGE
	I,	SJCN,	J/CAIM		;CAIN
	I,	SJCG,	J/CAIM		;CAIG


310:	R-PF,		J/NOP		;CAM <==> TDN
	R,	SJCL,	J/CAIM		;CAML
	R,	SJCE,	J/CAIM		;CAME
	R,	SJCLE,	J/CAIM		;CAMLE
	R,	TNA,	J/TDX		;CAMA <==> TDNA
	R,	SJCGE,	J/CAIM		;CAMGE
	R,	SJCN,	J/CAIM		;CAMN
	R,	SJCG,	J/CAIM		;CAMG
	.UCODE

215:					;[440] Near NOP and TDX
CAIM:	GEN AR*AC0,COMP FETCH,J/NOP
.TOC	"ARITHMETIC SKIPS -- AOS, SOS, SKIP"
;ENTER WITH (E) IN AR

	.DCODE
330:	R,		J/MOVES		;SKIP--rather like MOVES [440]
	R,	SJCL,	J/SKIP		;SKIPL
	R,	SJCE,	J/SKIP		;SKIPE
	R,	SJCLE,	J/SKIP		;SKIPLE
	R,	SJCA,	J/SKIP		;SKIPA
	R,	SJCGE,	J/SKIP		;SKIPGE
	R,	SJCN,	J/SKIP		;SKIPN
	R,	SJCG,	J/SKIP		;SKIPG
	.UCODE

312:					;Must be near MOVES
SKIP:	FIN STORE,SKIP FETCH,
		SKP AC#0,J/STSELF	;STORE IN SELF MODE

	.DCODE
350:	RPW,		J/AONS		;AOS--never skip [440]
	RPW,	SJCL,	J/AOS		;AOSL
	RPW,	SJCE,	J/AOS		;AOSE
	RPW,	SJCLE,	J/AOS		;AOSLE
	RPW,	SJCA,	J/AOS		;AOSA
	RPW,	SJCGE,	J/AOS		;AOSGE
	RPW,	SJCN,	J/AOS		;AOSN
	RPW,	SJCG,	J/AOS		;AOSG
	.UCODE

=0****00***0
AONS:	AR_AR+1,AD FLAGS,STORE,J/SLFEND	;[440] AOS only
AOS:	AR_AR+1,AD FLAGS,STORE,J/SKIP	;Other AOSx
=

	.DCODE
370:	RPW,		J/SONS		;SOS--never skip [440]
	RPW,	SJCL,	J/SOS		;SOSL
	RPW,	SJCE,	J/SOS		;SOSE
	RPW,	SJCLE,	J/SOS		;SOSLE
	RPW,	SJCA,	J/SOS		;SOSA
	RPW,	SJCGE,	J/SOS		;SOSGE
	RPW,	SJCN,	J/SOS		;SOSN
	RPW,	SJCG,	J/SOS		;SOSG
	.UCODE

=0****00***0
SONS:	AR_AR-1,AD FLAGS,STORE,J/SLFEND	;[440] SOS only
SOS:	AR_AR-1,AD FLAGS,STORE,J/SKIP	;Other SOSx
=
.TOC	"CONDITIONAL JUMPS -- JUMP, AOJ, SOJ, AOBJ"

	.DCODE
320:	I-PF,		J/TDN		;JUMP <==> TRN (Do not jump!)
	I,	SJCL,	J/JUMP		;JUMPL
	I,	SJCE,	J/JUMP		;JUMPE
	I,	SJCLE,	J/JUMP		;JUMPLE
	I,		J/JUMPA		;JUMPA--always jump [441]
	I,	SJCGE,	J/JUMP		;JUMPGE
	I,	SJCN,	J/JUMP		;JUMPN
	I,	SJCG,	J/JUMP		;JUMPG
	.UCODE
302:					;[441]
JUMPA:	FETCH,J/NOP			;JUMPA only
303:					;Other JUMPx--near TDN
JUMP:	AR_AC0,JUMP FETCH,J/NOP		; E IS IN VMA (HERE AND BELOW)

	.DCODE
340:	I-PF,		J/AONJ		;AOJ--never jump [440]
	I,	SJCL,	J/AOJ		;AOJL
	I,	SJCE,	J/AOJ		;AOJE
	I,	SJCLE,	J/AOJ		;AOJLE
	I,		J/AOJA		;AOJA--always jump [440]
	I,	SJCGE,	J/AOJ		;AOJGE
	I,	SJCN,	J/AOJ		;AOJN
	I,	SJCG,	J/AOJ		;AOJG
	.UCODE
=0****00**00
AOJA:	FETCH				;[441] AOJA only
AONJ:	AR_AC0+1,AD FLAGS,J/STAC	;[440] AOJ only
AOJ:	AR_AC0+1,AD FLAGS,JUMP FETCH,J/STORAC;Other AOJx
=

	.DCODE
360:	I-PF,	AC,	J/SONJ		;SOJ--never jump [440]
	I,	SJCL,	J/SOJ		;SOJL
	I,	SJCE,	J/SOJ		;SOJE
	I,	SJCLE,	J/SOJ		;SOJLE
	I,	AC,	J/SOJA		;SOJA--always jump [440]
	I,	SJCGE,	J/SOJ		;SOJGE
	I,	SJCN,	J/SOJ		;SOJN
	I,	SJCG,	J/SOJ		;SOJG
	.UCODE
=0****00**00
SONJ:	AR_1S,J/ADD			;[440] SOJ only--add -1 to AC0
SOJA:	AR_1S,FETCH,J/ADD		;[440] SOJA only--add -1 and jump
SOJ:	AR_AC0				;Other SOJx
=	AR_AR-1,AD FLAGS,JUMP FETCH,J/STORAC

	.DCODE
252:	I,	SJCGE,	J/AOBJ		;AOBJP
	I,	SJCL,	J/AOBJ		;AOBJN
	.UCODE
=0****00****
AOBJ:	AR_AC0+1,GEN CRY18,JUMP FETCH,J/STORAC
=
.TOC	"AC DECODE JUMPS -- JRST"

	.DCODE
254:	EA,		J/JRST		;JRST--must be at JFCL-100
	.UCODE
;
;	A READ detects JRST, and dispatches to one of 16 loc'ns on AC bits.
;	These have been completely rewritten to save space.  [414]
;	Note that the instruction dispatch must have cleared SC
;	for XJRSTF to work.
;
600:					;Multiple of 200, at JFCL-100
JRST:	J/FINI				;(0) JRST--A READ has prefetched
601:	PORTAL,VMA_AR,FETCH,J/NOP	;(1) PORTAL
602:
JRSTF:	SKP PC SEC0,CALL [JRSTOK]	;(2) JRSTF--Must be in section 0
603:	J/UUO				;(3)
604:
HALT:	SKP KERNEL,CALL [JRSTOK]	;(4) HALT--Must be kernel mode
605:	LOAD AR,CALL [GETNXT]		;(5) XJRSTF. Fetch flags
606:	SC_1S,SKP IO LEGAL,J/HALT	;(6) XJEN. Set switch
607:	ARX_PC+1,SKP IO LEGAL,CALL [JRSTOK];(7) XPCW
610:	SKP IO LEGAL,CALL [JRSTOK]	;(10) JRST 10, dismiss only
611:	J/UUO				;(11)
612:	SKP IO LEGAL,CALL [JRSTOK]	;(12) JEN
613:	J/UUO				;(13)
614:	AR_0.C,ARX_PC+1,J/XSFM		;(14) XSFM
615:	LOAD AR,J/XJRST			;(15) XJRST
616:	J/UUO				;(16)
617:	J/UUO				;(17)
;
;	JRSTOK will either drop out to UUO or return 20.
;	GETNXT starts reading the next word and returns 40.
;
622:	BR/AR,EA MOD DISP,J/JRSNDX	;JRSTF.  Is it indexed?
;
624:	HALT,J/CHALT			;HALT. Stop and loop
;
645:	RSTR FLAGS_AR,ARX_AR SWAP,	;XJRSTF/XJEN. Restore flags, get
	    AR_MEM,SKP SC0,J/XJSPLT	; address, and dismiss if XJEN
;
627:	BRX/ARX,AR_ARX ANDC ADMSK,	;XPCW. Get flags
	    ARX/AD,J/XPCW
;
630:	DISMISS,VMA_AR,FETCH,J/NOP	;JRST 10. Just dismiss and jump
;
632:	DISMISS,J/JRSTF			;JEN. Dismiss, then restore flags
;
;	The more complex forms of JRST end up here.  Most of these were
;	substantially rewritten. [414]
;
=1110
JRSNDX:	AR_ARX,J/RFLAGS			;JRSTF/JEN, no index. Flags in mem
	AR_XR				;Indexed. Flags in AC
RFLAGS:	RSTR FLAGS_AR,AR_BR,J/ARJMP	;[436] Restore flags; avoid race
;
=0
XJSPLT:	SKP USER,J/LDPCS		;XJRSTF, no dismiss. Enter user?
	DISMISS,SKP USER		;XJEN. Dismiss interrupt. User mode?
=0
LDPCS:	GET ECL EBUS,J/PCSLOD		;No. Get EBUS and load PCS
ARJMP:	VMA_AR,FETCH,J/NOP		;Yes. We're done
;
PCSLOD:	LD PCS				;Do the load (from ARX)
	COND/EBUS CTL,EBUS CTL/2,J/ARJMP;Release ECL EBUS and go
;
=0
XPCW:	BR/AR,AR_0S,SKP USER,		;XPCW. Save flags and fetch previous
	    CALL [PRVSEC]		; section if not user mode
	ARL_BRL,ARR_ARR,STORE		;Store flags word
	FIN STORE,AR_ARX COMP AND BRX,	;Store PC word
	    VMA_VMA+1,STORE
=0*****	FIN STORE,VMA_VMA+1,LOAD AR,	;Fetch new flags
	    CALL [GETNXT]		; and PC
	RSTR FLAGS_AR,AR_MEM,J/ARJMP	;Restore flags, then jump
;
=0
XSFM:	ARX_ARX ANDC ADMSK,SKP USER,	;Isolate flags and previous
	    CALL [PRVSEC]		; section if not user mode
	ARL_ARXL,ARR_ARR,STORE,J/STMEM	;Store flags and exit
;
XJRST:	AR_MEM,SET ACCOUNT EN,J/ARJMP	;XJRST. Get jump address and go
;
;	JRSTOK--Subroutine to check whether a JRST X, is legal.  Enter
;	skipping legal.  This exits to UUO if not, and returns 20
;	otherwise.
;
=0
JRSTOK:	J/UUO				;No go
	RETURN20			;Looks OK
;
;	GETNXT--Subroutine to await a load and then start loading
;	the next word in sequence.  Return 40.
;
GETNXT:	FIN LOAD,VMA_VMA+1,LOAD AR,RETURN [40];Await, then load
;
;	PRVSEC--Subroutine to load the previous section and then
;	swap it into the right half of AR.  This is paired with
;	ARSWAP (below).  Return 1.
;
=0
PRVSEC:	AR12-17_PREV SEC		;Load PCS
;
;	[334] Subroutine to swap AR halves.  Used in a couple of places.
;
ARSWAP:	AR_AR SWAP,RETURN1		;[334] Rearrange things
.TOC	"HALT LOOP"
;HERE WHILE PROCESSOR IS "HALTED"

CHALT:	AR_0S,CLR SC,CLR FE,SET HALTED,	;KERNEL OR CONSOLE HALT
		VMA/PC,PC_VMA		; IF JRST 4, COPY EA TO PC
.IF/PAGCNT				;[327] PFH, DATAO PAG bit 2 counts
	TRX2_AR				;[327] Zero count registers
	TRX3_AR
.ENDIF/PAGCNT				;[327]
;
;	The halt loop must be an odd number of ticks to allow diagnostics
;	to synchronize EBOX with E and SBUS clock phases.
;
=0
HALT1:	SKP -START,TIME/3T,		;CHECK FOR CONTINUE BUTTON
		FE_AR0-8,ARX_AR,J/HALT2	;PICK UP OPCODE IN CASE XCT
	TAKE INTRPT			;HERE IF EXAMINE/DEPOSIT UP
=0
HALT2:	GEN FE-1,BYTE DISP,CONTINUE,J/UNHALT	;INSTR FROM SWITCHES?
	SKP INTRPT,TIME/2T,J/HALT1	;Still halted
=110
UNHALT:	SET CONS XCT,CLR FE,J/UXCT	;XCT ONE FROM "SWITCHES"
	SKP AR EQ,J/START		;NOT AN INSTR.  START, OR CONT?
.TOC	"AC DECODE JUMPS -- JFCL"

	.DCODE
255:	I,	TNN,	J/JFCL		;JFCL--must be at JRST+100
	.UCODE
;
;	JFCL--Often a slow noop.
;
700:					;JFCL MUST BE AT JRST+100
JFCL:	ARX_BRX,SC_#,#/13.,SKP AC EQ 0	;[440] Grab AC field. Is it 0?
=00	AR_SHIFT,ARX_0S,		;No. MOVE AC TO AR32-35
		SC_#,#/32.,CALL,J/SHIFT	;SHIFTER WILL MOVE TO 0-3
	I FETCH,J/NOP			;[440] Yes. Speed up noop
	BR/AR,AR_PC,JFCL T		;[440] GET PC FLAGS INTO AR
=	TEST AR.BR,JFCL FETCH		;JUMP IF TEST SATISFIED
	AR_AR*BR,AD/ANDCB		;CLEAR TESTED FLAGS IN AR
	JFCL S,J/FINI			;SET PC FROM THEM

.TOC	"MAP"

	.DCODE
257:	I,	AC,	J/MAP		;MAP--256 is XCT
	.UCODE

1311:					;Must be near XCT
MAP:	MAP,BR/AR			;MAP E, GO READ BACK EBRG
=	SR_MAP				;With KL PAGING, MAP CAN PAGE FAIL
=0
RDEBRG:	AR_0S,SKP IO LEGAL,MB WAIT,	;FINISH READ REG FUNC
		CALL,J/GETEEB		;AND GET EBUS
	AR_EBUS REG			;READ DATA
	REL ECL EBUS,B WRITE,J/ST6	;GIVE IT TO USER
;
;	MAP never generates a hard page fail.  If the MAP microorder
;	faults, CLEAN returns here with
;
;	AR_SV.PFW,SKP IO LEGAL		;Return PFW in AC
=0
MAP2:	SR_0,J/UUO			;NO MAPS IN USER MODE
	SKP INTRPT			;DO NOT BUM THIS CODE OUT
=0	I FETCH,J/STORAC		;MAP must do nothing interesting if
	SET ACCOUNT EN,J/TAKINT		; an interrupt is pending
.TOC	"STACK INSTRUCTIONS -- PUSHJ, PUSH, POP, POPJ"

	.DCODE
260:	EA,		J/PUSHJ		;PUSHJ
	R,	B/0,	J/PUSH		;PUSH
	EA,	B/0,	J/POP		;POP
	I,		J/POPJ		;POPJ
	.UCODE

;PUSHJ
; ENTER WITH E IN AR
;PUSH
; ENTER WITH (E) IN AR

=0****00***0
PUSH:	ARX_AC0+1,PUSH,SKP CRY0,J/STMAC	;BUMP AC ACCORDING TO FORMAT
					; AND SECTION NUMBER
PUSHJ:	BR/AR,AR_PC+1,SKP PC SEC0	;GET PC WITH FLAGS
=
=0	AR_AR AND ADMSK			;STRIP OFF FLAGS IF NOT SEC0
	ARX_AC0+1,PUSH,SKP CRY0,J/JSTAC	;UPDATE STACK POINTER, STORE
=00
JRA1:	VMA_AR,LOAD ARX,CALL,J/XFERW	;GET SAVED AC
=10
JSTAC:	FIN STORE,VMA_BR,FETCH,		;STORE PC, JUMP ADDR TO VMA
		AR_ARX,J/STORAC		;PREPARE TO STORE AC VALUE
	TRAP2,MEM_AR,J/JSTAC		;CAUSE PDL OVRFLO

=0
STMAC:	FIN STORE,I FETCH,		;STORE RESULT, GET NEXT INSTR
		AR_ARX,B DISP,J/STSELF	;STORE AC IF B=0
	MEM_AR,TRAP2,			;PDL OVFLO, CAUSE TRAP
		AR_ARX,J/IFSTAC		;UPDATE AC BEFORE TRAPPING
;POP, POPJ
;ENTER WITH E IN AR

=0****00***0
POP:	BR/AR,AR_AC0,POP AR,J/POP2	;GET FROM STACK

POPJ:	AR_AC0,POP AR-ARX		;GET STACK TO AR AND ARX
=	AR_AR-1,TIME/3T,AC0,		;BACK OFF POINTER
	    STACK UPDATE,SKP CRY0	; UNDERFLOW?
=0	MQ_AR,AR_MEM,ARX_MEM,TIME/3T,	;[413] Yes. AC to MQ, PC to AR and
	    TRAP2,J/POPJT		;[414] ARX, set trap
	MQ_AR,AR_MEM,ARL_0.S,ARX_MEM,	;[413] AC TO BR, HALFWORD PC TO AR
	    TIME/3T,SKP PC SEC0		;FULL PC TO ARX. Extended form?
=0
POPJ2:	VMA_ARX,FETCH,ARX/MQ,		;[413] YES.  LOAD ENTIRE ADDR
	    SC_#,#/36.,J/SHFLOD
	VMA_AR,FETCH,ARX/MQ,SC_#,#/36.,	;[413] NO, LOAD HALFWORD ADDRESS
	    J/SHFLOD
;
;	POPJ gets stack underflow.  Unfortunately, we can't clear ARL and
;	set TRAP2 at the same time (to say nothing of testing PC SEC0).
;
POPJT:	ARL_0.S,ARR_ARR,		;[414] Halfword PC to AR. Test for
	    SKP PC SEC0,J/POPJ2		; extended form
;
=0*
POP2:	ARX_AR-1,AC0,STACK UPDATE,	;BACK UP POINTER
		SKP CRY0,CALL [POPTRP]	; and test for trap [413]
	GEN BR,WRITE (E),J/STMAC	;STORE RESULT & AC
;
;	Subroutine to test for POP trap and wait for memory.  Return 2.
;
=0
POPTRP:	AR_MEM,TRAP2,RETURN [2]		;POP stack underflowed.
;
;	A one line subroutine to wait for a memory fetch (either AR
;	or ARX) and return.  Used by all sorts of things.  Must adjoin
;	POPTRP.
;
XFERW:	AR_MEM,ARX_MEM,TIME/3T,RETURN2	;Cross reference both macros [313]
.TOC	"SUBROUTINE CALL/RETURN -- JSR, JSP, JSA, JRA"

	.DCODE
264:	EA,		J/JSR		;JSR
	EA,		J/JSP		;JSP
	I,		J/JSA		;JSA
	I,		J/JRA		;JRA
	.UCODE

=0****00***0
JSP:	AR_PC+1,FETCH,SKP PC SEC0,J/JSP1

JSR:	AR_PC+1,SKP PC SEC0
=
=0	AR_AR AND ADMSK,STORE,J/JSR1
	STORE				;IN SECT 0, SAVE FLAGS, TOO
JSR1:	FIN STORE,VMA_VMA+1,FETCH,J/NOP

=0
JSP1:	AR_AR AND ADMSK,J/STAC		;NON-ZERO SEC, NO FLAGS
	AC0_AR,J/FINI


=0****00***0
JSA:	ARX_AR SWAP,AR_AC0,STORE,J/JSA1	;SAVE E IN ARX LEFT, GET AC

JRA:	AR12-17_PC SEC			;[235] put section in jump address.
=	BR/AR,AR_AC0			;[235][414] Grab AC, keep jump addr
	ARR_ARL,ARL_BRL,J/JRA1		;[235][414] Generate memory address

JSA1:	FIN STORE,VMA_VMA+1,FETCH	;JUMP TO E+1
	ARR_PC+1,ARL_ARXL,J/STAC	;PC+1,,E GOES TO AC
.TOC	"UUO'S"
;LUUO'S TRAP TO CURRENT CONTEXT
; EXTENDED INSTRUCTION SET IS "HIDDEN" BENEATH LUUO OPCODES
;	The general format is
;
;	EA,	Bfield,	J/EXTEND op code - 1000
;
;	so that a jump to LUUO can be put as the direct DRAM object
;	and the EXTEND dispatch can ship it off to the appropriate
;	extended op code processor.  All of the legal EXTEND op codes
;	are assembled adjacent to their handlers.
;
;	WARNING:  use extreme caution if E1 for MOVSRJ or CMPSE should
;	ever be used for anything, as they are sign smeared if they are
;	> 377777 (they fall in with MOVSO and friends at EXT2). [301]
;	Use similar caution if new EXTEND codes are created which
;	must have the DCODE B field be 1 or 3.
;
	.DCODE
000:	EA,		J/UUO
.IF/EXTEXP
020:	EA,	J/BLUUO			;XBLT LUUO must adjoin GSNGL
.IFNOT/GFTCNV
023:	EA,	J/BLUUO			;G floating converts
	EA,	J/BLUUO			;decommited due to
	EA,	J/BLUUO			;lack of space
	EA,	J/BLUUO
.ENDIF/GFTCNV
.IFNOT/EXTEXP
020:	EA,	J/LUUO			;XBLT no longer dispatched
	EA,	J/LUUO
	EA,	J/LUUO
	EA,	J/LUUO
024:	EA,	J/LUUO
	EA,	J/LUUO
	EA,	J/LUUO
	EA,	J/LUUO
030:	EA,	J/LUUO
	EA,	J/LUUO
.ENDIF/EXTEXP
032:	EA,	J/LUUO			;These are reserved to Cobol.
	EA,	J/LUUO
	EA,	J/LUUO
	EA,	J/LUUO
	EA,	J/LUUO
	EA,	J/LUUO
;MONITOR UUO'S -- TRAP TO EXEC

040:	EA,	J/MUUO		;CALL
	EA,	J/MUUO		;INIT
	EA,	J/MUUO
	EA,	J/MUUO
	EA,	J/MUUO
	EA,	J/MUUO
	EA,	J/MUUO
	EA,	J/MUUO		;CALLI
	EA,	J/MUUO		;OPEN
	EA,	J/MUUO		;TTCALL
;
;	052 and 053 are now PMOVE and PMOVEM.
;
054:	EA,	J/MUUO
	EA,	J/MUUO		;RENAME
	EA,	J/MUUO		;IN
	EA,	J/MUUO		;OUT
	EA,	J/MUUO		;SETSTS
	EA,	J/MUUO		;STATO
	EA,	J/MUUO		;GETSTS
	EA,	J/MUUO		;STATZ
	EA,	J/MUUO		;INBUF
	EA,	J/MUUO		;OUTBUF
	EA,	J/MUUO		;INPUT
	EA,	J/MUUO		;OUTPUT
	EA,	J/MUUO		;CLOSE
	EA,	J/MUUO		;RELEAS
	EA,	J/MUUO		;MTAPE
	EA,	J/MUUO		;UGETF
	EA,	J/MUUO		;USETI
	EA,	J/MUUO		;USETO
	EA,	J/MUUO		;LOOKUP
	EA,	J/MUUO		;ENTER

;EXPANSION OPCODES

100:	EA,	J/UUO		;UJEN
	EA,	J/UUO
247:	EA,	J/UUO		;[430] Adjoins LSHC

.IFNOT/EXTEXP
102:	EA,	J/UUO
	EA,	J/UUO
106:	EA,	J/UUO
	EA,	J/UUO
.ENDIF/EXTEXP
	.UCODE
;HERE FOR UNDEFINED OPS (UUO'S) AND ILLEGAL INSTRUCTIONS
;E IS IN AR, OPCODE AND AC IN BRX

;HERE ON LUUO'S
; E IN AR, INSTR IN BRX
;
;	All LUUOs which have corresponding EXTEND op codes must dispatch
;	to their own first word.  In all cases, it is the same as LUUO.
;
.IF/EXTEXP				;[337]
1116:
.IF/GFTCNV				;[427]
BLUUO:					;[427] Define this for XBLT
.ENDIF/GFTCNV				;[427]
L-GTPI:	ARX_BRX,SKP PC SEC0,J/LUUO1	;GSNGL
1114:
L-SFTE:	ARX_BRX,SKP PC SEC0,J/LUUO1	;GDBLE
.IF/GFTCNV
1117:
L-GTDI:	ARX_BRX,SKP PC SEC0,J/LUUO1	;GDFIX
1106:
L-GTSI:	ARX_BRX,SKP PC SEC0,J/LUUO1	;GFIX
1107:
L-GTDR:	ARX_BRX,SKP PC SEC0,J/LUUO1	;GDFIXR
1110:
L-GTSR:	ARX_BRX,SKP PC SEC0,J/LUUO1	;GFIXR
.IFNOT/GFTCNV
1110:
BLUUO:	ARX_BRX,SKP PC SEC0,J/LUUO1	;Conditioned out EXTEND ops
3110:	J/MUUO				;Force EXTEND to UUO
.ENDIF/GFTCNV
1111:
L-DITE:	ARX_BRX,SKP PC SEC0,J/LUUO1	;DGFLTR
1112:
L-SITE:	ARX_BRX,SKP PC SEC0,J/LUUO1	;DGLTR
1113:
L-EFSC:	ARX_BRX,SKP PC SEC0,J/LUUO1	;GFSC
.IFNOT/EXTEXP
1110:
BLUUO:	ARX_BRX,SKP PC SEC0,J/LUUO1	;Conditioned out EXTEND ops
3110:	J/MUUO				;Force EXTEND to UUO
.ENDIF/EXTEXP
1006:
L-EDIT:	ARX_BRX,SKP PC SEC0,J/LUUO1	;EDIT
1010:
L-DBIN:	ARX_BRX,SKP PC SEC0,J/LUUO1	;DBIN AT 2010
1011:
L-BDEC:	ARX_BRX,SKP PC SEC0,J/LUUO1	;BDEC AT 2011
1012:
L-MVS:	ARX_BRX,SKP PC SEC0,J/LUUO1	;MOVE STRING AT 2012
1005:
L-CMS:					;STRING COMPARE
LUUO:	ARX_BRX,SKP PC SEC0		;WHICH KIND OF UUO?
=0***0
LUUO1:	CLR P,SKP -LOCAL AC ADDR,	;[414] Extended. Generate clean  
	    CALL [UUOCOM]		; section number
	BR/AR,AR_ARX ANDC ADMSK,	;COMPATiBLE.  ADDR TO BR
		SKP INTRPT,J/LUUO2	; DO IT THE OLD WAY
	VMA_#,#/420			;PT LOC FOR LUUO BLOCK POINTER
=
=00	LOAD ARX,PT REF,CALL,J/XFERW	;GET LUUO BLOCK ADDRESS
=10	VMA_ARX,STORE,CALL,J/UUOC2	;STORE UUO OPCODE AND FLAGS
	FIN STORE,VMA_VMA+1,LOAD AR,	;NOW GET A NEW PC
		J/XJRST			; [414]

;HERE FOR COMPATIBLE UUO
=0
LUUO2:	AR_AR*BR,AD/OR,VMA_#,#/40,	;SAVE OPCODE AND EA
		STORE,J/LUUO3		;THEN GET INSTR FROM 41
	TAKE INTRPT			;ONE MOMENT, PLEASE
LUUO3:	FIN STORE,VMA_VMA+1,LOAD ARX,
	    J/XCTW
;HERE ON MUUO'S
; E IN AR, OP AND AC IN BRX

1002:					;Fixed for EXTEND, other ops
UUO:					;A PEDANTIC DISTINCTION...
MUUO:	ARX_BRX,CLR P,SKP -LOCAL AC ADDR,;[414] Get clean section number
	    CALL [UUOCOM]		; and pull together pieces of UUO
1022:	LOAD ARX,UPT REF		;GET NEW PC
	ARX_MEM,VMA_#,#/424		;LOC'N OF MUUO DATA BLOCK
=0	BRX/ARX,STORE,UPT REF,		;STORE OPCODE, FLAGS
		CALL,J/UUOC2		;NOW RETURN TO COMMON CODE
	MEM_AR,AR_PC,SC_#,#/4		;READY TO SETUP NEW FLAGS
=00	VMA_VMA+1,SC_#,#/60,		;SET UP FOR CONTEXT WORD
		SH DISP,AR_0S,		;TEST USER AND PUBLIC FLAGS
		CALL,J/MUUOF		;SET NEW PREV FLAGS, GET EBUS
	DATAI PAG(L),ARX_1B17-1,	;GO COLLECT DATAI PAG INFO
		CALL,J/PCTXT
=11	LD PREV CTXT			;PCS FROM PC, CWSX FROM SXCT
	AR_SHIFT,ARL_BRL.S,		;COMBINE UBR WITH AC BLKS, CWSX
		STORE,			; STORE THAT AT 426 (XADDR =427)
		COND/EBUS CTL,EBUS CTL/2; & RELEASE ECL EBUS
	MEM_AR,AR_BRX,SR_0		;NOW GET NEW PC
SETPC:	VMA_AR AND ADMSK,FETCH,J/NOP

=0					;[414]
UUOCOM:	ARL_1.M				;FORCE AC ADDRESS
	MQ_AR,AR_ARX ANDC ADMSK		;SAVE ADDR IN MQ.  GET OPCODE
	BR/AR,AR_0.S,SKP USER		;SAVE OPCODE IN BR
=0	AR12-17_PREV SEC		;GET PCS
	AR_AR*BR,AD/OR,VMA_430+MODE	;[414] OPCODE+PCS, UUO new PC loc
	ARX_AR SWAP,AR_PC FLAGS		;GET FLAGS FROM PC
	ARL_ARL,ARR_ARX,RETURN20	;[414] FLAGS AND OPCODE COMBINED

UUOC2:	MEM_AR,ARX_PC+1			;FINISH STORE
	AR_ARX AND ADMSK,		;PC+1 ADDRESS TO AR
		VMA_VMA+1,STORE,ARX/MQ	;PUT PC AWAY, GET EFFECTIVE ADDR
	FIN STORE,AR_ARX,
		VMA_VMA+1,STORE,RETURN1	;PUT EA AWAY.

=1010					;HERE TO SETUP NEW FLAGS
MUUOF:	SET FLAGS_AR,J/GTEEB1		;GO GET ECL EBUS
	AR0-8_#,#/400,J/MUUOF		;PREV CTXT SUPERVISOR
	AR0-8_#,#/004,J/MUUOF		;  USER/CONCEALED
	AR0-8_#,#/404,J/MUUOF		;  USER/PUBLIC
.TOC	"JSYS, ADJSP, XCT, PXCT"

	.DCODE
104:	EA,		J/UUO		;JSYS
	I,		J/ADJSP		;ADJSP [431]
	.UCODE

;
;	ADJSP has been completely rewritten to start the I FETCH
;	quicker in all cases.  [431]
;
1000:					;Must adjoin JSYS (UUO)
ADJSP:	ARL_ARR,ARR_ARR,ARX_1,TIME/2T	;Gen adjustment for short stack
	AC0,STACK UPDATE,GEN ARX-1,	;Short stack enables CRY18; thus
	    SKP CRY0,I FETCH		; skip on long pointer
=0	AR_AR+FM[AC0],INH CRY18,	;Short pointer. Adjust both halves
	    SKP AR0,J/ADJPDL		; and set for proper overflow test
	ARL_SIGN,ARR_ARR		;Long pointer. Sign extend E
	AR_AR+FM[AC0],J/STAC		;Adjust and store
;
=0
ADJPDL:	GEN AR*AC0,AD/ANDCA,SKP AD0,	;Positive adjustment. Test for
	    J/ADJTRP			; - to + change
	GEN AR*AC0,AD/ANDCB,SKP AD0	;Negative. Look for + to - change
=0
ADJTRP:	AC0_AR,NXT INSTR		;No overflow. All done
	FETCH WAIT,TRAP2,J/STAC		;Overflow. Set trap; don't lose PF

	.DCODE
256:	R,		J/XCT		;XCT--257 is MAP
	.UCODE

1310:					;Must be near MAP
XCT:	SKP INTRPT			;CHECK FOR XCT . LOOP
=0	SKP USER,J/PXCT			;HERE ON XCT, NO INTERRUPT
	TAKE INTRPT			;GET OUT OF LONG XCT CHAIN
=0
PXCT:	SET PXCT			;SETUP PXCT CONTROLS FROM 9-12
UXCT:	ARX_AR (AD),LOAD IR,#/0,J/XCTGO	;COPY INSTR TO ARX, IR