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Trailing-Edge - PDP-10 Archives - BB-J724A-SM_1980 - sources/s.p11
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.SBTTL	S - VARIOUS SYMBOL AND MACRO DEFINITIONS

.REPT 0


                          COPYRIGHT (c) 1980, 1979
            DIGITAL EQUIPMENT CORPORATION, maynard, mass.

THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND  COPIED
ONLY  IN  ACCORDANCE  WITH  THE  TERMS  OF  SUCH  LICENSE AND WITH THE
INCLUSION OF THE ABOVE COPYRIGHT NOTICE.  THIS SOFTWARE OR  ANY  OTHER
COPIES  THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY
OTHER PERSON.  NO TITLE TO AND OWNERSHIP OF  THE  SOFTWARE  IS  HEREBY
TRANSFERRED.

THE INFORMATION IN THIS SOFTWARE IS SUBJECT TO CHANGE  WITHOUT  NOTICE
AND  SHOULD  NOT  BE  CONSTRUED  AS  A COMMITMENT BY DIGITAL EQUIPMENT
CORPORATION.

DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE OR  RELIABILITY  OF  ITS
SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL.

.ENDR
;
; VERSION 2(42): FEBRUARY 01, 1978  --  DMCC/EGF/JBS/KR/MM

;Revision history

; 1(27)		17-Aug-76	received from John Sauter
; 1(30)		05-Oct-76	added DZ11 symbols
; 1(31)		04-NOV-76	ADDED DTE20 SYMBOLS
; 1(32)		21-JAN-77	FIXED DTE20 SYMBOLS AND ADDED
;				 DUP11 SYMBOLS.
; 1(33)		14-FEB-77	UPDATED COPYRIGHT NOTICE
; 1(34)		17-FEB-77	CORRECTED SOME ERRORS IN DTE20
;				 SYMBOLS AND REMOVED SWITCH REG
; 1(35)		09-MAR-77	ADDED MORE DTE20 BITS
;
; 1(36)		18-MAR-77	REMOVED KGLOAD MACRO
;
; 1(37)		01-APR-77	CHANGED NAME TO "DN60".
;
; 1A(40)	27-JUN-77	ADDED KMC11, REMOVED PA611
;
; 2(41)		13-SEP-77	CORRECTED PRIORITY LEVEL FOR
;				 KW11-L AND REMOVED P=SP.
;
; 2(42)		01-FEB-78	ADDED HASP-MULTILEAVING STOPCODES
;
;
;
;	REVISION HISTORY CONTINUED
;
;
; 3(001) BS	ADDED VERSION NUMBER
;
;
VS=001
;
;
VEDIT=VEDIT+VS
;
;
;
;

	.ENABL	LC		;LOWER CASE IS LOWER CASE
	.ENABL	ABS,AMA		;ABSOLUTE PROGRAM, ABS ADDRESSES
;	.DSABL	GBL		;DISABLE GLOBAL REFERENCES
;	.LIST	MC,MD,ME	;
;	.NLIST	CND		;
	.LIST	MEB		;LIST ONLY CODE PRODUCING PARTS OF MACROS
.IIF NDF FT.HLP,FT.HLP=	1	;1 = TYPE OUT STOPCD INFORMATION
.IIF NDF DEBUG,DEBUG=1		;LEVEL OF DEBUG CODE INCLUDED
				; 0 = NONE = KEEP AS SMALL AS POSSIBLE
				; 1 = SOME - KEEP TRACKS, DIE ON SOME ERRORS
				; -1 = DIE ON ALL ERRORS
.IIF NDF FT.CHK,FT.CHK=	1	;1 EQUALS CHECK STUFF ON FLY

.IIF NDF PASS,PASS=0	;COUNT ASSEMBLER PASSES
	PASS=PASS+1
.SBTTL	STOPCD'S

; THESE STOP CODES ARE FOR ALL DEC SYSTEMS USING THIS PREFIX FILE.

; PART 1--STOP CODES COMMON TO DN60, DAS76, DAS80, DAS81,
;  DAS82, DAS85 AND DAS87.

S..NXM=	1	;BUS TRAPS'S, ADDRESS ERROR'S, ETC.
S..DL10=2	;DL10 ERRORS
S..CNK=	3	;CHUNKS ARE MESSED UP
S..ILS=	4	;ILLEGAL INSTRUCTION
S..CTY=	5	;NO CTY
S..MEM=	6	;MEMORY ERROR (E.G. PARITY, OR CAN'T READ WRITE BITS)
S..KW11=7	;KW11-L ERROR
S..CHK=10	;CHK11-DETECTED ERROR
S..NCI=11	;NOT ENOUGH CORE FOR INITIALIZATION
S..WDG=12	;CLOCK STOPPED TICKING
S..LOP=13	;LOOP IN LOW-PRIORITY CODE
S..DBG=14	;DEBUGGING STOP

; STOP CODES 15 TO 23 ARE RESERVED FOR CODES COMMON TO 
;   ALL PRODUCTS.

; PART 2 -- STOP CODES FOR DAS80, DAS81, DAS82, DAS85 AND DAS87

S..NCN=24	;NO CONNECTION FOR RECEIVED DATA
		; OR CONNECTION NUMBER USED BY SOME OTHER NODE
S..BDT=25	;BAD DATA TYPE REQUESTED BY 10

; STOP CODES 26 TO 37 ARE RESERVED FOR DAS80, DAS81, DAS82
;   DAS85 AND DAS87.
;
; PART 3 -- STOP CODES FOR DN60 SERIES

S..BAF=40	;BAD ADDRESS IN SUBROUTINE "FRECHK"
;S..QIE=41	;DQ11 SUBROUTINE CALLED WITH INTERRUPTS ENABLED
S..UQR=42	;UNKNOWN (DISABLED) DQ11 RECEIVER INTERRUPT
S..UQX=43	;UNKNOWN (DISABLED) DQ11 TRANSMITTER INTERRUPT
S..QRN=44	;DQ11 SUBROUTINE CALLED WITH DQ11 ALREADY RUNNING
S..NDQ=45	;NO DQ11S ON DN60
S..QER=46	;DQ11 ERROR
S..QXC=47	;DQ11 TRANSMITTER CHUNK CONFUSION
S..QRC=50	;DQ11 RECEIVER CHUNK CONFUSION
S..BCE=51	;BCC ACCUMULATION ERROR
S..XMB=52	;TRANSLATOR MESSAGE BUILDING ERROR
;S..QUE=53	;QUEUEING ERROR
S..TER=54	;"TEN ERROR" -- ERROR IN '10 PROTOCOL
S..HTS=55	;ERROR IN HORIZONTAL TABULATION SETTING MESSAGE
;
; THE FOLLOWING STOPCODES ARE USED BY THE DTE DRIVER AND THE QUEUED
;  PROTOCOL INTERFACE IN THE IMPLEMENTATION OF DN61-S(WITH DTE20).
;
.IF DF,FT2020 ;IF ON A 2020
S..DMA= 56	;DMC INITIALIZATION ERROR
S..DMC= 57	;DMC ERROR
S..DTB= 60
.ENDC ;END IF DF,FT2020
.IF NDF,FT2020 ;IF NOT ON A 2020
S..DTA= 56	;INITIALIZATION ERROR
S..DTB= 57	;TO TEN DONE ERROR
S..DTC= 60	;TO ELEVEN DONE ERROR
S..DTD= 61	;DOORBELL ERROR
S..DTE= 62	;E-BUS PARITY ERROR
S..DTF= 63	;QPR COUNT ERROR
S..DTG= 64	;PROTOCOL BROKEN
S..DTH= 65	;PROTOCOL BROKEN
S..DTI= 66	;PROTOCOL BROKEN
.ENDC ;END IF NDF,FT2020
S..DTM=120	;TCB MISSING FROM QUE
;
; THE FOLLOWING STOPCODES ARE USED BY THE KMC11 INTERFACE
;
S..KCQ=67	;KMC11 COMPLETE ON AN IDLE LCB
S..KNA=70	;KMC11 NOT FOLLOWING ACTIVE FLAG
S..KNR=71	;KMC11 NOT RUNNING
S..KKS=72	;KMC11 KEEP-ALIVE STOPPED.
S..KMM=73	;KMC11 MISSING FOR A PRESENT DUP11
S..KKF=74	;KMC11 KILL FAILED (TIMED OUT)
;
; THE FOLLOWING STOPCODES ARE USED BY DN65/62 FOR HASP-MULTILEAVING
;
S..HSA=75	;TROUBLE BUIKDING HASP TRANSMISSION BLOCK
S..HSB=76	;POINTER TO DEVICE MESSAGES WIPED OUT (ZERO)
S..HSC=77	;POINTER TO BSC TCB IS ZERO
S..HSD=100	;POINTER TO THE DEVICE'S XLATE TCB IS ZERO
S..HSE=101	;RESERVED FOR HASP-MULTILEAVING
S..HSF=102	;RESERVED FOR HASP-MULTILEAVING
S..HFR=115	;FORMAT ERROR IN RECEIVE DATA
S..HDO=116	;DEVICE REQUESTED BY REMOTE NON-EXISTANT
S..HMS=117	;MESSAGE STUCK IN XLHASP, COULD NOT GO TO BSC
;
; STOP CODES 120 TO 137 ARE RESERVED FOR FUTURE EXTENSIONS TO
;  THE DN60 SERIES.
;
; STOP CODES 140 TO 377 ARE RESERVED FOR FUTURE ASSIGNMENT.
;


S..RNG=141
;STOP CODE MACRO: FORM IS "STOPCD <CODE>,<SEVERITY>"

.MACRO	STOPCD	CD,TYPE
	Z=1
.IF NB TYPE
    .IF IDN <TYPE><DEBUG>
	.IIF EQ DEBUG,Z=0
    .ENDC;.IF IDN <TYPE><DEBUG>
.ENDC;.IF NB TYPE
.IF NE Z
    .IF NB CD
	TRAP	S..'CD
    .IFF
	TRAP
    .ENDC;.IF NB CD
.IFF
	NOP
.ENDC;.IF NE Z
.ENDM	STOPCD
.SBTTL	DEFINE REGISTERS AND PROCESSOR STATUS WORD LOCATION
;
;
;
; REGISTER DEFINITIONS
;
R0=	%0
R1=	%1
R2=	%2
R3=	%3
R4=	%4
R5=	%5
SP=	%6		;STACK POINTER
P=	%6
PC=	%7

	.=177776
PS:	.BLKW	1	;PROCESSOR STATUS WORD
.SBTTL	BIT DEFINES
;
B0=	1
B1=	2
B2=	4
B3=	10
B4=	20
B5=	40
B6=	100
B7=	200
B8=	400
B9=	1000
B10=	2000
B11=	4000
B12=	10000
B13=	20000
B14=	40000
B15=	100000

;DEFINE PROCESSOR LEVELS
;
BR0=	0
BR1=	1*40
BR2=	2*40
BR3=	3*40
BR4=	4*40
BR5=	5*40
BR6=	6*40
BR7=	7*40
.SBTTL		VECTORS

.MACRO	X	TYP,VQ,LQ
.IIF NDF TYP'INT,TYP'INT=	ERRINT
	TYP'VEC=	VQ		;VECTOR FOR TYP IS VQ
.IF B LQ
	TYP'LVL=	7		;DEFAULT LEVEL IS LEVEL 7
.IFF
	TYP'LVL=	LQ		;LEVEL OF TYP IS LQ
.ENDC
.ENDM	X

	X	NXM,04	;BUS-TIMEOUT INTERRUPT
	X	ILS,10	;ILLEGAL INSTRUCTION INTERRUPT
	X	BPT,14	;BPT
	X	IOT,20	;IOT INSTRUCTION
	X	PWF,24	;POWER FAIL INT'S
	X	EMT,30	;EMT CALL'S
	X	TRP,34	;TRAP INSTRUCTION
.SBTTL		CR11 HARDWARE BITS

CR.LVL= 6		; PROCESSOR LEVEL FOR CR11 INTERRUPTS
CR.VEC= 230

.=177160
CR0STS:	.BLKW	1	;CR11 STATUS REGISTER
CR0DAT:	.BLKW	1
CR.STS= CR0STS		; CR11 STATUS REGISTER

	CR.ERR= B15	; ERROR
	CR.DNE= B14	; CARD DONE
	CR.HCK= B13	; HOPPER CHECK
	CR.MCK= B12	; MOTION CHECK
	CR.TIM= B11	; TIMING ERROR
	CR.OLN= B10	; BACK ONLINE AFTER BEING OFF
	CR.BSY= B9	; BUSY
	CR.RDY= B8	; NOT READY
	CR.CDN= B7	; COLUMN DONE
	CR.INE= B6	; INTERRUPT ENABLE
	CR.EJT= B1	; EJECT
	CR.CFD= B0	; CARD FEED
	
CR.DAT= CR0DAT		; 12 LOW ORDER BITS ARE DATA
.SBTTL		CTY HARDWARE BITS

;CTY HARDWARE BITS

	.=177560
CTISTS:	.BLKW	1
CTICHR:	.BLKW	1
CTIVEC=	60
CTILVL=	4	; PRIORITY LEVEL

	CI.INE=	B6		; CTY INPUT INTERRUPT ENABLE

CTOSTS:	.BLKW	1
CTOCHR:	.BLKW	1
CTOVEC=	64
CTOLVL=	4	; PRIORITY LEVEL

	CO.INE=	B6		; CTY OUTPUT INTERRUPT ENABLE
	CO..MM=	B2		; CTY OUTPUT MAINT MODE
.SBTTL		DH11 HARDWARE BITS
DHBASE=	160020		;HARDWARE ADR OF FIRST DH11
DH.LVL=	7		;DH11 INTERRUPT LEVEL

		; 1ST WORD IS SYSTEM CONTROL REGISTER
	DH.RIE=	B6	;RECEIVE INTERRUPT ENABLE
	DH..RI=	B7	;RECEIVE INTERRUPT
	DH.CNX=	B8	;CLEAR NON EX MEM INT
	DH..MM=	B9	;MAINTANCE MODE
	DH.NXM=	B10	;NON EXISTENCE MEMORY
	DH..MC=	B11	;MASTER CLEAR
	DH.SIE=	B12	;STORAGE INTERRUPT ENABLE
	DH.TIE=	B13	;TRANSMIT INTERRUPT ENABLE
	DH..SI=	B14	;STORAGE INTERRUPT
	DH..TI=	B15	;TRANSMIT INTERRUPT
DH.NRC=	2	; 2ND WORD IS NEXT RECEIVED CHAR REGISTER
	DH.VDP=	B15	;VALID DATA PRESENT
	DH.DOV=	B14	;DATA OVER RUN
	DH..FE=	B13	;FRAMING ERROR
	DH..PE=	B12	;PARITY ERROR
			;BITS 11-8 LINE NUMBER
			;BITS 7-0 CHARACTER
DH.LPR=	4	; 3RD WORD IS LINE PARAMETER REGISTER
	DH.AEE=	B15	;AUTO ECHO ENABLE
	DH..HD=	B14	;HALF DUPLEX
	DH..OP=	B5	;ODD PARITY
	DH.PEN=	B4	;PARITY ENABLED
	DH.2SB=	B2	;2 STOP BITS
	DH.CL5=	0	;5 BIT
	DH.CL6=	B0	;6 BIT
	DH.CL7=	B1	;7 BIT
	DH.CL8=	B1!B0	;8 BIT
DH.CAR=	6	; 4TH WORD IS CURRENT ADDRESS REGISTER
DH.BCR=	10	; 5TH WORD IS BYTE COUNT REGISTER
DH.BAR=	12	; 6TH WORD IS BUFFER ACTIVE REGISTER
DH.BRK=	14	; 7TH WORD IS BREAK CONTROL REGISTER
DH.SSR=	16	; 8TH WORD IS SILO STATUS REGISTER
			;BITS 5-0 SILO ALARUM LEVEL
.SBTTL		DL10 HARDWARE BITS
;
;DL10 - UNIBUS TO DECSYSTEM-10 MEMORY BUS INTERFACE
;
	.=100000		;LOCATION OF CSR
DL.BAS:	.BLKW	1		;BASE ADDRESS FOR 10 MEMORY
DLBASE=	DL.BAS			;
DL.VEC=	170			;VECTOR ADR FOR DL10
DL.LVL=	5			;CHANNEL FIVE

DL.STS=DLBASE	;1ST WORD IS STATUS
	DL.11I=	B15		; BIT 15 - 11 INT(INTERRUPTS IF 11-INT-ENB SET)
	DL.11C=	B14		; BIT 14 - CLEAR 11 INT
	DL.10I=	B13		; BIT 13 - 10 INT
	DL.10C=	B12		; BIT 12 - CLEAR 10 INT
	DL.NXM=	B11		; BIT 11 - NXM(INTERRUPTS IF ERR ENB SET)
	DL.CNX=	B10		; BIT 10 - CLEAR NXM
	DL.PAR=	B9		; BIT 09 - PAR ERR(INTERRUPTS IF ERR ENB SET)
	DL.CPE=	B8		; BIT 08 - CLEAR PAR ERR
	DL.WCO=	B7		; BIT 07 - WCOV(INTERRUPTS IF ERR ENB SET)
	DL.CWC=	B6		; BIT 06 - CLEAR WCOV
	DL.PEN=	B5		; BIT 05 - PORT ENABLE
	DLPENB=	DL.PEN		;
	DL.B04=	B4		; BIT 04 - (GUESS !)
	DL.ERE=	B3		; BIT 03 - ERR ENABLE
	DL.INE=	B2		; BIT 02 - 11 INT ENB
	DL.B01=	B1		; BITS 00 & 01 - PIA
	DL.B00=	B0		;
.SBTTL		DM11-BB HARDWARE BITS

	.=170500
DMBASE:	.BLKW	1	;HDW ADR OF FIRST DM11

DM.LVL=	7		;PROCESSOR LEVEL FOR DM11BB INTERRUPTS

	B.DM11=	DMBASE	;FIRST DM11 ADR
	DM.SCN=	B11	;CLEAR SCANNER
	DM.INI=	B10	;CLER MULTIPLEXER
	DM..MM=	B9	;MAINTANCE MODE
	DM.STP=	B8	;STEP TO NEXT LINE
	DM.DNE=	B7
	DM.IEN=	B6	;INTERRUPT ENABLE
	DM.ENB=	B5	;SCAN ENABLE
	DM.BSY=	B4	;CLEAR SCAN STILL PERCOLATING
	DM.ALI=	B0!B1!B2!B3	;LINE NUMBER FIELD

; EIA PIN DEFINITIONS:

;	1	PROTECTIVE GROUND
;	2	TRANSMITTED DATA
;	3	RECEIVED DATA
;	4	REQUEST TO SEND
;	5	CLEAR TO SEND
;	6	DATA SET READY
;	7	SIGNAL GROUND
;	8	RECEIVED LINE SIGNAL DECTECTOR
;	17	RECEIVED SIGNAL ELEMENT TIMING
;	20	DATA TERMINAL READY
;	21	SIGNAL QUALITY DETECTOR
;	22	RING INDICATOR
;	24	TRANSMIT SIGNAL ELEMENT TIMING
.SBTTL		DN11 HARDWARE BITS

DN.LVL=	7			;PROCESSOR LEVEL FOR DN INTERRUPTS

	.=175200
DNBASE:	.BLKW	1		;CSR ADDRESS

	DN.PWI=	B15		;POWER INDICATE
	DN.ACR=	B14		;ABANDON CALL AND RETRY
	DN.DLO=	B13		;DATA LINE OCCUPIED
	DN.DNE=	B7		;DONE
	DN..IE=	B6		;INTERRUPT ENABLE
	DN.DSS=	B5		;DATA SET STATUS
	DN.PND=	B4		;PRESENT NEXT DIGIT
	DN..MM=	B3		;MAINTENANCE MODE
	DN..ME=	B2		;MASTER ENABLE
	DN..DP=	B1		;DIGIT PRESENT
	DN..CR=	B0		;CALL REQUEST
	DN.DGT=B8+B9+B10+B11	;DIGIT BITS
.SBTTL		DP11 HARDWARE BITS

DP.LVL=	7	;PROCESSOR LEVEL FOR DP11 INTERRUPTS

;A) RECEIVER STATUS REGISTER  (ADR = XXXXX0)

DP..CP=	B12		;CHARACTER PARITY; 1=ODD, 0=EVEN
DP..RA=	B11		;RECEIVE ACTIVE
DP..RD=	B7		;RECEIVE DONE
DP.RIE=	B6		;RECEIVE DONE INTERRUPT ENABLE
DP..MR=	B3		;MISCELLANEOUS RECEIVE
DP..MM=	B2		;MAINTENANCE MODE
DP..HD=	B1		;HALF DUPLEX
DP..SS=	B0		;STRIP SYNC

;B) TRANSMIT AND CONTROL STATUS REG  (ADR = XXXXX2)

DP..CF=	B15		;CARRIER FLAG
DP.ROF=	B14		;RECEIVE OVERRUN FLAG
DP.RNG=	B13		;RING FLAG
DP.MRY=	B12		;MODEM READY
DP.CAR=	B11		;CARRIER
DP.CTS=	B10		;CLEAR TO SEND
DP.RTS=	B9		;REQUEST TO SEND
DP..TD=	B7		;TRANSMIT DONE
DP.TIE=	B6		;TRANSMIT DONE INTERRUPT ENABLE
DP.SIE=	B5		;STATUS INTERRUPT ENABLE
DP.MIS=	B4		;MISCELLANEOUS
DP..MT=	B3		;MISCELLANEOUS TRANSMIT
DP..IS=	B1		;IDLE SYNC
DP.DTR=	B0		;TERMINAL READY
.SBTTL		DQ11 HARDWARE BITS

DQ.LVL=	7		;PROCESSOR LEVEL FOR DQ11 INTERRUPTS

; THE BASE ADR FOR THE DQ11 IS CONTAINED IN THE LINE BLOCK
; RECEIVE STATUS ( ADR =XXXXX0 )

	DQ.RGO=	B0	; RECEIVE GO
	DQ.SSY=	B1	; STRIP SYNC
	DQ.SEC=	B2	; 0=	PRIMARY,1=SECONDARY
	DQ.HD=	B3	; HALF DUPLEX(=	MASK INPUT WHEN XMT ACTIVE)
	DQ.CIE=	B4	; CHAR INTERRUPT ENABLE
	DQ.RIE=	B5	; RECEIVE DONE INTERRUPT ENABLE
	DQ.RDS=	B6	; RECEIVE DONE (SECONDARY) FLAG
	DQ.RDP=	B7	; RECEIVE DONE (PRIMARY) FLAG
	DQ.CHR=	7400	; CHAR DETECTED
	DQ.ETB=	B8	; CHAR WAS AN ETB
	DQ.ETX=	B9	; CHAR WAS AN ETX
	DQ.ENQ=	B10	; CHAR WAS AN ENQ
	DQ.SYN=	B11	; SPECIAL CHAR WAS A SYNC
	DQ.RAC=	B12	; RECEIVE ACTIVE
;		060000	; USER OPTION
	DQ.VCH=	B15	; VCHAR FLAG
	DQ.RKL=	DQ.RAC!DQ.VCH!DQ.RGO!DQ.CIE	; BITS TO STOP RECEIVER
;
; TRANSMIT STATUS ( ADR = XXXXX2 )

	DQ.XGO=	B0	; TRANSMIT GO
;		B1	; IDLE MODE
	DQ.SEC=	B2	; 0=	PRIMARY ACTIVE,1=SECONDARY ACTIVE
	DQ.EIE=	B3	; ERR INTERRUPT ENABLE
	DQ.DIE=	B4	; DATA SET INTERRUPT ENABLE
	DQ.XIE=	B5	; TRANSMIT DONE INTERRUPT ENABLE
	DQ.XDS=	B6	; TRANSMIT DONE(SECONDARY)
	DQ.XDP=	B7	; TRANSMIT DONE(PRIMARY)
	DQ.RTS=	B8	; REQUEST TO SEND
	DQ.DTR=	B9	; DATA TERMINAL READY
	DQ.DSR=	B10	; DATA SET READY
	DQ.RNG=	B11	; RING
	DQ.CAR=	B12	; CARRIER
	DQ.CTS=	B13	; CLEAR TO SEND
;		B14	; USER OPTION
	DQ.DSF=	B15	; DATA SET FLAG
; REG/ERR REGISTER ( ADR =XXXXX4 )

	DQ.XCL=	B0	; TRANSMIT CLOCK LOSS
	DQ.RCL=	B1	; RECEIVE CLOCK LOSS
	DQ.XLE=	B2	; TRANSMIT LATENCY ERROR
	DQ.RLE=	B3	; RECEIVE LATENCY ERROR
	DQ.XNX=	B4	; TRANSMIT NONEX MEM
	DQ.RNX=	B5	; RECEIVE NONEX MEM
	DQ.BCC=	B6	; RECEIVE BCC ERROR
	DQ.VRC=	B7	; RECEIVE VRC ERROR
;		007400	; REG SELECT FOR REFERENCE TO XXXXX6
	DQ.MEM=	B12	; WRENABLE 060000
	DQ.MBM=	020	; BYTE EQUIVALENT OF ABOVE
;		060000	; MEM EXT OR ENTER T/EXIT T
;		B15	; ERROR INTERRUPT

; SECONDARY REGISTERS ( ADR = XXXXX6 )

	RG.PRA=	0	; PRIMARY RECEIVE BA
	RG.PRC=	1	; PRIMARY RECEIVE CC
	RG.PTA=	2	; PRIMARY TRANSMIT BA
	RG.PTC=	3	; PRIMARY TRANSMIT CC
	RG.SRA=	4	; SECONDARY RECEIVE BA
	RG.SRC=	5	; SECONDARY RECEIVE CC
	RG.STA=	6	; SECONDARY TRANSMIT BA
	RG.STC=	7	; SECONDARY TRANSMIT CC
;		10	; CHAR DET REG
	RG.SYN=	11	; SYNC REG
	RG.MSC=	12	; MISC REG
	DQ.MC=	B5	; MASTER CLEAR (SORT OF)
;		13	; TRANSMIT BUF
;		14	; SEQUENCE REGISTER
;		15	; RECEIVE BCC
;		16	; TRANSMIT BCC
;		17	; RECEIVE/TRANSMIT POLYNOMIAL
; MACRO TO SELECT A PARTICULAR DQ11 "INTERNAL" REGISTER

.MACRO	DQREGS	REG,QQ
Z=	RG.'REG
.IIF EQ <Z&10>,Z=	Z+DQ.MBM
.IF B,QQ
	MOVB	#Z,5(DQ) 	;SET TO ADDRESS SECONDARY REGISTER RG.'REG
.IFF
	MOVB	#Z,5QQ	;SET TO ADDRESS SECONDARY REGISTER RG.'REG
.ENDC
.ENDM	DQREGS
.SBTTL		DS11 HARDWARE BITS

;HARDWARE ADDRESSES

DS.AUX=	175600		;AUXILLARY REGISTER
DS.DVA=	175400		;BEGINNING OF LINE DEVICE REGISTERS
DS.VEC=	400		;FIRST DS11 VECTOR
DS.LVL=	7		;PROCESSOR LEVEL OR DS11 INTERRUPTS

;BITS IN AUXILLARY REGISTER

DS.AD3=B15		;ADAPTER 3 IS PRRSENT IF SET
DS.AD2=B14		;ADAPTER 2 IS PRESENT IF SET
DS.AD1=B13		;ADAPTER 1 IS PRESENT IF SET
;	B12		;NOT USED
;	B11		;NOT USED
;	B10		;NOT USED
;	B9		;PROGRAM VECTOR 9
DS.IVA=B8		;PROGRAM VECTOR 8 - INTERRUPTS START AT 400
;	B7		;DIAG MODE
;	B6		;PROGRAM CLOCK ALLOW
;	B5		;NOT USED
;	B4		;DIAG BIT CNTR CLEAR
;	B3		;DIAG BIT COUNTER 4
;	B2		;DIAG BIT COUNTER 3
;	B1		;DIAG BIT COUNTER 2
;	B0		;DIAG BIT COUNTER 1


;OFFSETS OF REGISTERS FROM LINE BASE ADDRESS

DS.XDR=6		;TRANSMIT DATA REGISTER
DS.XST=4		;TRANSMIT STATUS REGISTER
DS.RDR=2		;RECEIVE DATA REGISTER
DS.RST=0		;RECEIVE STATUS REGISTER

;PRIORITY INTERRUPT LEVELS

I.DSRD=7		;RECEIVE DATA INTERRUPT
I.DSRS=6		;RECEIVE STATUS INTERRUPT
I.DSXD=7		;A TRANSMIT DATA INTERRUPT
I.DSXS=6		;A TRANSMIT STATUS INTERRUPT

;BITS IN XMIT STATUS REGISTER & RECEIVE REG.

DS.DTR=000440		;BOTH XMT & RCV REG.
DS.ZAP=170000		;CLEAR ALL OVERRUN FLAGS
DS.XGO=DS.DTR+<<I.DSXD/2>*4>+1	;REQUEST TO SEND
DS.RGO=B11!B10!DS.DTR!<<I.DSRD/2>*4>+1	;RECEIVE
;BITS IN TRANSMIT STATUS REGISTER
;
;	B15		; NOT USED
;	B14		; XMIT BIT OVERRUN
;	B13		; XMIT CHAR OVERRUN
;	B12		; CLEAR TO SEND FLAG
;	B11		; NOT USED
;	B10		; NOT USED
;	B9		; CLEAR TO SEND
;	B8		; DATA TERM READY
;	B7		; XMIT CHAR DONE
;	B6		; DATA SET READY
;	B5		; CODE SIZE 2
;	B4		; CODE SIZE 1
;	B3		; PRIORITY REQUEST 2
;	B2		; PRIORITY REQUEST 1
;	B1		; IDLE
;	B0		; REQUEST TO SEND

;BITS IN RECEIVE STATUS REGISTER
;
;	B15		; RING FLAG
;	B14		; REC BIT OVERRUN
;	B13		; REC CHAR OVERRUN
;	B12		; LINE SIGNAL FLAG
;	B11		; SYN STATE 2
;	B10		; SYN STATE 1
;	B9		; LINE SIGNAL
;	B8		; DATA TERMINAL READY
;	B7		; REC CHAR DONE
;	B6		; DATA SET READY
;	B5		; CODE SIZE 2
;	B4		; CODE SIZE 1
;	B3		; PRIORITY REQUEST 2
;	B2		; PRIORITY REQUEST 1
;	B1		; RING ALLOW
;	B0		; RECEIVE
.SBTTL		DUP11 HARDWARE BITS
;
UP.LVL=7		;DUP11 INTERRUPT LEVEL
;
UP.RSR=0		;RECEIVER STATUS REGISTER

UP.DCB=B0	;DATA SET CHANGE B
UP.DTR=B1	;DATA TERMINAL READY
UP.RTS=B2	;REQUEST TO SEND
UP.STD=B3	;SECONDARY TRANSMIT DATA
UP.REN=B4	;RECEIVER ENABLE
UP.DIE=B5	;DATASET INTERRUPT ENABLE
UP.RIE=B6	;RECEIVER INTERRUPT ENABLE
UP.RDN=B7	;RECEIVER DONE
UP.SSY=B8	;STRIP SYNC
UP.DSR=B9	;DATA SET READY
UP.SRD=B10	;SECONDARY RECEIVED DATA
UP.RAT=B11	;RECEIVE ACTIVE
UP.CAR=B12	;CARRIER
UP.CTS=B13	;CLEAR TO SEND
UP.RNG=B14	;RING
UP.DCA=B15	;DATA SET CHANGE A
;
UP.RBF=2		;RECEIVER DATA BUFFER

; B0-B7		;CHARACTER RECEIVED
UP.RSM=B8	;RECEIVE START OF MESSAGE
UP.REM=B9	;RECEIVE END OF MESSAGE
UP.RAB=B10	;RECEIVE ABORT
UP.RCR=B12	;CRC
UP.OVR=B14	;OVERRUN
UP.ERR=B15	;SUMMARY ERROR
;
;
UP.PAR=2		;PARAMETER STATUS REGISTER
;
; B0-B7		;SYNC CHARACTER
UP.CCI=B9	;CRC INHIBIT
UP.SMS=B12	;SECONDARY MODE SELECT
UP.DMD=B15	;DEC (I.E., BYTE) MODE
;
UP.XSR=4		;TRANSMITTER STATUS REGISTER
;
UP.HDX=B3	;HALF DUPLEX
UP.SND=B4	;SEND
UP.XIE=B6	;TRANSMITTER INTERRUPT ENABLE
UP.XDN=B7	;TRANSMITTER DONE
UP.INI=B8	;INITIALIZE (DEVICE RESET)
UP.XAT=B9	;TRANSMITTER ACTIVE
UP.XDL=B15	;TRANSMITTER DATA LATE
;
UP.XBF=6		;TRANSMITTER DATA BUFFER
;
; B0-B7		;CHARACTER TO TRANSMIT
UP.XSM=B8	;TRANSMIT START OF MESSAGE
UP.XEM=B9	;TRANSMIT END OF MESSAGE
UP.XAB=B10	;TRANSMIT ABORT
;
.SBTTL		DZ11 Hardware Bits

DZ.LVL=5				;DZ11 interrupt level

DZ.CSR=0	;1st word is control and status register

	DZ.MAI=B3		;maintenance mode bit
	DZ.CLR=B4		;clears silo, all UARTs and CSR
	DZ.MSE=B5		;master scan enable
	DZ.RIE=B6		;receive interrupt enable
	DZ..RI=B7		;receive done (RO)
				;causes interrupt if DZ.RIE=1 and 
				;DZ.SAE=0
	DZ.TLN=B8!B9!b10	;transmit line number (RO) when DZ..TI=1
	DZ.SAE=B12		;Silo alarm enable; if 1 prevents
				;DZ..RI from interrupting and if
				;DZ.RIE=1, allows DZ..SA to interrupt
	DZ..SA=B13		;Silo alarm (RO), set to 1 after 16 chars enter silo
	DZ.TIE=B14		;transmit interrupt enable
	DZ..TI=B15		;transmit ready (RO)

DZ.RBF=2	;Receive buffer register (RO)

	DZ.RCH=B0!B1!B2!B3!B4!B5!B6!B7 ;received character
	DZ.RLN=B8!B9!B10	;received line number
	DZ..PE=B12		;parity error
	DZ..FE=B13		;framing error
	DZ.DOV=B14		;overrun
	DZ.VDP=B15		;valid data

DZ.LPR=2	;Line parameter register (WO)

	DZ.PLN=B0!B1!B2		;line number for parameter loading
	DZ.CL5=0		;5 bit characters
	DZ.CL6=B3		;6 bit characters
	DZ.CL7=B4		;7 bit characters
	DZ.CL8=B3!B4		;8 bit characters
	DZ.2SB=B5		;send 2 stop bits (or 1.5 for 5 bit chars)
	DZ.PEN=B6		;parity enabled on transmit and receive
	DZ..OP=B7		;1=odd parity, 0=even parity
	DZ.SPD=B8!B9!B10!B11	;code for transmit and receive speed
				;0=50;1=75;2=110;3=134.5;4=150;5=300;6=600;7=1200
				;10=1800;11=2000;12=2400;13=3600;14=4800;15=7200;16=9600
				;17=unused
	DZ.RON=B12		;receiver on (setting to 1 turns on receiver clock)
DZ.TCR=4	;transmit control register

;	bits 0-7 are transmit enables for lines 0-7
;	bits 8-15 are DTR for lines 0-7

DZ.MSR=6	;modem status register (RO)

;	bits 0-7 are ring indicators for lines 0-7
;	bits 8-15 are carrier indicators for lines 0-7

DZ.TDR=6	;transmit data register (WO)

	DZ.TCH=B0!B1!B2!B3!B4!B5!B6!B7 ;character to be transmitted
;	bits 8-15 are transmit break bits for lines 0-7
.SBTTL		KG11 HARDWARE BITS

	.=170700
KG.STS:	.BLKW	1	;STATUS REGISTER
	KG.DNE=B7	;CALCULATION DONE
	KG.SEN=B6	;NOT SINGLE CYCLE
	KG.STP=B5	;STEP
	KG.CLR=B4	;CLEAR
	KG.DDB=B3	;WORD MODE
	;	007	;TYPE OF CALCULATION
			; 1 = CRC-16
			; 3 = LRC-16
			; 5 = CRC-CCITT
KG.INI=KG.SEN!KG.CLR!1	;NOT SINGLE CYCLE, CLEAR, CRC-16
KG.BCC:	.BLKW	1
KG.DTA:	.BLKW	1
;
.SBTTL		KW11-L HARDWARE BITS

;KW11-L LINE FREQUENCY CLOCK DEFINITIONS

CLKLVL=	6		; CLOCK INTERRUPT PRIORITY LEVEL
CLKVEC=	100		; CLOCK VECTOR

	.=177546
CLKWRD:	.BLKW	1	; CLOCK STATUS WORD

	KW.INE=B6	; ENABLE INTERRUPTS
	KW.TIC=B7	;SET BY CLOCK AND CLEARED BY PROGRAM
.SBTTL		LP11 HARDWARE BITS

LP.LVL=	4		; PROCESSOR LEVEL FOR LP11 INTERRUPTS
LP.VEC=	200		; VECTOR LOCATION

	.=177514
LP0STS:	.BLKW	1	;STATUS REGISTER FOR 1ST LP11
	LP.STS=LP0STS

	LP.ERR=	B15	; ERROR BIT(POWER OFF, NO PAPER, GATE, TEMP, OFFLINE)
	LP.DNE=	B7	; READY FOR NEXT CHARACTER
	LP.INE=	B6	; INTERRUPT ENABLE

LP0DAT:	.BLKW	1	;DATA REGISTER
	LP.DAT=LP0DAT


;FOR THE SECOND LP11
LP1STS:	.BLKW	1
LP1DAT:	.BLKW	1
	.SBTTL	LP20 HARDWARE BITS

; NOTATION:
; 	(R) ==> READ
; 	(W) ==> WRITE
; 	(RW) ==> READ/WRITE


L2.LVL=	4	; INTERUPT AT LEVEL 4 (DEFAULT)
L2.VEC=	754	; VECTOR FOR LP20
L20STS=	175400	; ADDRESS OF FIRST LP20
L21STS=	175420	; ADDRESS OF SECOND LP20

L20CRA=	0			; CONTROL REGISTER A FOR LP20
	L2.ERR=	100000		; (R) ERROR
	L2.PZE=	40000		; (R) PAGE COUNT WENT ZERO
	L2.UCD=	20000		; (R) UNDEFINED CHAR DETECTED
	L2.DR=	10000		; (R) DAVFU READY
	L2.ONL=	4000		; (R) ON LINE
	L2.DH=	2000		; (RW)DELIMIT HOLD
	L2.ERE=	1000		; (W) ERROR RESET
	L2.INI=	400		; (W) LOCAL INIT
	L2.DON=	200		; (R) DONE
	L2.ENB=	100		; (RW)INTERUPT ENABLE
	L2.A17=	40		; (RW)BAU ADDR BIT 17
	L2.A16=	20		; (RW)BUS ADDR BIT 16
	L2.DL=	10		; (RW)DAVFU LOAD
	L2.TM=	4		; (RW)TEST MODE
	L2.PEN=	2		; (RW)PARITY ENABLE
	L2.GO=	1		; (RW)THE GO BIT

L20CRB=	L20CRA+2
	L2.VD=	100000		; (R) VALID DATA
	L2.SPR=	40000		; (R) SPARE
	L2.PNR=	20000		; (R) PRINTER NOT READY
	L2.LDP=	10000		; (R) LPT DATA PARITY
	L2.OVF=	4000		; (R) OPTICAL VFU ON LPT
	L2.TB2=	2000		; (RW)TEST BIT 2
	L2.TB1=	1000		; (RW)TEST BIT 1
	L2.TB0=	400		; (RW)TEST BIT 0
	L2.POL=	200		; (R) PRINTER OFF LINE
	L2.DNR=	100		; (R) DAVFU NOT READY
	L2.LPE=	40		; (R) LPT DATA PARITY ERROR
	L2.MPE=	20		; (R) MEMORY PARITY ERROR
	L2.RPE=	10		; (R) RAM PARITY ERROR
	L2.MST=	4		; (R) MASTER SYNC TIMEOUT
	L2.DTE=	2		; (R) DEMAND TIMEOUT ERROR
	L2.GER=	1		; (RW)GO ERROR
.SBTTL		MF11-UP PARITY MEMORY

	MP.VEC=114	;INTERRUPT HERE ON PARITY ERROR
	MP.LVL=7

	.=172100
MP.REG:	.BLKW	1	;ADDR OF PARITY REGISTER FOR 16K

	MP.ERR=B15	;ERROR BIT
			; BITS 11-5 ERROR ADDRESS
	MP.WWP=B2	;WRITE WRONG PARITY
	MP.ENB=B0	;ENABLE
.SBTTL		KT11-D Memory Management Option

MM.SR0=177572		; Memory management Status Register
KPAR0=172340
KPAR1=172342
KPAR2=172344
KPAR3=172346
KPAR4=172350
KPAR5=172352
KPAR6=172354
KPAR6=172356
MM.PDR=-40		; difference to get PDR from PAR
.SBTTL		KMC11 HARDWARE BITS
;
MD.LVL=5		;PROCESSOR LEVEL FOR KMC11 INTERRUPTS
;
; BIT ASSIGNMENTS FOR THE KMC11 MAINTENENCE REGISTER - BSEL 1
;
MD.RUN=B15		;RUN THE MICROPROCESSOR
MD.CLR=B14		;CLEAR THE KMC11
MD.CWR=B13		;CRAM WRITE
MD.SLU=B12		;STEP LINE UNIT
MD.LLU=B11		;LOOP LINE UNIT
MD.RMO=B10		;ROM OUTPUT
MD.RMI=B9		;ROM INPUT
MD.SMP=B8		;STEP MICROPROCESSOR
;
.SBTTL		DMC11 Hardware Bits

MC.LVL=5			; hardware level for DMC11 interrupts

MC.CSI=0			; Input (i.e. to DMC11) control register
	MC.TPI=B0+B1		; Type of input transaction
				; 00=BA/CC In; 01=Cntrl In; 11=Base In
	  MC.BCI=0
	  MC.CTI=1
	  MC.BSI=3
	MC.IOI=B2		; 1=Input, 0=Output Buffer
	MC.RQI=B5		; Request Input transaction
	MC.IEI=B6		; Input transaction interrupt enable
	MC.RDI=B7		; Input transaction ready
;Maintenance Bits
	MC.SMP=B8		;Step microprocessor
	MC.RMI=B9		;ROM in
	MC.RMO=B10		;ROM out
	MC.MCL=B14		; Master Clear
	MC.RUN=B15		; Run

MC.CSO=2			; Output (i.e. from DMC11) control register
	MC.TPO=B0+B1		; type of output transaction
				; 00=BA/CC Out; 01=Cntrl Out
	  MC.BCO=0
	  MC.CTO=1
	MC.IOO=B2		; 1=Input, 2=Output
	MC.IEO=B6		; Out transaction interrupt enable
	MC.RDO=B7		; Ready Out

MC.DT0=4			; first data word

; For BA/CC I, BA/CC O, CNTL I, CNTL O and Base I formats

	MC.BA=B0		; 16 bit bus address

MC.DT2=6			; second data word

; For BA/CC I, BA/CC O, BASE I, CNTL I and CNTL O formats

	MC.HBA=B15		; the two high order bits of bus address
; For BA/CC I and BA/CC O formats

	MC.CC=B0		; 14-bit positive character count

; For BASE I format

	MC.RES=B14		; resume bit: 0=clear base table, 1=use old base table

; For CNTL I format

	MC.SCA=B0		; 8-bit secondary address
	MC.MAI=B8		; maintenance bit: 1=go into maintenance mode
	MC.HD=B10		; 1=go into DDCMP half-duplex mode 
	MC.SEC=B11		; 1=become a secondary station

; For CNTL O format

	MC.DCK=B0		; data check
	MC.TMO=B1		; time out
	MC.OVR=B2		; overrun
	MC.RMA=B3		; received maintenance message
	MC.LOS=B4		; lost data
	MC.DSC=B6		; disconnect
	MC.RST=B7		; received start mesage
	MC.NXM=B8		; non-existent memory
	MC.ERR=B9		; processor error
.SBTTL		PC11 HARDWARE BITS

PR.LVL=	4		; PROCESSOR LEVEL FOR PC11 READER INTERRUPTS
PR.VEC=	70		; VECTOR FOR PC11 READER
PP.LVL=	4		; PROCESSOR LEVEL FOR PC11 PUNCH INTERRUPTS
PP.VEC=	74		; VECTOR FOR PC11 PUNCH

	.=177550
PR0STS:	.BLKW	1	;STATUS REGISTER FOR 1ST PC11 READER
PR.STS=	PR0STS		; READER STATUS REGISTER

	PR.ERR=	B15	; ERROR BIT (NO TAPE, NO POWER, OR OFF-LINE)
	PR.BSY=	B11	; SET WHEN A CHARACTER IS BEING READ
	PR.DNE=	B7	; CHARACTER IS AVAILABLE IN THE READER BUFFER
	PR.INE=	B6	; INTERRUPT ENABLE
	PR..RE=	B0	; READER ENABLE

PR.DAT:	.BLKW	1	; READER BUFFER REGISTER

PP0STS:	.BLKW	1	;STATUS REGISTER FOR 1ST PC11 PUNCH
PP.STS=	PP0STS		; PUNCH STATUS REGISTER

	PP.ERR=	B15	; ERROR BIT (NO TAPE OR NO POWER)
	PP.RDY=	B7	; SET WHEN READY TO PUNCH A CHARACTER
	PP.INE=	B6	; INTERRUPT ENABLE

PP.DAT:	.BLKW	1	; PUNCH BUFFER REGISTER
.SBTTL		TC11 HARDWARE BITS

TC.VEC=	214			; TC11 INTERRUPT VECTOR ADDRESS

TC.LVL=	6			; TC11 PRIORITY LEVEL

	.=177340
TC.STS:	.BLKW	1		; TC11 CONTROL AND STATUS REGISTER

	TC..EZ=	B15		; END ZONE
	TC.PAR=	B14		; PARITY ERROR
	TC.MTE=	B13		; MARK TRACK ERROR
	TC.ILO=	B12		; ILLEGAL OPERATION
	TC..SE=	B11		; SELECTION ERROR
	TC..BM=	B10		; BLOCK MISSED
	TC..DM=	B9		; DATA MISSED
	TC.NXM=	B8		; NON-EX MEM
	TC.UPS=	B7		; TAPE IS UP TO SPEED
	TC.CLK=	B6		; USED TO SIMULATE TIMING TRACK
	TC.MMT=	B5		; MAINT MARK TRACK
	TC.DT0=	B4		; DATA TRACK 0
	TC.DT1=	B3		; DATA TRACK 1
	TC.DT2=	B2		; DATA TRACK 2
	TC.D17=	B1		; EXTENDED DATA 17
	TC.D16=	B0		; EXTENDED DATA 16

TC.CMD:	.BLKW	1		; TC11 COMMAND REGISTER

	TC.ERR=	B15		; ERROR
	TC..MM=	B13		; MAINT MODE
	TC..DI=	B12		; DELAY INHIBIT
	TC.REV=	B11		; SET = REVERSE MOTION; CLEAR = FORWARD MOTION
	TC.US0=	0		; SELECT UNIT 0
	TC.US1=	B8		; SELECT UNIT 1
	TC.US2=	B9		; SELECT UNIT 2
	TC.US3=	B9!B8		; SELECT UNIT 3
	TC.US4=	B10		; SELECT UNIT 4
	TC.US5=	B10!B8		; SELECT UNIT 5
	TC.US6=	B10!B9		; SELECT UNIT 6
	TC.US7=	B10!B9!B8	; SELECT UNIT 7
	TC.RDY=	B7		; READY
	TC.INE=	B6		; INTERRUPT ENABLE
	TC.A17=	B5		; EXTENDED MEM BIT BA17
	TC.A16=	B4		; EXTENDED MEM BIT BA16
	TC.SAT=	0		; STOP ALL TAPE MOTION
	TC.RMT=	B1		; FINDS MARK TRACK CODE
	TC..RD=	B2		; READ
	TC.RDA=	B2!B1		; READ ALL
	TC.SST=	B3		; STOP ALL TAPE MOTION IN SELECTED TRANSPORT ONLY
	TC.WTM=	B3!B1		; WRITE TIMING AND MARK TRACK
	TC..WR=	B3!B2		; WRITE
	TC.WRA=	B3!B2!B1	; WRITE ALL
TC.WCR:	.BLKW	1		; TC11 WORD COUNT REGISTER

TC.BAR:	.BLKW	1		; TC11 BUS ADDRESS REGISTER

TC.DAT:	.BLKW	1		; TC11 DATA REGISTER
.SBTTL		DTE20 HARDWARE BITS
;
TE.LVL=6		;PROCESSOR LEVEL FOR DTE20 INTERRUPTS
TE.VEC=774		;VECTOR FOR DTE20 INTERRUPTS

TE.DYC=0		;DELAY COUNTER
TE.XW3=2		;DEPOSIT OR EXAMINE WORD 3
TE.XW2=4		;DEPOSIT OR EXAMINE WORD 2
TE.XW1=6		;DEPOSIT OR EXAMINE WORD 1
TE.XA1=10		;TEN ADDRESS WORD 1
;
TS.DEP=B12		;DEPOSIT
TS.POF=B11		;EXAMINE/DEPOSIT PROTECT OFF
TS.PEX=B15		;PHYSICAL EXAMINE
;
TE.XA2=12		;TEN ADDRESS WORD 2
TE.XBC=14		;TO-10 BYTE COUNT (?)
TE.EBC=16		;TO-11 BYTE COUNT
;
TS.IFB=B15		;I FLIPFLOP BIT
TS.ZST=B14		;ZSTOP
TS.EBM=B13		;TO 11 BYTE MODE
;
TE.XAD=20		;TO-10 PDP-11 MEMORY ADDRESS
TE.EAD=22		;TO-11 PDP-11 MEMORY ADDRESS
TE.XDT=24		;TO-10 PDP-11 DATA WORD
TE.EDT=26		;TO-11 PDP-11 DATA WORD
TE.DG1=30		;DIAGNOSTIC WORD 1
TE.DG2=32		;DIAGNOSTIC WORD 2
TS.RST=B6		;RESET DTE20
;
;
TE.STW=34		;STATUS WORD
;
TS.XNT=B15		;TO-10 NORMAL TERMINATION
TS.XTS=B14		;TO-10 NORMAL TERMINATION STATUS
TS.XER=B13		;TO-10 ERROR TERMINATION (AND STATUS)
TS.XEC=B12		;CLEAR TO-10 ERROR TERMINATION
TS.XEE=B11		;10 REQUESTED -11 INTERRUPT
TS.RES=B11		;REQUEST -11 STATUS
TS.EIS=B10		;10 REQUESTS 11 INTERRUPT STATUS
TS.MPE=B9		;11 MEMORY PARITY ERROR
TS.EEX=B8		;11 REQUESTED 10 INTERRUPT
TS.ETD=B7		;TO-11 TRANSFER DONE
TS.ENT=B6		;TO-11 NORMAL TERMINATION
TS.EEE=B5		;11 INTERRUPT ENABLE
TS.EPE=B4		;E-BUS PARITY ERROR
TS.RM=B3		;RESTRICTED MODE
TS.DEI=B3		;DISABLE -11 INTERRUPT
TS.XDN=B2		;DEPOSIT/EXAMINE DONE
TS.EET=B1		;TO-11 ERROR TERMINATION (AND STATUS)
TS.IEN=B0		;INTERRUPTS ENABLED
TS.CET=B0		;CLEAR TO-11 ERROR TERMINATION
;
TE.DG3=36		;STATUS WORD 3
TS.TBM=B0		;TO TEN BYTE MODE
;
.SBTTL		TM11 HARDWARE BITS

TM.VEC=	224			; TM11 VECTOR ADDRESS

TM.LVL=	5			; TM11 PRIORITY LEVEL

	.=172520
TM.STS:	.BLKW	1		; STATUS REGISTER

	TM..IC=	B15		; ILLEGAL COMMAND
	TM.EOF=	B14		; END OF FILE
	TM.CRE=	B13		; CYCLICAL REDUNDANCY
	TM.PAE=	B12		; PARITY ERROR
	TM.BGL=	B11		; BUS GRANT LATE
	TM.EOT=	B10		; END OF TAPE
	TM.RLE=	B9		; RECORD LENGTH ERROR
	TM.BTE=	B8		; BAD TAPE ERROR
	TM.NXM=	B7		; NON-EXISTENT MEMORY
	TM.SLR=	B6		; SELECT REMOTE
	TM.BOT=	B5		; BEGINNING OF TAPE
	TM.7CH=	B4		; SEVEN CHANNEL
	TM.TSD=	B3		; TAPE SETTLE DOWN
	TM.WRL=	B2		; WRITE LOCK
	TM.RWS=	B1		; REWIND STATUS
	TM.TUR=	B0		; TAPE UNIT READY
TM.MTC:	.BLKW	1		; COMMAND REGISTER

	TM.ERR=	B15		; ERROR
	TM.D72=	0		; 200 BPI 7 CHANNEL
	TM.D75=	B13		; 556 BPI 7 CHANNEL
	TM.D78=	B14		; 800 PBI 7 CHANNEL
	TM.D98=	B14!B13		; 800 BPI 9 CHANNEL
	TM..PC=	B12		; POWER CLEAR
	TM..LP=	B11		; LATERAL PARITY
	TM..US=	B10!B9!B8	; UNIT SELECT FIELD
	TM.US0=	0		; SELECT UNIT 0
	TM.US1=	B8		; SELECT UNIT 1
	TM.US2=	B9		; SELECT UNIT 2
	TM.US3=	B8!B9		; SELECT UNIT 3
	TM.US4= B10		; SELECT UNIT 4
	TM.US5=	B10!B8		; SELECT UNIT 5
	TM.US6=	B10!B9		; SELECT UNIT 6
	TM.US7=	B10!B9!B8	; SELECT UNIT 7
	TM.CUR=	B7		; CU READY
	TM.INE=	B6		; INTERRUPT ENABLE
	TM.A17=	B5		; EXTENDED MEM BIT BA17
	TM.A16=	B4		; EXTENDED MEM BIT BA16
	TM.OFL=	0		; OFF-LINE
	TM..RD=	B1		; READ
	TM..WR=	B2		; WRITE
	TM.WEF=	B1!B2		; WRITE EOF
	TM..SF=	B3		; SPACE FORWARD
	TM..SR=	B3!B1		; SPACE REVERSE
	TM.WEG=	B3!B2		; WRITE WITH EXTENDED GAP
	TM.REW=	B3!B2!B1	; REWIND
	TM..GO=	B0		; GO

TM.BCR:	.BLKW	1		; BYTE COUNT REGISTER

TM.BAR:	.BLKW	1		; BYTE ADDRESS REGISTER

TM.DAT:	.BLKW	1		; DATA BUFFER

TM.RDL:	.BLKW	1		; TU 10 READ LINES