Trailing-Edge
-
PDP-10 Archives
-
decuslib10-01
-
43,50126/cp8ddm.mac
There are no other files named cp8ddm.mac in the archive.
TITLE CP8DDM PDP-8/A, PDP-8/E, 8/I SIMULATOR CPU TABLES
;
;COPYRIGHT 1973, APPLIED DATA RESEARCH, PRINCETON, N.J. 08540
;ALL RIGHTS RESERVED
;
;REVISED 12/18/73 RMS, FOR NXM PROBLEM
;REVISED 3/12/74 MSR, TO ADD PACKED MEMORY OPTION
;REVISED 5/21/75 MSR, TO ADD PDP-8A AND TIMESHARE OPTION
;
T3=15
IFNDEF EAE,< EAE=0>
IFNDEF PACKED,< PACKED=0>
IFNDEF MEM,< MEM=4>
MEMSIZ=MEM*^D1024
IFNDEF OPT2,< OPT2=0>
IFE VM-SIXBIT/PDP8A/,<
IFG MEM-4,< OPT2=1>>
IFNDEF PWR,< PWR=0>
;
EXTERN CPURD, CPUWR, CPURST, NULL, SLPCHK, ADDRNT
EXTERN .FLAGS,.READ,.WRITE
EXTERN .LOADR,.BLDUP,.TRDN,.FETCH
INTERN ITIM,SPC,LDRUCB,SYSLST
INTERN DBR,IBR,IBBR,SR,BSR,OLDPC,PCSAVE,SC
INTERN STM,CPUUCB,CPUDDM,SIO,SLAC,CORE
INTERN TRAPS, .BRSET
IFN VM-SIXBIT/PDP8/,<INTERN EAEMOD,DISABL,GTFF>
INTERN UB,UF,BAT
INTERN RMEM1,RMEM2,WMEM1,WMEM2,WMEM3,WMEM4
INTERN L0,L7750,L7751,L7754,L7755
;
;DDM HEADER....
;
CPUDDM: DDM1 CPU,CPURDB,CPUUCB ;DEVICE HEADER.
DDM1A INIT8,0
DDM2 ^D8,^D15,^D8,^D12 ;ADDRESSES AND FRAMES
DDM3 QADR+QFIX+QBRK,^D12,MEMSIZ
DDM4 CPURD,CPUWR,CPURST,ADDRNT,.BRSET,SLPCHK
CORE=CPUDDM+DNFRM
;
CPUUCB: UCB CPU,0,CPUDDM,NULL,0,QADR+QFIX+QBRK
;
INTERN PCTWDT
PCTWDT=^D15 ;DEFINE WIDTH OF TRACE ADDRESSES
IFE PACKED,<
RMEM1=(SKIPGE MB,@(XR2))
RMEM2=RBNKTB
WMEM1=(SKIPGE @(XR2))
WMEM2=RBNKTB
WMEM3=(HRRM MB,@(XR2))
WMEM4=WBNKTB
DEFINE CBANK(NXMLOC,NN),<
IRP NN<
IFG MEMSIZ-<NN*^D4096>,<BANK0+<NN*^D4096>(MA)>
IFLE MEMSIZ-<NN*^D4096>,<NXMLOC>
>
>
RBNKTB: CBANK REDZRO,<0,1,2,3,4,5,6,7>
WBNKTB: CBANK WRTJNK,<0,1,2,3,4,5,6,7>
L0: POINT 12,BANK0,35
L7750: POINT 12,BANK0+7750,35
L7751: POINT 12,BANK0+7751,35
L7754: POINT 12,BANK0+7754,35
L7755: POINT 12,BANK0+7755,35
.BRSET: MOVE MA,BRKBLK+BFRM ;GET CORE ADDRESS
CAML MA,CORE ;DOES IT EXIST?
POPJ P, ;NO
AOS (P) ;YES, SET UP SKIP RETURN
LDB XR2,[POINT 3,MA,^D23];GET BANK NUMBER
ANDI MA,7777
HLRZ XR3,BRKBLK+BBRK ;GET THE BREAK BITS
JUMPE XR3,.+2 ;ACTIONS ARE ZERO... BREAKS?
MOVSI XR3,400000 ;EITHE, SET FLAG OF 1 IN BIT 0
HLLM XR3,@WBNKTB(XR2) ;STORE BREAK BIT
POPJ P, ;EXIT
>
IFN PACKED,<
RMEM1=(JSP MX,)
RMEM2=GWORD
WMEM1=(JSP MX,)
WMEM2=SWORD
WMEM3=(JSP MX,)
WMEM4=SWORDX
GWORD: CAIGE MA,4000 ;IS BANK DISPLACEMENT GREATER THAN 3777?
SKIPA MB,@RBNKT1(XR2) ;NO
MOVS MB,@RBNKT2(XR2) ;YES
HRRZ MB,MB ;CLEAR OUT UNEEDED JUNK
TRZE MB,400000 ;BREAKPOINT?
JRST (MX) ;YES
JRST 1(MX) ;NO
SWORD: CAIGE MA,4000
JRST SWORDR
HLRZ T3,@RBNKT2(XR2) ;GET WORD
TRNE T3,400000 ;BREAK POINT?
JRST (MX) ;YES
DPB MB,[POINT 12,@WBNKT2(XR2),17];NO, STORE MB
JRST 2(MX)
SWORDR: HRRZ T3,@RBNKT1(XR2)
TRNE T3,400000 ;BREAKPOINT?
JRST (MX) ;YES
DPB MB,[POINT 12,@WBNKT1(XR2),35]
JRST 2(MX)
SWORDX: CAIGE MA,4000
JRST .+3
DPB MB,[POINT 12,@WBNKT2(XR2),17]
JRST (MX)
DPB MB,[POINT 12,@WBNKT1(XR2),35]
JRST (MX)
DEFINE CBANK1(NXMLOC,NN),<
IRP NN<
IFG MEMSIZ-<NN*^D4096>,<BANK0+<NN*^D2048>(MA)>
IFLE MEMSIZ-<NN*^D4096>,<NXMLOC>
>
>
DEFINE CBANK2(NXMLOC,NN),<
IRP NN<
IFG MEMSIZ-<NN*^D4096>,<XWD MA,<BANK0+<<NN-1>*^D2048>>>
IFLE MEMSIZ-<NN*^D4096>,<NXMLOC>
>
>
RBNKT1: CBANK1 REDZRO,<0,1,2,3,4,5,6,7>
RBNKT2: CBANK2 REDZRO,<0,1,2,3,4,5,6,7>
WBNKT1: CBANK1 WRTJNK,<0,1,2,3,4,5,6,7>
WBNKT2: CBANK2 WRTJNK,<0,1,2,3,4,5,6,7>
L0: POINT 12,BANK0,35
L7750: POINT 12,BANK0+7750-4000,17
L7751: POINT 12,BANK0+7751-4000,17
L7754: POINT 12,BANK0+7754-4000,17
L7755: POINT 12,BANK0+7755-4000,17
.BRSET: MOVE MA,BRKBLK+BFRM ;GET THE CORE ADDRESS
CAML MA,CORE ;DOES IT EXIST?
POPJ P, ;NO
AOS (P) ;YES, SET UP SKIP RETURN
LDB XR2,[POINT 3,MA,^D23];GET THE BANK NUMBER
ANDI MA,7777 ;CUT BANK DISPLACEMENT TO 12 BITS
HLRZ XR3,BRKBLK+BBRK ;GET THE BREAK BITS
JUMPE XR3,.+2 ;ACTIONS ARE ZERO...BREAKS?
MOVEI XR3,1 ;EITHER, SET FLAG
CAIGE MA,4000 ;HI OR LOW HALF OF BANK?
JRST .BRSTL ;LOW
DPB XR3,[POINT 1,@WBNKT2(XR2),0];HI, STORE BIT
POPJ P, ;EXIT
.BRSTL: DPB XR3,[POINT 1,@WBNKT1(XR2),18];STORE BIT
POPJ P, ;EXIT
>
;
REDZRO: 0 ;NXM READS HERE
WRTJNK: 0 ;NXM WRITES HERE
;
ITIM: Z ;INTERVAL TIMER
Z ;TIME OF LAST UPDATE
XXCORE: MEMSIZ
STM: Z ;SAVE TIMER
SIO: Z ;SAVED FLAGS
SIR: Z ;IR AND OTHER SAVED REGISTERS
SPC: Z ;PC
SLAC: Z ;L-AC
SMQ: Z ;MQ
SMA: Z ;MA
SMB: Z ;MB
Z ;SAVED XRS
Z
Z
;
IBR: Z ;IBR AND OTHER REAL REGISTERS
DBR: Z
IBBR: Z
BSR: Z
SR: Z
OLDPC: Z
SC: Z
PCSAVE: Z
TRAPS: Z
UB: Z
UF: Z
BAT: Z
IFN VM-SIXBIT/PDP8/,<
DISABL: Z
GTFF: Z
EAEMOD: Z
>
;
CPURDB: RDB AC,SLAC,12 ;AC,SAVED.
IFE VM-SIXBIT/PDP8E/,<RDB MQ,SMQ,12 ;MQ, SAVED.>
IFE VM-SIXBIT/PDP8A/,<RDB MQ,SMQ,12>
RDB MA,SMA,12,P
RDB MB,SMB,12,P
RDB IR,SIR,3,P
CPUPC: RDB PC,SPC,15
RDB SR,SR,12
RDB IBBR,IBBR,3
RDB DBR,DBR,3
RDB OLDPC,OLDPC,15,P
RDB BSR,BSR,7
DRDB TM,STM,36,P
DRDB ITM,ITIM,36 ;INTERVAL TIMER
RDB STAT,SIO,27
IFN EAE,<
IFE VM-SIXBIT/PDP8/,<RDB MQ,SMQ,12>
RDB SC,SC,5 ;EAE SHIFT COUNTER
IFE VM-SIXBIT/PDP8E/,<
FLG EAEMDE,EAEMOD,35 ;EAE MODE FLOP
>
>
DRDB CORE,XXCORE,15,P
;
FLG L,SLAC,^D23
FLG LINK,SLAC,^D23
FLG ION,SIO,1
IFG MEM-4,<
FLG UINT,SIO,9
FLG UF,UF,0
FLG UB,UB,0>
IFN PWR,< FLG PWR,SIO,27>
IFN OPT2,< FLG PWR,SIO,27
FLG BAT,BAT,0>
FLG SINGLE,.FLAGS,1
FLG SI,.FLAGS,1 ;SIN INST TRAP, REG AND ABBREVIATION
FLG ILLEG,TRAPS,0
;
RBLK IBR,SPC,3,,8,23
Z
;MEMORY INITIALIZATION AND ARRAY
;
INIT8: MOVE XR1,[XWD BANK0,BANK0+1] ;CLEAR ALL OF CORE.
SETZM BANK0
IFE PACKED,<BLT XR1,BANK0-1+MEMSIZ>
IFN PACKED,<BLT XR1,BANK0-1+<MEMSIZ/2>>
POPJ P,
;
BANK0:
IFE PACKED,<BLOCK MEMSIZ>
IFN PACKED,<BLOCK MEMSIZ/2>
;
SYSLST: SIXBIT /PDP8/ ;SYSTEM LIST: SYSTEM NAME
Z ,.FETCH ;ENTRY TO FETCH PHASE
Z ,CPUPC ;PC RDB
XWD .LOADR,LDRUCB ;SYSTEM LOADER INFORMATION.
Z ,.BLDUP ;BUILD UP VM AC'S
Z ,.TRDN ;TEAR DOWN VM AC'S.
DDM3 QADR+QATBL+QRD,^D36,0
Z,STM
;
LDRUCB: UCB LDR,0,SYSLST,NULL,0,QADR+QATBL+QRD
END