Trailing-Edge
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PDP-10 Archives
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decuslib10-08
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43,50463/04/vilink.mic
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.ass dskb dsk
.copy dskb:libsim.rel=sys:libsim.rel[1,4]
.r link
*mided.MAP/MAP
*/symseg:none ;Avoid local symbols
*midedb,vdccou,sys:simlib[1,4]/include:(ocsp)
*sys:libsim[1,4]/include:(run,isoltr)
*/segment:high REL:simhgh ;Must be first in high segment
*/segment:high termty,sscan,mmista,mided1,mided2,mided3
*/segment:high vtmcur,vtsynk,vtisng
*/segment:high sys:libsim[1,4]/search ;Place any libsim modules here
*/segment:high sys:simlib[1,4]/search,rel:helper/search
*REL:MAKSHR
*/g
.start
; version 401=4A, 115=(115), 137=where to deposit
.d 401 221 137
.ssave DSKD:VIDED
.del dskb:libsim.rel
.deassign
.prot <405> DSKD:VIDED.EXE
.noerror
.teco vilink.mic
*n
*.d ^ED^ED^ED ^[i(^[3ci)^[rkiun
*^[-s(^[i000^[1ximi
*FSun^[u4^[6r1ximi
*FSu4^[u3^[5r1ximi
*fsu3^[u2^[4r1ximi
*fsu2^[u1^[3r1ximi^[^[
*<6-Q1;Qn+2un^[1;>
*<76-Q2;Qn+20un^[1;>
*<776-Q3;Qn+200un^[1;>
*<7776-Q4;Qn+2000un^[1;>
*-s(^[-d^[%n\^[^[ki 137
*^[ex^[^[