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EDIT=0
VERSION=1

DEFINE	NAME	(EDT,VER),<
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TITLE	MCODE3 	DX20 MICRO-DIAGNOSTIC OF THE CHANNEL BUS INTERFACE - PART 2  VERSION EDT'.'VER





>

NAME	\EDIT,\VERSION




	COMMENT	$

	MCODE3 IS THE 2ND PART OF A 2 PART MICRODIAGNOSTIC OF THE
CHANNEL BUS INTERFACE.  IT IS MAINLY A LOGIC TEST (AS OPPOSED TO A FUNCTIONAL
TEST) WHICH DOES THE FOLLOWING:

	(1)   TESTS THE SCRATCH PAD LOGIC - THE COUNTER AND THE RAM,
	(2)   TESTS THE PARITY CHECKING AND GENERATING LOGIC,
	(3)   TESTS THE CONTROL UNIT LOGIC -
		(A) THE HANDSHAKING LOGIC,
		(B) THE RESET LOGIC,
		(C) THE CONTROL UNIT SELECT LOGIC,
		(D) THE CONTROL UNIT ADDRESS COMPARE LOGIC. THIS REPORTS
			TO THE HOST THE ADDRESSES TO WHICH THE DX20 IS
			SETUP TO RESPOND.

IN ORDER TO SIMULATE THE ACTIONS OF A DEVICE ON THE CHANNEL BUS, THE LOOP
BACK FEATURE IS USED.  THIS ALLOWS THE LOOPING BACK OF TAG OUT AND BUS OUT
LINES INTO TAG IN AND BUS IN LINES, RESPECTIVELY.  THE BUS OUT LINES ARE
LOOPED BACK COMPLEMENTED.

WHEN THE DX20 IS OPERATING AS A CONTROL UNIT, IT IS REQUIRED THAT THE DIAGNOSTIC
NOT ALLOW ANY SIGNALS TO PROPAGATE ONTO THE TAG OUT OR BUS OUT LINES.  TO
INSURE THIS, THE "ON LINE" BIT IS KEPT CLEARED.  THIS DISABLES THE DRIVERS.
NOTE: ALL DOCUMENTATION USES THE TERM "SET" TO DENOTE THE ASSERTION OF A
	SIGNAL AND "CLEAR" TO DENOTE ITS NEGATION, WHETHER OR NOT THE SIGNAL
	IS ASSERTED HIGH OR LOW.

$
	RPTCNT=	100			;SET REPEAT COUNT TO 100 TIMES

	SUBTTL	CHANNEL BUS INTERFACE REGISTER BIT DEFINITIONS

;DEFINE CHANNEL BUS INTERFACE REGISTERS

CSR0=0				;CONTROL AND STATUS REGISTER 0 (READ/WRITE CLEAR)
CSR1=1				;CONTROL AND STATUS REGISTER 1 (READ/WRITE)
TOR0=2				;TAG OUT REGISTER 0 (READ/WRITE)
TOR1=3				;TAG OUT REGISTER 1 (READ/WRITE)
TAGIN0=4			;TAG IN REGISTER 0 (READ ONLY)
TAGIN1=5			;TAG IN REGISTER 1 (READ ONLY BITS 7-4)
SPADR=5				;SCRATCH PAD ADDRESS REGISTER (READ/WRITE BITS 3-0)
DRLO=6				;DATA REGISTER 0 (READ ONLY)
CBILO=7			;BUS IN REGISTER 0 (READ ONLY)
SPDALO=10			;SCRATCH PAD DATA REGISTER 0 (WRITE ONLY)
BORLO=11				;BUS OUT REGISTER 0 (WRITE ONLY)
DRHI=12				;DATA REGISTER 1 (READ ONLY)
CBIHI=13			;BUS IN REGISTER 1 (READ ONLY)
SPDAHI=14			;SCRATCH PAD DATA REGISTER 1 (WRITE ONLY)
BORHI=15				;BUS OUT REGISTER 1 (WRITE ONLY)
CUSTAT=16			;CONTROL UNIT RESET STATUS REGISTER (WRITE ONLY)

;WRITEABLE PULSES DEFINITIONS

CLSLRQ=4			;CLEAR SLVE REQ PULSE
CLKDRL=6			;CLOCK DR REG 0

;REGISTER BIT DEFINITIONS

;CSR0

;READ ONLY BITS

EXFER=1B28			;END XFER
TIMOUT=1B29			;TIME OUT FLAG
DPPE=1B30			;DP PE FLAG
UBPE=1B31			;UB PE FLAG
MKPE=1B32			;MK PE FLAG
BUS1PE=1B33			;BUS1 PE FLAG
BUS0PE=1B34			;BUS0 PE FLAG
SLVSEL=1B35			;SLVE SEL

;WRITE ONLY BITS

CLRFLG=1B34			;CLEARS ALL FLAGS
CSLVSL=1B35			;CLEARS "SLVE SEL"

;CSR1

SPEN=1B28			;SP ENABLE
DIHISP=1B29			;DIAG HIGH SPEED
EVPAR=1B30			;EVEN PAR
EXTBUS=1B31			;EXTENDED BUS
MOD360=1B32			;360 MODE
LOOPEN=1B33			;LOOP ENABLE
ONLINE=1B34			;ON LINE
CHANL=1B35			;CHANNEL MODE

;TOR0

SRVOUT=1B28			;TOR SRV OUT
CLKOUT=1B29			;TOR CLK OUT
MTROUT=1B30			;TOR MTR OUT
ADROUT=1B31			;TOR ADR OUT
HLDOUT=1B32			;TOR HLD OUT
TMREN=1B33			;TIMER INTERRUPT ENABLE
SELOUT=1B34			;TOR SEL OUT
CMDOUT=1B35			;TOR CMD OUT

;TOR1

OPLOUT=1B28			;TOR OPL OUT
CURSEN=1B29			;ENABLE CU RESET
SUPOUT=1B30			;TOR SUP OUT
DATOUT=1B31			;TOR DAT OUT
DISACK=1B32			;DIAG SLVE ACK
DIMUX=1B33			;DIAG MUX BIT
TODOUT=1B34			;TO DAT OUT
TOSOUT=1B35			;TO SRV OUT

;TAGIN0

OPLIN=1B28			;TI OPL IN
MK0IN=1B29			;TI MK 0 IN
MK1IN=1B30			;TI MK 1 IN
ADRIN=1B31			;TI ADR IN
TOHOUT=1B32			;TO HLD OUT
MTRIN=1B33			;TI MTR IN
SELIN=1B34			;TI SEL IN
STAIN=1B35			;TI STA IN

;TAGIN1

SRVIN=1B28			;TI SRV IN
DISIN=1B29			;TI DIS IN
REQIN=1B30			;TI REQ IN
DATIN=1B31			;TI DAT IN

;SPADR

SPABTS=17B35			;SP ADDR BITS

;CUSTAT

SELRST=1B33			;SEL RESET
SYSRST=1B34			;SYS RESET
HALTIO=1B35			;HALT I/O

;LOOPED BACK BIT DEFINITIONS

;TOR0

OPLINL=1B28			;OPL IN
MK0INL=1B29			;MK 0 IN
MK1INL=1B30			;MK 1 IN
ADRINL=1B31			;ADR IN
HLDOTL=1B32			;TO HLD OUT
SELINL=1B34			;SEL IN
STAINL=1B35			;STA IN

;TOR1

SRVINL=1B28			;SRV IN
DISINL=1B29			;DIS IN
REQINL=1B30			;REQ IN
DATINL=1B31			;DAT IN

;SOME DATA PATH DEFINITIONS

HSDPIN=13			;HS DP INIT

;ASSEMBLY CONTROL SWITCH

CUADRS=1			;ALLOWS ASSEMBLY OF CU ADDRESS PRINT LOGIC