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MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 1
MCOD5T MAC 17-Oct-88 14:29 DATA PATH TEST - PART 2
1 XLIST
2 LIST
3
4
5
6
7 TITLE MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1
8
9
10
11
12
13 ^
14
15
16
17
18 COMMENT $
19
20 MCODE5 IS THE 2ND PART OF A 4 PART MICRODIAGNOSTIC OF THE HIGH SPEED
21 DATA PATH. IT DOES THE FOLLOWING:
22
23 (1) TESTS THE PORTION OF THE FORMATTER CONTROL LOGIC NOT TESTED
24 BY MCODE3. SPECIFICALLY, THAT LOGIC CONCERNING THE BYTE
25 COUNTER AND THE DATA PATH PARITY DETECTION.
26 (2) TESTS THE GENERATION OF "SLVE REQ" AND "MSTR REQ" ON THE
27 CHANNEL BUS AND MASSBUS INTERFACES, RESPECTIVELY.
28 (3) TESTS THE "DATA PATH" AND THE FORMATTING THROUGH THAT PATH.
29 FOR EXAMPLE, SHIFTING AND MASKING THROUGH THE MUX AND DEMUX.
30
31 THE MAJORITY OF THE TESTS RELY ON THE PROPER OPERATION OF THE MASSBUS
32 AND/OR CHANNEL BUS INTERFACES.
33
34 ALL TESTING REQUIRING CLOCKING IS DONE IN THE SINGLE STEPPING MODE SO AS
35 TO ALLOW EXAMINATION OF SIGNAL STATES DURING THE TEST.
36
37 NOTE: ALL DOCUMENTATION USES THE TERM "SET" TO DENOTE THE ASSERTION OF A
38 SIGNAL AND "CLEAR" TO DENOTE ITS NEGATION.
39
40 $
41 000100 RPTCNT= 100 ;SET REPEAT COUNT TO 100 TIMES
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 2
MCOD5T MAC 17-Oct-88 14:29 DATA PATH BIT REGISTER DEFINITIONS
42 SUBTTL DATA PATH BIT REGISTER DEFINITIONS
43
44 ;DEFINE THE DATA PATH REGISTERS
45
46 000000 REG0=0 ;REGISTER 0 (READ ONLY)
47 000001 REG1=1
48 000002 REG2=2
49 000003 REG3=3 ;READ ONLY
50 000004 MCLO=4 ;MASSBUS COUNTER BITS 7-0
51 000005 MCHI=5 ;MASSBUSS COUNTER BITS 15-8
52 000006 BCLO=6 ;BYTE COUNTER BITS 7-0
53 000007 BCHI=7 ;BYTE COUNTER BITS 15-8
54 000010 DFRMAD=10 ;DF ROM ADDRESS BITS 7-0
55 000011 RMDALO=11 ;DF ROM DATA BITS 7-0 (READ ONLY)
56 000012 RMDAHI=12 ;DF ROM DATA BITS 15-8 (READ ONLY)
57 000013 ARLO=13 ;ASSEMBLY REGISTER BITS 7-0
58 000014 ARHI=14 ;ASSEMBLY REGISTER BITS 15-8
59 000015 REG15=15 ;READ ONLY
60 000016 REG16=16 ;READ ONLY
61 000017 REG17=17 ;READ ONLY
62
63 000011 LDRMDA=11 ;LOAD ROM DATA PULSE (WRITE ONLY)
64 000012 CLKPLS=12 ;BASE CLOCK PULSE (WRITE ONLY)
65 000013 HSDPIN=13 ;HS DP INIT PULSE (WRITE ONLY)
66 000014 SETRUN=14 ;SET RUN PULSE (WRITE ONLY)
67
68 ;REGISTER 0
69
70 000001 UBPEFG=1B35 ;MICROBUS PARITY ERROR FLAG
71 000002 DPPEFG=1B34 ;DATA PATH PARITY ERROR FLAG
72 000004 BCOVF=1B33 ;BYTE COUNT OVERFLOW FLAG
73 000010 MCOVF=1B32 ;MASSBUS COUNTER OVERFLOW FLAG
74
75 ;REGISTER 1
76
77 000001 DXHISP=1B35 ;DX HIGH SPEED
78 000002 BCLKEN=1B34 ;BASE CLOCK ENABLE
79 000004 DSLVRQ=1B33 ;DIAGNOSTIC SLAVE REQUEST
80 000010 DMSTRQ=1B32 ;DIAGNOSTIC MASTER REQUEST
81 000020 SLVACK=1B31 ;SLAVE ACK
82 000040 MSTACK=1B30 ;MASTER ACK
83 000100 SLVRQ=1B29 ;SLAVE REQUEST
84 000200 MSTRQ=1B28 ;MASTER REQUEST
85
86 ;REGISTER 2
87
88 000001 RMADR8=1B35 ;ROM ADDR BIT 8
89 000002 SEBCOV=1B34 ;SLVE END ON BC OVFL EN
90 000004 MEMCOV=1B33 ;MSTR END ON MC OVFL EN
91 000010 MEONFE=1B32 ;MSTR END ON FMTR END EN
92 000100 SRHDOF=1B29 ;SLVE REQ HLDOFF
93 000200 MRHDOF=1B28 ;MASTER REQ HLDOFF
94
95 ;REGISTER 3
96
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 2-1
MCOD5T MAC 17-Oct-88 14:29 DATA PATH BIT REGISTER DEFINITIONS
97 000002 NSEXFR=1B34 ;NOT SLVE END XFER
98 000004 NMEXFR=1B33 ;NOT MSTR END XFER
99 000010 NFEXFR=1B32 ;NOT FMTR END XFER
100
101 ;REGISTER 4 (MASSBUS COUNTER 7-0 - MCLO)
102
103 000377 MCLOBT=377B35 ;BITS 7-0 OF MASSBUS COUNTER
104
105 ;REGISTER 5 (MASSBUS COUNTER 15-8 - MCHI)
106
107 000377 MCHIBT=377B35 ;BITS 15-8 OF MASSBUS COUNTER
108
109 ;REGISTER 6 (BYTE COUNTER 7-0 - BCLO)
110
111 000377 BCLOBT=377B35 ;BITS 7-0 OF BYTE COUNTER
112
113 ;REGISTER 7 (BYTE COUNTER 15-8 - BCHI)
114
115 000377 BCHIBT=377B35 ;BITS 15-8 OF BYTE COUNTER
116
117 ;REGISTER 10 (DF ROM ADR 7-0 - DFRMAD)
118
119 000377 RMADLO=377B35 ;BITS 7-0 OF DF ROM ADDRESS
120
121 ;REGISTER 11 (DF ROM DATA 7-0 - RMDALO)
122
123 000377 RDLOBT=377B35 ;BITS 7-0 OF DF ROM DATA
124
125 ;REGISTER 12 (DF ROM DATA 15-8 - RMDAHI)
126
127 000377 RDLOBT=377B35 ;BITS 15-8 OF DF ROM DATA
128
129 ;REGISTER 13 (ASSEMBLY REGISTER 7-0 - ARLO)
130
131 000377 ARLOBT=377B35 ;BITS 7-0 OF ASSEMBLY REGISTER
132
133 ;REGISTER 14 (ASSEMBLY REGISTER 15-8 - ARHI)
134
135 000377 ARHIBT=377B35 ;BITS 15-8 OF ASSEMBLY REGISTER
136
137 ;REGISTER 15
138
139 000003 AR1716=3B35 ;BITS 17-16 OF ASSEMBLY REGISTER
140 000004 NCLRAR=1B33 ;NOT CLEAR ASSEMBLY REG
141 000010 NENMDM=1B32 ;NOT ENABLE MUX/DEMUX
142 000020 LDCB=1B31 ;LOAD CHANNEL BUFFER
143 000040 LDSB=1B30 ;LOAD SILO BUFFER
144 000100 EXTRUN=1B29 ;EXTEND RUN
145
146 ;REGISTER 16
147
148 000001 SLVEPE=1B35 ;SLVE PARITY ERROR
149 000002 MSTRPE=1B34 ;MSTR PARITY ERROR
150 000004 NCLRN=1B33 ;NOT CLR RUN
151 000010 NOTRUN=1B32 ;NOT RUN
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 2-2
MCOD5T MAC 17-Oct-88 14:29 DATA PATH BIT REGISTER DEFINITIONS
152 000020 DFCPH0=1B31 ;DF CLK PH 0
153 000040 DFCPH1=1B30 ;DF CLK PH 1
154 000100 NRNDAT=1B29 ;NOT RUN DATA
155
156 ;REGISTER 17
157
158 000001 SLVRDY=1B35 ;SLAVE RDY
159 000002 SLRDY1=1B34 ;SLAVE RDY DLY 1
160 000004 SLRDY2=1B33 ;SLAVE RDY DLY 2
161 000010 MSTRDY=1B32 ;MASTER RDY
162 000020 MSRDY1=1B31 ;MASTER RDY DLY 1
163 000040 MSRDY2=1B30 ;MASTER RDY DLY 2
164
165 ;DEFINE SOME CHANNEL BUS INTERFACE REGISTERS WHICH ARE REFERENCED
166
167 000000 CSR0=0
168 000001 CSR1=1
169 000002 TOR0=2
170 000003 TOR1=3
171 000006 DRLO=6
172 000007 CBILO=7
173 000011 BORLO=11
174 000006 CLKDRL=6 ;WRITE TO REG 6 CLOCKS DRLO REG
175 000004 SLAK25=4 ;WRITE TO REG 4 GENERATES "SLVE ACK DL25"
176
177 ;DEFINE SOME CHANNEL BUS INTERFACE REGISTER BITS WHICH ARE USED
178
179 000001 CHANL=1B35 ;CHANNEL MODE BIT
180 000004 LOOPEN=1B33 ;LOOP ENABLE BIT
181 000010 DISACK=1B32 ;DIAG SLVE ACK
182 000040 EVPAR=1B30 ;EVEN PARITY FORCED
183 000001 STAINL=1B35 ;STA IN LOOPED BACK
184 000200 SRVINL=1B28 ;SRV IN LOOPED BACK
185 000002 CLRFLG=1B34 ;CLEARS REG 0 FLAGS
186
187 ;ROM ADDRESSES WITH DIAGNOSTIC DATA
188
189 000340 ZERADR=340 ;ADDR OF 1ST ROM LOC AFTER OPERATIONAL PROGRAMS
190 000310 DIAGAD=310 ;ADDR OF 1ST DIAG ROM LOC
191
192 000310 DMXSHF=310
193 000314 MUXSHF=314
194
195 000320 ZEROS=320
196 000321 ONES=321
197
198 000322 CC0=322
199 000327 CC1=MSK0
200 000323 CC2=323
201 000324 CC4=324
202 000325 CC5=325
203 000326 CC8=326
204
205 000327 MSK0=327
206 000330 MSK1=330
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 2-3
MCOD5T MAC 17-Oct-88 14:29 DATA PATH BIT REGISTER DEFINITIONS
207 000331 MSK2=331
208 000332 MSK3=332
209 000333 MSK4=333
210 000334 MSK5=334
211 000335 MSK6=335
212 000336 MSK7=336
213 000337 MSK8=337
214 000360 MSK1S=MSHF0
215
216 000340 DSHF0=340
217 000341 DSHF1=341
218 000342 DSHF2=342
219 000343 DSHF3=343
220 000344 DSHF4=344
221 000345 DSHF5=345
222 000346 DSHF6=346
223 000347 DSHF7=347
224 000350 DSHF10=350
225 000351 DSHF11=351
226 000352 DSHF12=352
227 000353 DSHF13=353
228 000354 DSHF14=354
229 000355 DSHF15=355
230 000356 DSHF16=356
231 000357 DSHF17=357
232
233 000360 MSHF0=360
234 000361 MSHF1=361
235 000362 MSHF2=362
236 000363 MSHF3=363
237 000364 MSHF4=364
238 000365 MSHF5=365
239 000366 MSHF6=366
240 000367 MSHF7=367
241 000370 MSHF10=370
242 000371 MSHF11=371
243 000372 MSHF12=372
244 000373 MSHF13=373
245 000374 MSHF14=374
246 000375 MSHF15=375
247 000376 MSHF16=376
248 000377 MSHF17=377
249
250 ;OPERATIONAL ROM PROGRAMS
251
252 000000 WINCM=0
253 000010 RINCMF=10
254 000027 RINCR1=27
255 000022 RINCR2=22
256 000021 RINCR3=21
257 000020 RINCR4=20
258 000030 WCDMP=30
259 000040 RCDMPF=40
260 000057 RCDMR1=57
261 000053 RCDMR2=53
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 2-4
MCOD5T MAC 17-Oct-88 14:29 DATA PATH BIT REGISTER DEFINITIONS
262 000052 RCDMR3=52
263 000051 RCDMR4=51
264 000050 RCDMR5=50
265 000060 WHIDN=60
266 000100 RHIDNF=100
267 000137 RHIDR1=137
268 000131 RHIDR2=131
269 000130 RHIDR3=130
270 000127 RHIDR4=127
271 000136 RHIDR5=136
272 000123 RHIDR6=123
273 000122 RHIDR7=122
274 000121 RHIDR8=121
275 000120 RHIDR9=120
276 000140 WASC6=140
277 000150 RASC6F=150
278 000177 RAS6R1=177
279 000176 RAS6R2=176
280 000163 RAS6R3=163
281 000162 RAS6R4=162
282 000161 RAS6R5=161
283 000160 RAS6R6=160
284 000200 WAS71=200
285 000210 RAS71F=210
286 000227 RA71R1=227
287 000223 RA71R2=223
288 000222 RA71R3=222
289 000221 RA71R4=221
290 000220 RA71R5=220
291 000230 WAS72=230
292 000240 RAS72F=240
293 000257 RA72R1=257
294 000253 RA72R2=253
295 000252 RA72R3=252
296 000251 RA72R4=251
297 000250 RA72R5=250
298 000260 WEM1=260
299 000264 REM1F=264
300 000271 REM1R1=271
301 000270 REM1R2=270
302 000274 WEM2=274
303 000300 REM2F=300
304 000305 REM2R1=305
305 000304 REM2R2=304
306 000310 WCOBOL=310
307 000320 RCOBLF=320
308 000337 RCBLR1=337
309 000332 RCBLR2=332
310 000331 RCBLR3=331
311 000330 RCBLR4=330
312
313 ;DEFINE RHDATA IN ORDER TO BE ABLE TO USE WRITE, READ, AND READB MACROS.
314 000001 RHDATA=1
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 1
MCERR MAC 17-Oct-88 14:28 DATA PATH BIT REGISTER DEFINITIONS
315 IF2 <PRINTX STARTING BINARY FILE>
316 SEARCH DX20CA ;READ THE CROSS ASSEMBLER
317
318 ;MASSBUS REGISTER BIT DEFINITIONS
319
320 ;STATUS & CONTROL REGISTER 1
321
322 000000 MPSCR0== 0 ;REGISTER NAME
323 000001 RUN== 1 ;RUN LINE FROM RH20
324 000002 GO== 2 ;GO BIT
325 000174 FN== 174 ;FUNCTION CODE
326 000004 F0== 4 ;FUNCTION BIT 0
327 000010 F1== 10 ;FUNCTION BIT 1
328 000020 F2== 20 ;FUNCTION BIT 2
329 000040 F3== 40 ;FUNCTION BIT 3
330 000100 F4== 100 ;FUNCTION BIT 4
331 000200 WCLK== 200 ;WRITE CLOCK LINE FROM RH20
332
333 ;STATUS AND CONTROL REGISTER 2
334
335 000001 MPSCR1== 1 ;REGISTER NAME
336 000001 DONE== 1 ;DATA TRANSFER DONE (READ)
337 000001 EBL== 1 ;SET EBL (WRITE)
338 000002 EXC== 2 ;EXCEPTION LINE FROM RH20 (READ)
339 000002 CLRGO== 2 ;SET TO CLEAR GO (WRITE)
340 000004 CMPERR== 4 ;COMPOSITE ERROR FLAG (READ)
341 000004 START== 4 ;START A DATA TRANSFER (WRITE)
342 000010 DTD== 10 ;DATA TO DEVICE
343 000020 OCC== 20 ;OCCUPIED
344 000040 ILF== 40 ;ILLEGAL FUNCTION
345 000100 MPERR== 100 ;MICRO-PROCESSOR DETECTED ERROR FLAG
346 000200 ATA== 200 ;ATTENTION
347
348 ;ERROR CODE REGISTER
349
350 000002 MPECR== 2 ;REGISTER NAME
351
352 ;DRIVE TYPE REGISTER
353
354 000003 MPDTR== 3 ;REGISTER NAME
355
356 ;HARDWARE VERSION REGISTER
357
358 000004 MPHVR== 4 ;REGISTER NAME
359
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 2
MCERR MAC 17-Oct-88 14:28 DATA PATH BIT REGISTER DEFINITIONS
360 ;DATA BUFFER REGISTER 0
361
362 000005 MPDB0== 5 ;REGISTER NAME
363
364 ;DATA BUFFER REGISTER 1
365
366 000006 MPDB1== 6 ;REGISTER NAME
367
368 ;DATA BUFFER REGISTER 2
369
370 000007 MPDB2== 7 ;REGISTER NAME
371
372 000003 DB== 3 ;DATA BUFFER BITS 16 AND 17
373 000004 DBPAR== 4 ;PARITY BIT
374 000010 DBPARE== 10 ;PARITY ERROR (READ)
375 000020 DBEVEN== 20 ;DATA BUFFER EVEN PARITY CONTROL
376
377 ;GENERAL PURPOSE REGISTERS
378
379 000010 MPGP0==10 ;REGISTER NAMES
380 000011 MPGP1==11
381 000012 MPGP2==12
382 000013 MPGP3==13
383 000014 MPGP4==14
384 000015 MPGP5==15
385 000016 MPGP6==16
386 000017 MPGP7==17
387 000020 MPGP10==20
388 000021 MPGP11==21
389 000022 MPGP12==22
390 000023 MPGP13==23
391 000024 MPGP14==24
392 000025 MPGP15==25
393 000026 MPGP16==26
394 000027 MPGP17==27
395
396 ;MP STATUS REGISTER
397
398 000036 MPSTAT==36 ;REGISTER NAME
399 000001 INT0== 1 ;INTERRUPT LINE 0
400 000002 INT1== 2 ;INTERRUPT LINE 1
401 000004 INT2== 4 ;INTERRUPT LINE 2
402 000010 INT3== 10 ;INTERRUPT LINE 3
403 000020 C== 20 ;CARRY BIT
404 000040 Z== 40 ;ZERO BIT
405
406 ;I/O BANK SELECT REGISTER
407
408 000037 IOSEL==37 ;REGISTER NAME
409 000007 INADR== 7 ;INPUT BANK ADDRESS
410 000070 OUTADR== 70 ;OUTPUT BANK ADDRESS
411 000100 SPRES== 100 ;STACK POINTER RESET
412 000200 INIT== 200 ;INITIALIZE
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 3
MCERR MAC 17-Oct-88 14:28 DATA PATH BIT REGISTER DEFINITIONS
413 ;THE FOLLOWING AC'S ARE USED BY THE ERROR HANDLER
414
415 ; AC7 FLAG REGISTER
416 ; AC6 REPEAT COUNTER
417 ; AC5 SAVE OF BR (DURING CALL ONLY)
418 ; AC4 SAVE OF I/O SELECT REGISTER (DURING CALL ONLY)
419 ; AC1 CORRECT DATA FOR ERRORA CALL
420 ; AC0 ACTUAL DATA FOR ERRORA AND ERRORM CALLS
421
422 ;FLAG REGISTER BITS
423
424 ; BIT 7 ERROR LOOP
425 ; BIT 6 ERROR DETECTED
426 ; BIT 5 RELIABILITY MODE
427 ; 4 - 0 LAST ERROR NUMBER
428
429 777777 777777 %TNUM== -1 ;SET TEST NUMBER TO -1 SO ENTIRE DRIVE REGISTER
430
431 000000 %REQ==0
432 000001 IFDEF RHDATA,<%REQ==1>
433 IFDEF CUADRS,<%REQ==1>
434 ;IS LOADED WITH TEST NUMBER ON FIRST TEST
435
436 DEFINE DEFTST(PROG),<
437 DEFINE TEST(E,NAME,X<;*>),<
438
439 LALL
440 X'**********************************************************************
441 X PROG * TEST E * NAME
442 X'**********************************************************************
443 SALL
444
445 IFN <^D'E^!%TNUM>&177400,<
446 IFG %TNUM,<DATI IOSEL,AC6 ;;SAVE THE IOSEL REG>
447 LDBR 11 ;;GET DEVICE CODE FOR MASSBUS INTERFACE
448 MOVB IOSEL ;;LOAD INTO I/O SELECT REGISTER
449 LDBR ^D'E_-8 ;;GET HIGH ORDER BITS OF TEST NUMBER
450 MOVB MPGP1 ;;LOAD INTO MASSBUS REG 20
451 IFG %TNUM,< MOV AC6,BR ;;GET SAVED IOSEL REG
452 MOVB IOSEL ;;RESTORE IT>
453 >
454 LDBR ^D'E&377 ;;GET LOW ORDER BITS OF TEST NUMBER
455 GOINK TESTI ;;GO INITIALIZE TEST
456 %TNUM==^D'E ;;REMEMBER TEST NUMBER
457 %EMES==0 ;;CLEAR ERROR MESSAGE NUMBER
458 TST==TST'E ;;REMEMBER TEST PC
459 LALL
460
461 TST'E: SALL
462 >>
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 4
MCERR MAC 17-Oct-88 14:28 DATA PATH BIT REGISTER DEFINITIONS
463 000200 PNT==200 ;ADDITIONAL PRINT ROUTINE REQUEST FLAG
464 ;ERROR PRINT ROUTINE NUMBER MUST BE IN DXGP3
465
466 DEFINE ERRMAC(ADR,LADR,PRTN,COR),<
467 GOINK ERRSET ;;GO SET ERROR DETECTED FLAG
468 LPADR==ADR ;;REMEMBER ERROR LOOP ADDRESS
469 CORF==<PRTN&PNT>!COR ;;REMEMBER IF CORRECT AND ACTUAL DATA
470 LALL
471
472 ERLOOP LADR ;;IF ERROR, LOOP TO LADR
473 >
474
475 DEFINE ERROR(LADR,MES1,MES2,PRTN<0>),<ERRMAC ERLP,LADR,PRTN,0>
476
477 DEFINE ERRORM(LADR,MES1,MES2,PRTN<0>),<ERRMAC ERLPM,LADR,PRTN,100>
478
479 DEFINE ERRORA(LADR,MES1,MES2,PRTN<0>),<ERRMAC ERLPA,LADR,PRTN,100>
480
481 DEFINE ERRORD(LADR,MES1,MES2,PRTN<0>),<ERRMAC ERLPD,LADR,PRTN,40>
482
483 DEFINE ERLOOP(ADR),<SALL
484 IFN %EMES&<^-37>,<IF2 <
485 LALL
486
487 PRINTX ?TOO MANY ERROR MESSAGES IN ONE TEST
488 SALL
489 >>
490 LDBR CORF!%EMES ;;LOAD MESSAGE NUMBER
491 GOINK LPADR ;;GO TO ERROR HANDLER
492 JMPZ ADR ;;LOOP IF Z IS SET
493 %EMES==%EMES+1 ;;UPDATE THE MESSAGE NUMBER
494 >
495
496 DEFINE REPEAT(RADR),<
497 GOINK REPTU ;;GO TO REPEAT ROUTINE
498 JMPZ RADR ;;REPEAT IF Z IS SET
499 >
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 5
MCERR MAC 17-Oct-88 14:28 DATA PATH BIT REGISTER DEFINITIONS
500 IFDEF RHDATA,<
501 DEFINE WRITE,<GOINK SETWRT ;;CALL ROUTINE TO SET UP RH20>
502 DEFINE READ,<GOINK SETRD ;;CALL ROUTINE TO SET UP RH20>
503 DEFINE READB,<GOINK SETRDB ;;CALL ROUTINE TO SET UP RH20>
504
505 DEFINE CHKRH(LADR,PRTN,CODE),<
506 LDBR <PRTN&PNT>!%EMES!CODE ;;SET UP CODE FOR EC REGISTER
507 GOINK CKTRM ;;CALL HOST TO CHECK TERMINATION OF RH20
508 LALL
509
510 ERRLOP LADR ;;IF ERROR, LOOP TO LADR
511 %EMES==%EMES+1
512 >
513 DEFINE CHKTRM(LADR,MES1,MES2,PRTN<0>),<CHKRH LADR,PRTN,40>
514 DEFINE CHKERR(LADR,MES1,MES2,PRTN<0>),<CHKRH LADR,PRTN,140>
515
516 DEFINE ERRLOP(LADR),<SALL
517 JMPZ LADR ;;IF ERROR, LOOP TO LADR
518 >
519 >
520 IFDEF CUADRS,<
521 DEFINE SNDADR,<GOINK SENDAD ;;CALL ROUTINE TO SEND CU ADDRESSES>
522 >
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 6
MCERR MAC 17-Oct-88 14:28 DATA PATH BIT REGISTER DEFINITIONS
523 000000 %ADRH==0 ;;CLEAR HIGH ADDRESS REFERENCE FLAG
524
525 DEFINE GOINK(ADR),<
526 IFE .&<^-1777>,<
527 JMPSUB ADR ;;GO TO ADDRESS IN LOW 1K
528 >
529 IFN .&<^-1777>,<
530 IFIDN <ADR><TESTI>,<
531 JMPSUB TESTIH
532 %ADRH==%ADRH!1
533 >
534 IFIDN <ADR><LPADR>,<
535 IFE <LPADR-ERLP>,<
536 JMPSUB ERLPH
537 %ADRH==%ADRH!2
538 >
539 IFE <LPADR-ERLPM>,<
540 JMPSUB ERLPMH
541 %ADRH==%ADRH!4
542 >
543 IFE <LPADR-ERLPA>,<
544 JMPSUB ERLPAH
545 %ADRH==%ADRH!10
546 >
547 IFDEF CATAB,<
548 IFE <LPADR-ERLPD>,<
549 JMPSUB ERLPDH
550 %ADRH==%ADRH!400
551 >
552 >
553 >
554 IFIDN <ADR><ERRSET>,<
555 JMPSUB ERSETH
556 %ADRH==%ADRH!20
557 >
558 IFIDN <ADR><REPTU>,<
559 JMPSUB REPTUH
560 %ADRH==%ADRH!40
561 >
562 IFDEF RHDATA,<
563 IFIDN <ADR><SETWRT>,<
564 JMPSUB STWRTH
565 %ADRH==%ADRH!100
566 >
567 IFIDN <ADR><SETRD>,<
568 JMPSUB STRDH
569 %ADRH==%ADRH!100
570 >
571 IFIDN <ADR><SETRDB>,<
572 JMPSUB STRDBH
573 %ADRH==%ADRH!100
574 >
575 IFIDN <ADR><CKTRM>,<JMPSUB CKTRMH>
576 >
577 IFDEF CUADRS,<
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 6-1
MCERR MAC 17-Oct-88 14:28 DATA PATH BIT REGISTER DEFINITIONS
578 IFIDN <ADR><SENDAD>,<
579 JMPSUB SNDADH
580 %ADRH==%ADRH!200
581 >
582 >
583 >
584 >
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 7
MCERR MAC 17-Oct-88 14:28 DATA PATH BIT REGISTER DEFINITIONS
585 DEFINE .ECRAM,<
586 IFE .&<^-1777>,< JMP BEGEND>
587 IFN .&<^-1777>,< JUMP BEGEND>
588 IFN %ADRH&1,< TESTIH: MOVB AC5
589 JUMP TEST0I>
590 IFN %ADRH&2,< ERLPH: MOVB AC5
591 JUMP ERLP0>
592 IFN %ADRH&4,< ERLPMH: MOVB AC5
593 JUMP ERLPM0>
594 IFN %ADRH&10,< ERLPAH: MOVB AC5
595 JUMP ERLPA0>
596 IFN %ADRH&20,< ERSETH: JUMP ERRSET>
597 IFN %ADRH&40,< REPTUH: JUMP REPTU>
598 IFN %ADRH&100,< STWRTH: LDBR 1
599 JMP CALLH
600 STRDH: LDBR 2
601 JMP CALLH
602 STRDBH: LDBR 3
603 CALLH: MOVB AC5
604 JUMP CALL0
605 CKTRMH: MOVB AC5
606 JUMP CKTRM0>
607 IFN %ADRH&200,< SNDADH: LDBR 200
608 MOVB AC5
609 JUMP CALL0>
610 IFN %ADRH&400,< ERLPDH: MOVB AC5
611 JUMP ERLPD0>
612 >
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 8
MCERR MAC 17-Oct-88 14:28 DATA PATH BIT REGISTER DEFINITIONS
613 ;MICRO-DIAGNOSTIC START ROUTINE
614
615 .INIT ^ ;INITIALIZE THE CROSS ASSEMBLER
616
617 SALL
618 000000 0 002000 01 0000
619
620 000001 0 002011 0 1 0 011 BEGIN: LDBR 11 ;SELECT THE MASSBUS
621 000002 0 066371 3 3 0 17 11 MOVB IOSEL ;INTERFACE
622 000003 0 022000 1 1 0 00 00 WAITGO: DATI MPSCR0,BR ;READ CONTROL REGISTER
623 000004 0 014000 0 6 0 000 SHR ;SHIFT GO BIT TO BIT 0
624 000005 0 104007 4 2 0007 JMPB0 .+2 ;JUMP AROUND IF GO IS SET
625 000006 0 100003 4 0 0003 JMP WAITGO ;NOT YET, KEEP WAITING
626 000007 0 022000 1 1 0 00 00 DATI MPSCR0,BR ;READ THE FUNCTION CODE AGAIN
627 000010 0 014000 0 6 0 000 SHR ;SHIFT RIGHT
628 000011 0 014000 0 6 0 000 SHR ;SHIFT F0 TO BIT 0
629 000012 0 104031 4 2 0031 JMPB0 CMDF0 ;JUMP IF F0 IS SET
630 000013 0 014000 0 6 0 000 SHR ;SHIFT F1 TO BIT 0
631 000014 0 104017 4 2 0017 JMPB0 .+3 ;JUMP IF RELIABILITY MODE REQUESTED
632 000015 0 002000 0 1 0 000 LDBR 0 ;SET UP FLAG REG WITH ALL ZEROS
633 000016 0 100020 4 0 0020 JMP .+2
634 000017 0 002040 0 1 0 040 LDBR 40 ;SET RELIABILITY MODE FLAG
635 000020 0 072171 3 5 0 07 11 MOVB AC7 ;PUT IN AC7
636 000021 0 002300 0 1 0 300 LDBR INIT+SPRES ;RESET THE DX20
637 000022 0 066371 3 3 0 17 11 MOVB IOSEL ;AND THE STACK POINTER
638 000023 0 002011 0 1 0 011 LDBR 11 ;SELECT THE MASSBUS
639 000024 0 066371 3 3 0 17 11 MOVB IOSEL ;INTERFACE AGAIN
640 000025 0 002000 0 1 0 000 LDBR 0 ;CLEAR RIGHT HALF OF DXGP3
641 000026 0 064351 3 2 0 16 11 MOVB MPGP6 ;TO INDICATE NO ADDITIONAL ERROR PRINTER
642 000027 0 116033 4 7 0033 JMPSUB OFFGO ;TURN OFF GO
643 000030 0 100236 4 0 0236 JMP TSTART ;GO START THE FIRST TEST
644
645 000031 0 014000 0 6 0 000 CMDF0: SHR ;SHIFT F1 TO BIT 0
646 000032 0 016000 0 7 0 000 RETURN ;RETURN TO CALLER
647
648 000033 0 002000 0 1 0 000 OFFGO: LDBR 0 ;GET A ZERO
649 000034 0 064051 3 2 0 02 11 MOVB MPECR ;CLEAR ERROR CODE REGISTER
650 000035 0 032121 1 5 0 05 01 DATI MPSCR1,AC5 ;READ STATUS REGISTER 1
651 000036 0 002010 0 1 0 010 LDBR DTD ;GET MASK OF DIRECTION BIT
652 000037 0 072133 3 5 0 05 13 LANDBR AC5 ;KEEP ONLY THAT BIT
653 000040 0 002002 0 1 0 002 LDBR CLRGO ;GET BIT TO CLEAR GO
654 000041 0 062134 3 1 0 05 14 LORB AC5,BR ;COMBINE WITH COPY OF DTD
655 000042 0 064031 3 2 0 01 11 MOVB MPSCR1 ;CLEAR GO AND ATA
656 000043 0 016000 0 7 0 000 RETURN
657
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 9
MCERR MAC 17-Oct-88 14:28 DATA PATH BIT REGISTER DEFINITIONS
658 ;TEST INITIALIZATION
659
660 000044 0 062130 3 1 0 05 10 TEST0I: MOV AC5,BR ;GET TEST NUMBER BACK
661 000045 0 001000 0 0 2 000 TESTI: LDMAR 0 ;CLEAR MEMORY ADDRESS REGISTER
662 000046 0 000400 0 0 1 000 LDMARX 0 ;ALL BITS
663 000047 0 132157 5 5 0 06 17 DATI IOSEL,AC6 ;SAVE IOSEL REG
664 000050 0 010011 0 4 0 011 LDMEM 11 ;GET DEVICE CODE FOR MASSBUS INTERFACE
665 000051 0 046371 2 3 0 17 11 MOVMEM IOSEL ;LOAD INTO I/O SELECT REGISTER
666 000052 0 064211 3 2 0 10 11 MOVB MPGP0 ;WRITE TEST NUMBER INTO DXGP0
667 000053 0 062150 3 1 0 06 10 MOV AC6,BR ;GET SAVED IOSEL REG
668 000054 0 066371 3 3 0 17 11 MOVB IOSEL ;RESTORE IT
669 000055 0 002040 0 1 0 040 LDBR 40 ;GET MASK OF ONLY RELIABILITY BIT
670 000056 0 072173 3 5 0 07 13 LANDBR AC7 ;CLEAR ERROR AND MESSAGE NUMBER BITS
671 000057 0 062170 3 1 0 07 10 MOV AC7,BR ;GET FLAGS
672 000060 0 014000 0 6 0 000 SHR ;SHIFT RELIABILITY MODE BIT TO BR4
673 000061 0 106064 4 3 0064 JMPB4 .+3 ;JUMP AROUND IF RELIABILITY MODE
674 000062 0 002000 0 1 0 000 LDBR 0 ;QUICK VERIFY, LOAD A ZERO COUNT
675 000063 0 100065 4 0 0065 JMP .+2
676 000064 0 002077 0 1 0 077 LDBR RPTCNT-1 ;GET REPEAT COUNT
677 000065 0 072151 3 5 0 06 11 MOVB AC6 ;SAVE IN AC6
678 000066 0 016000 0 7 0 000 RETURN ;NOW START THE TEST
679
680 ;I/O SELECT REGISTER GENERAL ROUTINES
681
682 000067 0 132117 5 5 0 04 17 SAVIOS: DATI IOSEL,AC4 ;SAVE I/O SELECT REGISTER IN AC4
683 000070 0 002011 0 1 0 011 LDBR 11 ;SELECT MASSBUS INTERFACE
684 000071 0 066371 3 3 0 17 11 MOVB IOSEL ;GO I/O
685 000072 0 016000 0 7 0 000 NRTN: RETURN
686
687 000073 0 062110 3 1 0 04 10 RESIOS: MOV AC4,BR ;GET SAVED I/O SELECT REGISTER
688 000074 0 066371 3 3 0 17 11 MOVB IOSEL ;RESTORE IT
689 000075 0 016000 0 7 0 000 RETURN
690
691 ;ROUTINE TO SET ATA AND/OR MPERR IN STATUS REGISTER
692 ;ENTER WITH BITS TO SET IN BR
693
694 000076 0 032121 1 5 0 05 01 SETATA: DATI MPSCR1,AC5 ;READ STATUS REGISTER
695 000077 0 072134 3 5 0 05 14 LORBR AC5 ;SET REQUESTED BITS
696 000100 0 002310 0 1 0 310 LDBR ATA+MPERR+DTD ;GET MASK OF ONLY BITS TO SET
697 000101 0 062133 3 1 0 05 13 LANDB AC5,BR ;CLEAR OTHER BITS READ
698 000102 0 064031 3 2 0 01 11 MOVB MPSCR1 ;WRITE INTO STATUS REGISTER
699 000103 0 016000 0 7 0 000 RETURN
700
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 10
MCERR MAC 17-Oct-88 14:28 DATA PATH BIT REGISTER DEFINITIONS
701 ;ERROR HANDLER ROUTINES
702
703 000104 0 002300 0 1 0 300 ERRSET: LDBR 300 ;GET ERROR LOOP AND DETECTED FLAGS
704 000105 0 072174 3 5 0 07 14 LORBR AC7 ;SET BOTH BITS IN FLAG REGISTER
705 000106 0 016000 0 7 0 000 RETURN
706
707 ;CHECK IF TO REPORT AN ERROR
708
709 000107 0 062170 3 1 0 07 10 ERRCHK: MOV AC7,BR ;GET FLAG REGISTER
710 000110 0 110112 4 4 0112 IFNDEF .ERROR,<JMPB7 .+2> ;SKIP IF IN ERROR LOOP
711 IFDEF .ERROR,<JMP REPORT> ;REPORT ALL ERRORS
712 000111 0 016377 0 7 0 377 RETURN -1 ;RETURN WITH Z SET TO CONTINUE TEST
713 000112 0 062165 3 1 0 07 05 SHL AC7,BR ;SHIFT ERROR DETECTED BIT TO BR7
714 000113 0 110126 4 4 0126 JMPB7 REPORT ;REPORT IT IF SET
715 000114 0 002037 0 1 0 037 LDBR 37 ;GET MASK FOR ERROR NUMBER
716 000115 0 072133 3 5 0 05 13 LANDBR AC5 ;CLEAR CONTROL BITS IN CURRENT NUMBER
717 000116 0 062173 3 1 0 07 13 LANDB AC7,BR ;EXTRACT LAST ERROR NUMBER
718 000117 0 060137 3 0 0 05 17 OSB AC5 ;COMPARE LAST AND CURRENT ERROR NUMBERS
719 000120 0 114122 4 6 0122 JMPZ NOFAIL ;JUMP IF AT SAME ERROR
720 000121 0 016377 0 7 0 377 RETURN -1 ;NO, RETURN WITH Z SET TO CONTINUE TEST
721 000122 0 116067 4 7 0067 NOFAIL: JMPSUB SAVIOS ;SAVE I/O REGISTER, SELECT MASSBUS
722 000123 0 002200 0 1 0 200 LDBR ATA ;GET ATA BIT
723 000124 0 072131 3 5 0 05 11 MOVB AC5 ;SAVE IN AC5
724 000125 0 016000 0 7 0 000 RETURN ;RETURN WITH Z CLEAR TO SIGNAL END OF LOOP
725
726 000126 0 116067 4 7 0067 REPORT: JMPSUB SAVIOS ;SAVE I/O REGISTER, SELECT MASSBUS
727 000127 0 062130 3 1 0 05 10 MOV AC5,BR ;GET ERROR NUMBER
728 000130 0 064051 3 2 0 02 11 MOVB MPECR ;PUT IN ERROR CODE REGISTER
729 000131 0 002240 0 1 0 240 LDBR 240 ;GET MASK OF LOOP AND RELIABILITY BITS
730 000132 0 072173 3 5 0 07 13 LANDBR AC7 ;LEAVE ONLY THOSE TWO BITS IN FLAG REG
731 000133 0 002037 0 1 0 037 LDBR 37 ;GET MASK OF ERROR NUMBER
732 000134 0 062133 3 1 0 05 13 LANDB AC5,BR ;GET CURRENT NUMBER FROM AC5
733 000135 0 072174 3 5 0 07 14 LORBR AC7 ;MERGE AND PUT IN FLAG REGISTER
734 000136 0 002300 0 1 0 300 LDBR ATA+MPERR ;GET ATA AND ERROR BITS
735 000137 0 072131 3 5 0 05 11 MOVB AC5 ;SAVE IN AC5
736 000140 0 016000 0 7 0 000 RETURN ;RETURN WITH Z CLEAR TO SIGNAL ERROR REPORT
737
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 11
MCERR MAC 17-Oct-88 14:28 DATA PATH BIT REGISTER DEFINITIONS
738 000141 0 072131 3 5 0 05 11 ERLP: MOVB AC5 ;SAVE MESSAGE NUMBER IN AC5
739 000142 0 116107 4 7 0107 ERLP0: JMPSUB ERRCHK ;CHECK FOR ERROR
740 000143 0 114072 4 6 0072 JMPZ NRTN ;NO, RETURN WITH Z CLEAR TO CONTINUE TEST
741 000144 0 100161 4 0 0161 JMP ERRCOM ;GO TO COMMON ROUTINE
742
743 000145 0 072131 3 5 0 05 11 ERLPM: MOVB AC5 ;SAVE MESSAGE NUMBER IN AC5
744 000146 0 116107 4 7 0107 ERLPM0: JMPSUB ERRCHK ;CHECK FOR ERROR
745 000147 0 114072 4 6 0072 JMPZ NRTN ;NO, RETURN WITH Z CLEAR TO CONTINUE TEST
746 000150 0 044311 2 2 0 14 11 MOVMEM MPGP4 ;PUT CORRECT DATA IN RIGHT HALF OF DXGP2
747 000151 0 100157 4 0 0157 JMP ERRCA ;JUMP AROUND
748
749 000152 0 072131 3 5 0 05 11 ERLPA: MOVB AC5 ;SAVE MESSAGE NUMBER IN AC5
750 000153 0 116107 4 7 0107 ERLPA0: JMPSUB ERRCHK ;CHECK FOR ERROR
751 000154 0 114072 4 6 0072 JMPZ NRTN ;NO, RETURN WITH Z CLEAR TO CONTINUE TEST
752 000155 0 062030 3 1 0 01 10 MOV AC1,BR ;GET CORRECT DATA FROM AC1
753 000156 0 064311 3 2 0 14 11 MOVB MPGP4 ;PUT IN RIGHT HALF OF DXGP2
754 000157 0 062010 3 1 0 00 10 ERRCA: MOV AC0,BR ;GET ACTUAL DATA FROM AC0
755 000160 0 064331 3 2 0 15 11 MOVB MPGP5 ;PUT IN LEFT HALF OF DXGP2
756 000161 0 062130 3 1 0 05 10 ERRCOM: MOV AC5,BR ;GET BITS TO SET IN STATUS REGISTER
757 000162 0 116076 4 7 0076 CHKLOP: JMPSUB SETATA ;GO SET THE BITS
758 000163 0 116003 4 7 0003 CHKLP: JMPSUB WAITGO ;WAIT FOR GO TO SET
759 000164 0 104170 4 2 0170 JMPB0 ELOOPC ;JUMP IF TO CONTINUE
760 000165 0 116033 4 7 0033 JMPSUB OFFGO ;TURN OFF GO
761 000166 0 116073 4 7 0073 JMPSUB RESIOS ;RESTORE I/O SELECT REGISTER
762 000167 0 016377 0 7 0 377 ZRTN: RETURN -1 ;RETURN WITH Z SET TO LOOP
763
764 000170 0 116033 4 7 0033 ELOOPC: JMPSUB OFFGO ;TURN OFF GO
765 000171 0 116073 4 7 0073 JMPSUB RESIOS ;RESTORE I/O SELECT REGISTER
766 000172 0 016000 0 7 0 000 RETURN ;RETURN WITH Z CLEAR TO CONTINUE
767
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 12
MCERR MAC 17-Oct-88 14:28 DATA PATH BIT REGISTER DEFINITIONS
768 XLIST
769 LIST
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 13
MCERR MAC 17-Oct-88 14:28 DATA PATH BIT REGISTER DEFINITIONS
770 XLIST
771 LIST
772 000173 0 002200 0 1 0 200 SENDAD: LDBR 200 ;SET UP CODE FOR HOST
773 000174 0 100202 4 0 0202 JMP CALL
774 000175 0 002001 0 1 0 001 SETWRT: LDBR 1 ;SET UP CODE FOR HOST
775 000176 0 100202 4 0 0202 JMP CALL
776 000177 0 002002 0 1 0 002 SETRD: LDBR 2 ;SET UP CODE FOR HOST
777 000200 0 100202 4 0 0202 JMP CALL
778 000201 0 002003 0 1 0 003 SETRDB: LDBR 3 ;SET UP CODE FOR HOST
779 000202 0 072131 3 5 0 05 11 CALL: MOVB AC5 ;SAVE CODE IN AC5
780 000203 0 116067 4 7 0067 CALL0: JMPSUB SAVIOS ;SAVE I/O SELECT REG., SELECT MASSBUS
781 000204 0 062130 3 1 0 05 10 MOV AC5,BR ;GET CODE TO PASS TO HOST
782 000205 0 064051 3 2 0 02 11 MOVB MPECR ;WRITE INTO ERROR CODE REGISTER
783 000206 0 002200 0 1 0 200 LDBR ATA ;GET ATTENTION BIT
784 000207 0 116076 4 7 0076 JMPSUB SETATA ;SET ATTENTION IN STATUS REGISTER
785 000210 0 116003 4 7 0003 JMPSUB WAITGO ;WAIT FOR GO TO SET
786 000211 0 116033 4 7 0033 JMPSUB OFFGO ;TURN GO OFF AGAIN
787 000212 0 116073 4 7 0073 JMPSUB RESIOS ;RESTORE THE I/O SELECT REGISTER
788 000213 0 016000 0 7 0 000 RETURN ;RETURN, RH20 IS SET UP
789
790 000214 0 072131 3 5 0 05 11 CKTRM: MOVB AC5 ;SAVE MESSAGE NUMBER IN AC5
791 000215 0 116067 4 7 0067 CKTRM0: JMPSUB SAVIOS ;SAVE I/O SELECT REG., SELECT MASSBUS
792 000216 0 062130 3 1 0 05 10 MOV AC5,BR ;GET MESSAGE NUMBER AGAIN
793 000217 0 064051 3 2 0 02 11 MOVB MPECR ;WRITE IT INTO ERROR CODE REGISTER
794 000220 0 002200 0 1 0 200 LDBR ATA ;GET ATTENTION BIT
795 000221 0 100162 4 0 0162 JMP CHKLOP ;TELL HOST, DECIDE IF TO LOOP ON RESPONSE
796
797 XLIST
798 LIST
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 14
MCERR MAC 17-Oct-88 14:28 DATA PATH BIT REGISTER DEFINITIONS
799 ;REPEAT TEST ROUTINE
800
801 000222 0 072147 3 5 0 06 07 REPTU: DECR AC6 ;DECREMENT REPEAT COUNT
802 000223 0 114072 4 6 0072 JMPZ NRTN ;IF NOW -1, RETURN WITH Z CLEAR
803 000224 0 016377 0 7 0 377 RETURN -1 ;RETURN WITH Z SET TO REPEAT TEST
804
805 ;REPORT END OF DIAGNOSTIC WITH 0 ERROR CODE AND 0 TEST NUMBER
806
807 000225 0 002011 0 1 0 011 BEGEND: LDBR 11 ;SELECT MASSBUS INTERFACE
808 000226 0 066371 3 3 0 17 11 MOVB IOSEL ;IN I/O SELECT REGISTER
809 000227 0 002000 0 1 0 000 LDBR 0 ;GET A ZERO
810 000230 0 064211 3 2 0 10 11 MOVB MPGP0 ;MAKE TEST NUMBER 0
811 000231 0 064231 3 2 0 11 11 MOVB MPGP1 ;TO SAY END OF DIAGNOSTIC
812 000232 0 002200 0 1 0 200 LDBR ATA ;GET ATTENTION BIT
813 000233 0 064031 3 2 0 01 11 MOVB MPSCR1 ;SET IT
814 000234 0 116003 4 7 0003 JMPSUB WAITGO ;WAIT FOR GO TO SET
815 000235 0 100001 4 0 0001 JMP BEGIN ;START DIAGNOSTIC OVER AGAIN
816
817
818 000236 TSTART: ;COME HERE TO START THE TESTING
819
820
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 1
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
821 SUBTTL DATA PATH TEST - PART 2
822
823 DEFTST MCODE5
824 TEST 225,TEST MASSBUS COUNTER (MC)
825 ;***********************************************************************
826 ;* MCODE5 * TEST 225 * TEST MASSBUS COUNTER (MC)
827 ;***********************************************************************
828 SALL
829 000236 0 002011 0 1 0 011
830 000237 0 066371 3 3 0 17 11
831 000240 0 002000 0 1 0 000
832 000241 0 064231 3 2 0 11 11
833 000242 0 002341 0 1 0 341
834 000243 0 116045 4 7 0045
835
836 000244 TST225: SALL
837
838 ;*TEST THAT THE MC INCREMENTS CORRECTLY WHEN A "SET MSTR ACK" PULSE IS
839 ;*GENERATED.
840
841 ;*LOAD TEST DATA INTO THE MC.
842 ;*SET "MSTR RDY DLY 2".
843 ;*SET "DIAG MSTR REQ".
844 ;*CHECK THE MC FOR CORRECT INCREMENTED DATA.
845
846 000244 0 001000 0 0 2 000 LDMAR 0 ;CLEAR MAR
847 000245 0 010001 0 4 0 001 LDMEM 1 ;SETUP ADD PNT ROUTINE NUMBER
848 000246 0 002224 0 1 0 224 GOSUB SETPNT
849 000247 0 177631 7 7 3 11 11
850 000250 0 002057 0 1 0 057 LDBR CNTDAT ;SETUP POINTER TO DATA TO LOAD
851 000251 0 072051 3 5 0 02 11 MOVB AC2
852 000252 0 002011 0 1 0 011 LDBR CNTCOR ;SETUP POINTER TO CORRECT DATA AFTER
853 000253 0 072071 3 5 0 03 11 MOVB AC3 ;INCREMENTING
854 000254 0 002022 0 1 0 022 LDBR ^D18 ;SET LOOP COUNT MINUS 1
855 000255 0 072031 3 5 0 01 11 MOVB AC1
856 000256 0 061050 3 0 2 02 10 MCLP: MOV AC2,MAR ;SET MAR TO POINT TO LOAD DATA
857 000257 0 045531 2 2 3 05 11 MOVMEM MCHI,I ;LOAD HI ORDER BITS AND INC POINTER
858 000260 0 044111 2 2 0 04 11 MOVMEM MCLO ;LOAD LOW ORDER BITS
859 000261 0 002000 0 1 0 000 LDBR 0 ;CLEAR "DIAG MSTR REQ"
860 000262 0 064031 3 2 0 01 11 MOVB REG1
861 000263 0 002105 0 1 0 105 GOSUB DEVWR ;SETUP DEVICE WRITE
862 000264 0 177631 7 7 3 11 11
863 000265 0 064271 3 2 0 13 11 MOVB HSDPIN ;SET "MSTR RDY DLY 2"
864 000266 0 002010 0 1 0 010 LDBR DMSTRQ ;SET "DIAG MSTR REQ"
865 000267 0 064031 3 2 0 01 11 MOVB REG1
866 000270 0 000000 0 0 0 000 NOP ;DELAY BEFORE DOING DATI
867 000271 0 032005 1 5 0 00 05 DATI MCHI,AC0 ;READ HI ORDER BITS
868 000272 0 032104 1 5 0 04 04 DATI MCLO,AC4 ;READ LOW ORDER BITS
869 000273 0 002011 0 1 0 011 LDBR 11 ;SELECT MASSBUS INTERFACE
870 000274 0 066371 3 3 0 17 11 MOVB IOSEL
871 000275 0 061050 3 0 2 02 10 MOV AC2,MAR ;STORE LOADED DATA FOR
872 000276 0 047471 2 3 3 03 11 MOVMEM MPGP13,I ;ERROR
873 000277 0 046051 2 3 0 02 11 MOVMEM MPGP12 ;PRINTOUT
874 000300 0 062110 3 1 0 04 10 MOV AC4,BR ;STORE ACTUAL DATA FOR
875 000301 0 066151 3 3 0 06 11 MOVB MPGP16 ;ERROR
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 1-1
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
876 000302 0 062010 3 1 0 00 10 MOV AC0,BR ;PRINTOUT
877 000303 0 066171 3 3 0 07 11 MOVB MPGP17
878 000304 0 061070 3 0 2 03 10 MOV AC3,MAR ;STORE CORRECT DATA FOR
879 000305 0 047531 2 3 3 05 11 MOVMEM MPGP15,I ;ERROR
880 000306 0 046111 2 3 0 04 11 MOVMEM MPGP14 ;PRINTOUT
881 000307 0 002022 0 1 0 022 LDBR 22 ;SELECT DATA PATH
882 000310 0 066371 3 3 0 17 11 MOVB IOSEL
883 000311 0 061070 3 0 2 03 10 MOV AC3,MAR ;SET MAR TO CORRECT DATA
884 000312 0 041417 2 0 3 00 17 OSM AC0,I ;CHECK IF HI ORDER BITS CORRECT
885 000313 0 114315 4 6 0315 JMPZ .+2 ;JUMP IF CORRECT
886 000314 0 100317 4 0 0317 JMP MCERR ;ELSE, REPORT ERROR
887 000315 0 040117 2 0 0 04 17 OSM AC4 ;CHECK IF LOW ORDER BITS CORRECT
888 000316 0 114320 4 6 0320 JMPZ .+2 ;JUMP IF CORRECT
889 000317 0 116104 4 7 0104 MCERR: ERROR MCLP,MC DID NOT INCREMENT CORRECTLY,,PNT
890
891 ERLOOP MCLP ^SALL
892 000320 0 002200 0 1 0 200
893 000321 0 116141 4 7 0141
894 000322 0 114256 4 6 0256
895 000323 0 072063 3 5 0 03 03 INCR AC3 ;INC CORRECT DATA POINTER TO
896 000324 0 072063 3 5 0 03 03 INCR AC3 ;NEXT VALUE
897 000325 0 072043 3 5 0 02 03 INCR AC2 ;INC LOAD DATA POINTER TO
898 000326 0 072043 3 5 0 02 03 INCR AC2 ;NEXT VALUE
899 000327 0 072027 3 5 0 01 07 DECR AC1 ;DEC LOOP COUNT
900 000330 0 114332 4 6 0332 JMPZ .+2 ;JUMP IF DONE
901 000331 0 100256 4 0 0256 JMP MCLP ;ELSE, CONTINUE
902
903 000332 0 116222 4 7 0222 REPEAT TST
904 000333 0 114244 4 6 0244
905
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 2
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
906 TEST 226,TEST "MC OF FLAG"
907 ;***********************************************************************
908 ;* MCODE5 * TEST 226 * TEST "MC OF FLAG"
909 ;***********************************************************************
910 SALL
911 000334 0 002342 0 1 0 342
912 000335 0 116045 4 7 0045
913
914 000336 TST226: SALL
915
916 ;*CLEAR ALL REG 0 FLAGS.
917 ;*LOAD MC WITH ALL ONES AND CLOCK IT.
918 ;*CHECK THAT "MC OF FLAG" IS SET.
919
920 000336 0 064011 3 2 0 00 11 MOVB REG0 ;CLEAR FLAGS
921 000337 0 002377 0 1 0 377 LDBR 377 ;LOAD ALL ONES INTO MC
922 000340 0 064111 3 2 0 04 11 MOVB MCLO
923 000341 0 064131 3 2 0 05 11 MOVB MCHI
924 000342 0 002000 0 1 0 000 LDBR 0 ;CLEAR "DIAG MSTR REQ"
925 000343 0 064031 3 2 0 01 11 MOVB REG1
926 000344 0 002105 0 1 0 105 GOSUB DEVWR ;SETUP DEVICE WRITE
927 000345 0 177631 7 7 3 11 11
928 000346 0 064271 3 2 0 13 11 MOVB HSDPIN ;SET "MSTR RDY DLY 2"
929 000347 0 002010 0 1 0 010 LDBR DMSTRQ ;SET "DIAG MSTR REQ"
930 000350 0 064031 3 2 0 01 11 MOVB REG1
931 000351 0 000000 0 0 0 000 NOP ;DELAY BEFORE DOING DATI
932 000352 0 032000 1 5 0 00 00 DATI REG0,AC0 ;READ REG 0
933 000353 0 062005 3 1 0 00 05 SHL AC0,BR ;MOVE "MC OF FLAG" TO BIT 4
934 000354 0 106356 4 3 0356 JMPB4 .+2 ;JUMP IF SET, SHOULD BE
935 ERROR TST,"MC OF FLAG" DID NOT SET,^_
936 000355 0 116104 4 7 0104 DIAG LOADED MC WITH ALL ONES THEN SET "DIAG MSTR REQ"
937
938 ERLOOP TST ^SALL
939 000356 0 002000 0 1 0 000
940 000357 0 116141 4 7 0141
941 000360 0 114336 4 6 0336
942 ;*LOAD ALL ZEROS INTO THE MC AND CLOCK IT.
943 ;*CHECK THAT "MC OF FLAG" STAYS SET.
944
945 000361 0 002000 0 1 0 000 LDBR 0 ;CLEAR THE MC
946 000362 0 064131 3 2 0 05 11 MOVB MCHI
947 000363 0 064111 3 2 0 04 11 MOVB MCLO
948 000364 0 002000 0 1 0 000 LDBR 0 ;CLEAR "DIAG MSTR REQ"
949 000365 0 064031 3 2 0 01 11 MOVB REG1
950 000366 0 002105 0 1 0 105 GOSUB DEVWR ;SETUP DEVICE WRITE
951 000367 0 177631 7 7 3 11 11
952 000370 0 064271 3 2 0 13 11 MOVB HSDPIN ;SET "MSTR RDY DLY 2"
953 000371 0 002010 0 1 0 010 LDBR DMSTRQ ;SET "DIAG MSTR REQ"
954 000372 0 064031 3 2 0 01 11 MOVB REG1
955 000373 0 000000 0 0 0 000 NOP ;DELAY BEFORE DOING DATI
956 000374 0 032000 1 5 0 00 00 DATI REG0,AC0 ;READ REG 0
957 000375 0 062005 3 1 0 00 05 SHL AC0,BR ;MOVE "MC OF FLAG" TO BIT 4
958 000376 0 106400 4 3 0400 JMPB4 .+2 ;JUMP IF SET, SHOULD BE
959 ERROR TST,"MC OF FLAG" DID NOT STAY SET,^_
960 <DIAG SET "MC OF FLAG" THEN LOADED MC WITH ZEROS AND
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 2-1
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
961 000377 0 116104 4 7 0104 SET "DIAG MSTR REQ">
962
963 ERLOOP TST ^SALL
964 000400 0 002001 0 1 0 001
965 000401 0 116141 4 7 0141
966 000402 0 114336 4 6 0336
967 ;*WRITE REG 0.
968 ;*CHECK THAT "MC OF FLAG" IS CLEARED.
969
970 000403 0 064011 3 2 0 00 11 MOVB REG0 ;WRITE REG 0 TO CLEAR FLAGS
971 000404 0 000000 0 0 0 000 NOP ;DELAY BEFORE DOING DATI
972 000405 0 032000 1 5 0 00 00 DATI REG0,AC0 ;READ REG 0
973 000406 0 062005 3 1 0 00 05 SHL AC0,BR ;MOVE "MC OF FLAG" TO BIT 4
974 000407 0 106411 4 3 0411 JMPB4 .+2 ;JUMP IF SET, SHOULDN'T BE
975 000410 0 100412 4 0 0412 JMP .+2 ;JUMP IF CLEARED
976 ERROR TST,"MC OF FLAG" DID NOT CLEAR,^_
977 000411 0 116104 4 7 0104 DIAG SET "MC OF FLAG" THEN WROTE REG 0
978
979 ERLOOP TST ^SALL
980 000412 0 002002 0 1 0 002
981 000413 0 116141 4 7 0141
982 000414 0 114336 4 6 0336
983 ;*LOAD MC WITH SELECTED DATA PATTERNS THEN CLOCK IT.
984 ;*CHECK THAT "MC OF FLAG" IS NOT SET.
985
986 000415 0 001001 0 0 2 001 MCOF1: LDMAR CTR1 ;SET MAR TO LOAD DATA
987 000416 0 002015 0 1 0 015 GOSUB MCFTST ;GO LOAD MC AND CLOCK IT
988 000417 0 177631 7 7 3 11 11
989 000420 0 114422 4 6 0422 JMPZ .+2 ;JUMP IF CLEAR
990 ERROR MCOF1,"MC OF FLAG" SET WHEN IT SHOULDN'T HAVE,^_
991 000421 0 116104 4 7 0104 DIAG LOADED MC WITH 177760 THEN SET "DIAG MSTR REQ"
992
993 ERLOOP MCOF1 ^SALL
994 000422 0 002003 0 1 0 003
995 000423 0 116141 4 7 0141
996 000424 0 114415 4 6 0415
997 000425 0 001003 0 0 2 003 MCOF2: LDMAR CTR2 ;SET MAR TO LOAD DATA
998 000426 0 002015 0 1 0 015 GOSUB MCFTST ;GO LOAD MC AND CLOCK IT
999 000427 0 177631 7 7 3 11 11
1000 000430 0 114432 4 6 0432 JMPZ .+2 ;JUMP IF CLEAR
1001 ERROR MCOF1,"MC OF FLAG" SET WHEN IT SHOULDN'T HAVE,^_
1002 000431 0 116104 4 7 0104 DIAG LOADED MC WITH 177417 THEN SET "DIAG MSTR REQ"
1003
1004 ERLOOP MCOF1 ^SALL
1005 000432 0 002004 0 1 0 004
1006 000433 0 116141 4 7 0141
1007 000434 0 114415 4 6 0415
1008 000435 0 001005 0 0 2 005 MCOF3: LDMAR CTR3 ;SET MAR TO LOAD DATA
1009 000436 0 002015 0 1 0 015 GOSUB MCFTST ;GO LOAD MC AND CLOCK IT
1010 000437 0 177631 7 7 3 11 11
1011 000440 0 114442 4 6 0442 JMPZ .+2 ;JUMP IF CLEAR
1012 ERROR MCOF1,"MC OF FLAG" SET WHEN IT SHOULDN'T HAVE,^_
1013 000441 0 116104 4 7 0104 DIAG LOADED MC WITH 170377 THEN SET "DIAG MSTR REQ"
1014
1015 ERLOOP MCOF1 ^SALL
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 2-2
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
1016 000442 0 002005 0 1 0 005
1017 000443 0 116141 4 7 0141
1018 000444 0 114415 4 6 0415
1019 000445 0 001007 0 0 2 007 MCOF4: LDMAR CTR4 ;SET MAR TO LOAD DATA
1020 000446 0 002015 0 1 0 015 GOSUB MCFTST ;GO LOAD MC AND CLOCK IT
1021 000447 0 177631 7 7 3 11 11
1022 000450 0 114452 4 6 0452 JMPZ .+2 ;JUMP IF CLEAR
1023 ERROR MCOF1,"MC OF FLAG" SET WHEN IT SHOULDN'T HAVE,^_
1024 000451 0 116104 4 7 0104 DIAG LOADED MC WITH 7777 THEN SET "DIAG MSTR REQ"
1025
1026 ERLOOP MCOF1 ^SALL
1027 000452 0 002006 0 1 0 006
1028 000453 0 116141 4 7 0141
1029 000454 0 114415 4 6 0415
1030 000455 0 116222 4 7 0222 REPEAT TST
1031 000456 0 114336 4 6 0336
1032
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 3
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
1033 TEST 227,TEST GENERATION OF "MSTR END XFER"
1034 ;***********************************************************************
1035 ;* MCODE5 * TEST 227 * TEST GENERATION OF "MSTR END XFER"
1036 ;***********************************************************************
1037 SALL
1038 000457 0 002343 0 1 0 343
1039 000460 0 116045 4 7 0045
1040
1041 000461 TST227: SALL
1042
1043 ;*TEST THAT "MSTR END XFER" IS SET WHEN (1) "MC OF FLAG" SETS WITH
1044 ;*"MSTR END XFER ON MC OVFL" (MEX ON MC) SET, OR (2) "FMTR END XFER" SETS
1045 ;*WITH "MSTR END XFER ON FMTR END XFER" (MEX ON FEX) SET.
1046
1047 ;*CLEAR "MEX ON MC OVERFLOW" BIT.
1048 ;*GENERATE "MC OF FLAG".
1049 ;*CHECK THAT "MSTR END XFER" IS NOT SET.
1050
1051 000461 0 064011 3 2 0 00 11 MOVB REG0 ;CLEAR FLAGS
1052 000462 0 002377 0 1 0 377 LDBR 377 ;LOAD ALL ONES INTO MC
1053 000463 0 064111 3 2 0 04 11 MOVB MCLO
1054 000464 0 064131 3 2 0 05 11 MOVB MCHI
1055 000465 0 002000 0 1 0 000 LDBR 0
1056 000466 0 064051 3 2 0 02 11 MOVB REG2 ;CLEAR MEX ON MC BIT
1057 000467 0 002000 0 1 0 000 LDBR 0 ;CLEAR "DIAG MSTR REQ"
1058 000470 0 064031 3 2 0 01 11 MOVB REG1
1059 000471 0 002105 0 1 0 105 GOSUB DEVWR ;SETUP DEVICE WRITE
1060 000472 0 177631 7 7 3 11 11
1061 000473 0 064271 3 2 0 13 11 MOVB HSDPIN ;SET "MSTR RDY DLY 2"
1062 000474 0 002010 0 1 0 010 LDBR DMSTRQ ;SET "DIAG MSTR REQ"
1063 000475 0 064031 3 2 0 01 11 MOVB REG1
1064 000476 0 000000 0 0 0 000 NOP ;DELAY BEFORE DOING DATI
1065 000477 0 022003 1 1 0 00 03 DATI REG3,BR ;READ REG 3
1066 000500 0 014000 0 6 0 000 SHR ;RIGHT ADJUST "NOT MSTR END XFER" BIT
1067 000501 0 014000 0 6 0 000 SHR
1068 000502 0 104504 4 2 0504 JMPB0 .+2 ;JUMP IF SET, SHOULD BE
1069 ERROR TST,"MSTR END XFER" SET WHEN IT SHOULDN'T HAVE,^_
1070 000503 0 116104 4 7 0104 DIAG CLEARED "MEX ON MC" THEN SET "MC OF FLAG"
1071
1072 ERLOOP TST ^SALL
1073 000504 0 002000 0 1 0 000
1074 000505 0 116141 4 7 0141
1075 000506 0 114461 4 6 0461
1076 ;*SET "MEX ON MC OVERFLOW" BIT.
1077 ;*CHECK THAT "MSTR END XFER" IS SET.
1078
1079 000507 0 002004 0 1 0 004 LDBR MEMCOV ;SET "MEX ON MC"
1080 000510 0 064051 3 2 0 02 11 MOVB REG2
1081 000511 0 000000 0 0 0 000 NOP ;DELAY BEFORE DOING DATI
1082 000512 0 022003 1 1 0 00 03 DATI REG3,BR ;READ REG 3
1083 000513 0 014000 0 6 0 000 SHR ;RIGHT ADJUST "NOT MSTR END XFER" BIT
1084 000514 0 014000 0 6 0 000 SHR
1085 000515 0 104517 4 2 0517 JMPB0 .+2 ;JUMP IF IT SET, SHOULDN'T HAVE
1086 000516 0 100520 4 0 0520 JMP .+2 ;ELSE, OKAY
1087 ERROR TST,"MSTR END XFER" DID NOT SET,^_
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 3-1
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
1088 000517 0 116104 4 7 0104 DIAG SET "MC OF FLAG" THEN SET "MEX ON MC"
1089
1090 ERLOOP TST ^SALL
1091 000520 0 002001 0 1 0 001
1092 000521 0 116141 4 7 0141
1093 000522 0 114461 4 6 0461
1094 ;*WRITE REG 0 TO CLEAR "MC OF FLAG".
1095 ;*CHECK THAT "MSTR END XFER" IS CLEARED.
1096
1097 000523 0 064011 3 2 0 00 11 MOVB REG0 ;CLEAR "MC OF FLAG"
1098 000524 0 000000 0 0 0 000 NOP ;DELAY BEFORE DOING DATI
1099 000525 0 022003 1 1 0 00 03 DATI REG3,BR ;READ REG 3
1100 000526 0 014000 0 6 0 000 SHR ;RIGHT ADJUST "NOT MSTR END XFER" BIT
1101 000527 0 014000 0 6 0 000 SHR
1102 000530 0 104532 4 2 0532 JMPB0 .+2 ;JUMP IF SET, SHOULD BE
1103 ERROR TST,"MSTR END XFER" DIDN'T CLEAR,^_
1104 000531 0 116104 4 7 0104 DIAG SET "MSTR END XFER" THEN CLEARED "MC OF FLAG"
1105
1106 ERLOOP TST ^SALL
1107 000532 0 002002 0 1 0 002
1108 000533 0 116141 4 7 0141
1109 000534 0 114461 4 6 0461
1110 ;*SET "MEX ON FEX" BIT.
1111 ;*SET "FMTR END XFER".
1112 ;*CHECK THAT "MSTR END XFER" IS SET.
1113
1114 000535 0 002100 0 1 0 100 GOSUB DEVRD ;SETUP DEVICE READ
1115 000536 0 177631 7 7 3 11 11
1116 000537 0 002011 0 1 0 011 MEX1: LDBR RMADR8+MEONFE ;SET "MEX ON FEX" AND ROM ADDR BIT 8
1117 000540 0 064051 3 2 0 02 11 MOVB REG2
1118 000541 0 064271 3 2 0 13 11 MOVB HSDPIN ;CLEAR "RUN"
1119 000542 0 002000 0 1 0 000 LDBR 0 ;CLEAR "DX HIGH SPEED"
1120 000543 0 064031 3 2 0 01 11 MOVB REG1
1121 000544 0 002320 0 1 0 320 LDBR ZEROS ;SET ROM ADDR TO POINT TO LOC WITH
1122 000545 0 064211 3 2 0 10 11 MOVB DFRMAD ;"ROM 00"=0
1123 000546 0 002001 0 1 0 001 LDBR DXHISP ;SET "DX HIGH SPEED"
1124 000547 0 064031 3 2 0 01 11 MOVB REG1
1125 000550 0 002054 0 1 0 054 GOSUB SWEX ;GO SET "SLVE WOR END XFER"
1126 000551 0 177631 7 7 3 11 11
1127 000552 0 022003 1 1 0 00 03 DATI REG3,BR ;READ REG 3
1128 000553 0 014000 0 6 0 000 SHR ;RIGHT ADJUST "NOT MSTR END XFER" BIT
1129 000554 0 014000 0 6 0 000 SHR
1130 000555 0 104557 4 2 0557 JMPB0 .+2 ;JUMP IF SET, SHOULDN'T BE
1131 000556 0 100560 4 0 0560 JMP .+2 ;ELSE, OKAY
1132 ERROR MEX1,"MSTR END XFER" DID NOT SET,^_
1133 000557 0 116104 4 7 0104 DIAG SET "MEX ON FEX" AND "FMTR END XFER"
1134
1135 ERLOOP MEX1 ^SALL
1136 000560 0 002003 0 1 0 003
1137 000561 0 116141 4 7 0141
1138 000562 0 114537 4 6 0537
1139 ;*CLEAR "MEX ON FEX" BIT.
1140 ;*CHECK THAT "MSTR END XFER" IS CLEARED.
1141
1142 000563 0 002001 0 1 0 001 LDBR RMADR8 ;CLEAR "MEX ON FEX"
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 3-2
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
1143 000564 0 064051 3 2 0 02 11 MOVB REG2
1144 000565 0 000000 0 0 0 000 NOP ;DELAY BEFORE DOING DATI
1145 000566 0 022003 1 1 0 00 03 DATI REG3,BR ;READ REG 3
1146 000567 0 014000 0 6 0 000 SHR ;RIGHT ADJUST "NOT MSTR END XFER" BIT
1147 000570 0 014000 0 6 0 000 SHR
1148 000571 0 104573 4 2 0573 JMPB0 .+2 ;JUMP IF SET, SHOULD BE
1149 ERROR MEX1,"MSTR END XFER" DID NOT CLEAR,^_
1150 000572 0 116104 4 7 0104 DIAG SET "MSTR END XFER" THEN CLEARED "MEX ON FEX"
1151
1152 ERLOOP MEX1 ^SALL
1153 000573 0 002004 0 1 0 004
1154 000574 0 116141 4 7 0141
1155 000575 0 114537 4 6 0537
1156 ;*SET "MEX ON FEX" BIT.
1157 ;*CLEAR "FMTR END XFER" BY CLEARING "SLVE END XFER".
1158 ;*CHECK THAT "MSTR END XFER" IS CLEARED.
1159
1160 000576 0 002011 0 1 0 011 LDBR RMADR8+MEONFE ;SET "MEX ON FEX"
1161 000577 0 064051 3 2 0 02 11 MOVB REG2
1162 000600 0 002065 0 1 0 065 GOSUB CLRSEX ;GO CLEAR "SLVE WOR END XFER"
1163 000601 0 177631 7 7 3 11 11
1164 000602 0 022003 1 1 0 00 03 DATI REG3,BR ;READ REG 3
1165 000603 0 014000 0 6 0 000 SHR ;RIGHT ADJUST "NOT MSTR END XFER" BIT
1166 000604 0 014000 0 6 0 000 SHR
1167 000605 0 104607 4 2 0607 JMPB0 .+2 ;JUMP IF SET, SHOULD BE
1168 ERROR MEX1,"MSTR END XFER" DID NOT CLEAR,^_
1169 000606 0 116104 4 7 0104 DIAG SET "MSTR END XFER" THEN CLEARED "FMTR END XFER"
1170
1171 ERLOOP MEX1 ^SALL
1172 000607 0 002005 0 1 0 005
1173 000610 0 116141 4 7 0141
1174 000611 0 114537 4 6 0537
1175 000612 0 116222 4 7 0222 REPEAT TST
1176 000613 0 114461 4 6 0461
1177
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 4
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
1178 TEST 228,TEST BYTE COUNTER (BC)
1179 ;***********************************************************************
1180 ;* MCODE5 * TEST 228 * TEST BYTE COUNTER (BC)
1181 ;***********************************************************************
1182 SALL
1183 000614 0 002344 0 1 0 344
1184 000615 0 116045 4 7 0045
1185
1186 000616 TST228: SALL
1187
1188 ;*TEST THAT THE BC INCREMENTS CORRECTLY WHEN A "SET SLVE ACK" PULSE IS
1189 ;*GENERATED.
1190
1191 ;*LOAD TEST DATA INTO THE BC.
1192 ;*SET "SLVE RDY DLY 2".
1193 ;*SET "DIAG SLVE REQ".
1194 ;*CHECK THE BC FOR THE CORRECT INCREMENTED DATA.
1195
1196 000616 0 001000 0 0 2 000 LDMAR 0 ;CLEAR MAR
1197 000617 0 010002 0 4 0 002 LDMEM 2 ;SETUP ADD PNT ROUTINE NUMBER
1198 000620 0 002224 0 1 0 224 GOSUB SETPNT
1199 000621 0 177631 7 7 3 11 11
1200 000622 0 002057 0 1 0 057 LDBR CNTDAT ;SETUP POINTER TO DATA TO LOAD
1201 000623 0 072051 3 5 0 02 11 MOVB AC2
1202 000624 0 002011 0 1 0 011 LDBR CNTCOR ;SETUP POINTER TO CORRECT DATA AFTER
1203 000625 0 072071 3 5 0 03 11 MOVB AC3 ;INCREMENTING
1204 000626 0 002022 0 1 0 022 LDBR ^D18 ;SET LOOP COUNT MINUS 1
1205 000627 0 072031 3 5 0 01 11 MOVB AC1
1206 000630 0 061050 3 0 2 02 10 BCLP: MOV AC2,MAR ;SET MAR TO POINT TO LOAD DATA
1207 000631 0 045571 2 2 3 07 11 MOVMEM BCHI,I ;LOAD HI ORDER BITS AND INC POINTER
1208 000632 0 044151 2 2 0 06 11 MOVMEM BCLO ;LOAD LOW ORDER BITS
1209 000633 0 002000 0 1 0 000 LDBR 0 ;CLEAR "SLVE REQ"
1210 000634 0 064031 3 2 0 01 11 MOVB REG1
1211 000635 0 002100 0 1 0 100 GOSUB DEVRD ;SETUP DEVICE READ
1212 000636 0 177631 7 7 3 11 11
1213 000637 0 064271 3 2 0 13 11 MOVB HSDPIN ;SET "SLVE RDY DLY 2"
1214 000640 0 002004 0 1 0 004 LDBR DSLVRQ ;SET "SLVE REQ"
1215 000641 0 064031 3 2 0 01 11 MOVB REG1
1216 000642 0 000000 0 0 0 000 NOP ;DELAY BEFORE DOING DATI
1217 000643 0 032007 1 5 0 00 07 DATI BCHI,AC0 ;READ HI ORDER BITS
1218 000644 0 032106 1 5 0 04 06 DATI BCLO,AC4 ;READ LOW ORDER BITS
1219 000645 0 002011 0 1 0 011 LDBR 11 ;SELECT MASSBUS INTERFACE
1220 000646 0 066371 3 3 0 17 11 MOVB IOSEL
1221 000647 0 061050 3 0 2 02 10 MOV AC2,MAR ;STORE LOADED DATA FOR
1222 000650 0 047471 2 3 3 03 11 MOVMEM MPGP13,I ;ERROR
1223 000651 0 046051 2 3 0 02 11 MOVMEM MPGP12 ;PRINTOUT
1224 000652 0 062110 3 1 0 04 10 MOV AC4,BR ;STORE ACTUAL DATA FOR
1225 000653 0 066151 3 3 0 06 11 MOVB MPGP16 ;ERROR
1226 000654 0 062010 3 1 0 00 10 MOV AC0,BR ;PRINTOUT
1227 000655 0 066171 3 3 0 07 11 MOVB MPGP17
1228 000656 0 061070 3 0 2 03 10 MOV AC3,MAR ;STORE CORRECT DATA FOR
1229 000657 0 047531 2 3 3 05 11 MOVMEM MPGP15,I ;ERROR
1230 000660 0 046111 2 3 0 04 11 MOVMEM MPGP14 ;PRINTOUT
1231 000661 0 002022 0 1 0 022 LDBR 22 ;SELECT DATA PATH
1232 000662 0 066371 3 3 0 17 11 MOVB IOSEL
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 4-1
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
1233 000663 0 061070 3 0 2 03 10 MOV AC3,MAR ;SET MAR TO CORRECT DATA
1234 000664 0 041417 2 0 3 00 17 OSM AC0,I ;CHECK IF HI ORDER BITS CORRECT
1235 000665 0 114667 4 6 0667 JMPZ .+2 ;JUMP IF CORRECT
1236 000666 0 100671 4 0 0671 JMP BCERR ;ELSE, REPORT ERROR
1237 000667 0 040117 2 0 0 04 17 OSM AC4 ;CHECK IF LOW ORDER BITS CORRECT
1238 000670 0 114672 4 6 0672 JMPZ .+2 ;JUMP IF CORRECT
1239 000671 0 116104 4 7 0104 BCERR: ERROR BCLP,BC DID NOT INCREMENT CORRECTLY,,PNT
1240
1241 ERLOOP BCLP ^SALL
1242 000672 0 002200 0 1 0 200
1243 000673 0 116141 4 7 0141
1244 000674 0 114630 4 6 0630
1245 000675 0 072063 3 5 0 03 03 INCR AC3 ;INC CORRECT DATA POINTER TO
1246 000676 0 072063 3 5 0 03 03 INCR AC3 ;NEXT VALUE
1247 000677 0 072043 3 5 0 02 03 INCR AC2 ;INC LOAD DATA POINTER TO
1248 000700 0 072043 3 5 0 02 03 INCR AC2 ;NEXT VALUE
1249 000701 0 072027 3 5 0 01 07 DECR AC1 ;DEC LOOP COUNT
1250 000702 0 114704 4 6 0704 JMPZ .+2 ;JUMP IF DONE
1251 000703 0 100630 4 0 0630 JMP BCLP ;ELSE, CONTINUE
1252
1253 000704 0 116222 4 7 0222 REPEAT TST
1254 000705 0 114616 4 6 0616
1255
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 5
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
1256 TEST 229,TEST "BC OF FLAG"
1257 ;***********************************************************************
1258 ;* MCODE5 * TEST 229 * TEST "BC OF FLAG"
1259 ;***********************************************************************
1260 SALL
1261 000706 0 002345 0 1 0 345
1262 000707 0 116045 4 7 0045
1263
1264 000710 TST229: SALL
1265
1266 ;*CLEAR ALL REG 0 FLAGS.
1267 ;*LOAD BC WITH ALL ONES AND CLOCK IT.
1268 ;*CHECK THAT "BC OF FLAG" IS SET.
1269
1270 000710 0 064011 3 2 0 00 11 MOVB REG0 ;WRITE REG 0 TO CLEAR FLAGS
1271 000711 0 002377 0 1 0 377 LDBR 377 ;FILL THE BC
1272 000712 0 064171 3 2 0 07 11 MOVB BCHI
1273 000713 0 064151 3 2 0 06 11 MOVB BCLO
1274 000714 0 002000 0 1 0 000 LDBR 0
1275 000715 0 064031 3 2 0 01 11 MOVB REG1 ;CLEAR "DIAG SLVE REQ"
1276 000716 0 002100 0 1 0 100 GOSUB DEVRD ;SETUP DEVICE READ
1277 000717 0 177631 7 7 3 11 11
1278 000720 0 064271 3 2 0 13 11 MOVB HSDPIN ;SET "SLVE RDY DLY 2"
1279 000721 0 002004 0 1 0 004 LDBR DSLVRQ ;SET "DIAG SLVE REQ"
1280 000722 0 064031 3 2 0 01 11 MOVB REG1
1281 000723 0 000000 0 0 0 000 NOP ;DELAY BEFORE DOING DATI
1282 000724 0 032000 1 5 0 00 00 DATI REG0,AC0 ;READ REG 0
1283 000725 0 002373 0 1 0 373 LDBR 373 ;SET MASK OF ALL BUT "BC OF FLAG" BIT
1284 000726 0 060014 3 0 0 00 14 LORB AC0 ;IF BIT IS SET, RESULT IS ALL ONES
1285 000727 0 114731 4 6 0731 JMPZ .+2 ;JUMP IF SET, SHOULD BE
1286 ERROR TST,"BC OF FLAG" DID NOT SET,^_
1287 000730 0 116104 4 7 0104 DIAG LOADED BC WITH ALL ONES THEN SET "DIAG SLVE REQ"
1288
1289 ERLOOP TST ^SALL
1290 000731 0 002000 0 1 0 000
1291 000732 0 116141 4 7 0141
1292 000733 0 114710 4 6 0710
1293 ;*LOAD ALL ZEROS INTO THE BC THEN CLOCK IT.
1294 ;*CHECK THAT THE "BC OF FLAG" STAYS SET.
1295
1296 000734 0 002000 0 1 0 000 LDBR 0 ;CLEAR THE BC
1297 000735 0 064171 3 2 0 07 11 MOVB BCHI
1298 000736 0 064151 3 2 0 06 11 MOVB BCLO
1299 000737 0 064031 3 2 0 01 11 MOVB REG1 ;CLEAR "DIAG SLVE REQ"
1300 000740 0 002100 0 1 0 100 GOSUB DEVRD ;SETUP DEVICE READ
1301 000741 0 177631 7 7 3 11 11
1302 000742 0 064271 3 2 0 13 11 MOVB HSDPIN ;SET "SLVE RDY DLY 2"
1303 000743 0 002004 0 1 0 004 LDBR DSLVRQ ;SET "DIAG SLVE REQ"
1304 000744 0 064031 3 2 0 01 11 MOVB REG1
1305 000745 0 000000 0 0 0 000 NOP ;DELAY BEFORE DOING DATI
1306 000746 0 032000 1 5 0 00 00 DATI REG0,AC0 ;READ REG 0
1307 000747 0 002373 0 1 0 373 LDBR 373 ;SET MASK OF ALL BUT "BC OF FLAG" BIT
1308 000750 0 060014 3 0 0 00 14 LORB AC0 ;IF BIT IS SET, RESULT IS ALL ONES
1309 000751 0 114753 4 6 0753 JMPZ .+2 ;JUMP IF STILL SET, SHOULD BE
1310 ERROR TST,"BC OF FLAG" DID NOT STAY SET,^_
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MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
1311 <DIAG SET "BC OF FLAG" THEN LOADED BC WITH ZEROS AND
1312 000752 0 116104 4 7 0104 SET "DIAG SLVE REQ">
1313
1314 ERLOOP TST ^SALL
1315 000753 0 002001 0 1 0 001
1316 000754 0 116141 4 7 0141
1317 000755 0 114710 4 6 0710
1318 ;*WRITE REG 0.
1319 ;*CHECK THAT "BC OF FLAG" IS CLEARED.
1320
1321 000756 0 064011 3 2 0 00 11 MOVB REG0 ;WRITE REG 0 TO CLEAR FLAGS
1322 000757 0 002373 0 1 0 373 LDBR 373 ;SET MASK OF ALL BUT "BC OF FLAG"
1323 000760 0 072011 3 5 0 00 11 MOVB AC0 ;MOVE MASK TO AC0
1324 000761 0 022000 1 1 0 00 00 DATI REG0,BR ;READ REG 0
1325 000762 0 060012 3 0 0 00 12 LORCB AC0 ;IF BIT CLEARED, RESULT IS ALL ONES
1326 000763 0 114765 4 6 0765 JMPZ .+2 ;JUMP IF CLEARED
1327 ERROR TST,"BC OF FLAG" DID NOT CLEAR,^_
1328 000764 0 116104 4 7 0104 DIAG SET "BC OF FLAG" THEN WROTE REG 0
1329
1330 ERLOOP TST ^SALL
1331 000765 0 002002 0 1 0 002
1332 000766 0 116141 4 7 0141
1333 000767 0 114710 4 6 0710
1334 ;*LOAD BC WITH SELECTED DATA PATTERNS THEN CLOCK IT.
1335 ;*CHECK THAT "BC OF FLAG" IS NOT SET.
1336
1337 000770 0 001001 0 0 2 001 BCOF1: LDMAR CTR1 ;SET MAR TO LOAD DATA
1338 000771 0 002034 0 1 0 034 GOSUB BCFTST ;GO LOAD BC AND CLOCK IT
1339 000772 0 177631 7 7 3 11 11
1340 000773 0 114775 4 6 0775 JMPZ .+2 ;JUMP IF CLEAR
1341 ERROR BCOF1,"BC OF FLAG" SET WHEN IT SHOULDN'T HAVE,^_
1342 000774 0 116104 4 7 0104 DIAG LOADED BC WITH 177760 THEN SET "DIAG SLVE REQ"
1343
1344 ERLOOP BCOF1 ^SALL
1345 000775 0 002003 0 1 0 003
1346 000776 0 116141 4 7 0141
1347 000777 0 114770 4 6 0770
1348 001000 0 001003 0 0 2 003 BCOF2: LDMAR CTR2 ;SET MAR TO LOAD DATA
1349 001001 0 002034 0 1 0 034 GOSUB BCFTST ;GO LOAD BC AND CLOCK IT
1350 001002 0 177631 7 7 3 11 11
1351 001003 0 115005 4 6 1005 JMPZ .+2 ;JUMP IF CLEAR
1352 ERROR BCOF1,"BC OF FLAG" SET WHEN IT SHOULDN'T HAVE,^_
1353 001004 0 116104 4 7 0104 DIAG LOADED BC WITH 177417 THEN SET "DIAG SLVE REQ"
1354
1355 ERLOOP BCOF1 ^SALL
1356 001005 0 002004 0 1 0 004
1357 001006 0 116141 4 7 0141
1358 001007 0 114770 4 6 0770
1359 001010 0 001005 0 0 2 005 BCOF3: LDMAR CTR3 ;SET MAR TO LOAD DATA
1360 001011 0 002034 0 1 0 034 GOSUB BCFTST ;GO LOAD BC AND CLOCK IT
1361 001012 0 177631 7 7 3 11 11
1362 001013 0 115015 4 6 1015 JMPZ .+2 ;JUMP IF CLEAR
1363 ERROR BCOF1,"BC OF FLAG" SET WHEN IT SHOULDN'T HAVE,^_
1364 001014 0 116104 4 7 0104 DIAG LOADED BC WITH 170377 THEN SET "DIAG SLVE REQ"
1365
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 5-2
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
1366 ERLOOP BCOF1 ^SALL
1367 001015 0 002005 0 1 0 005
1368 001016 0 116141 4 7 0141
1369 001017 0 114770 4 6 0770
1370 001020 0 001007 0 0 2 007 BCOF4: LDMAR CTR4 ;SET MAR TO LOAD DATA
1371 001021 0 002034 0 1 0 034 GOSUB BCFTST ;GO LOAD BC AND CLOCK IT
1372 001022 0 177631 7 7 3 11 11
1373 001023 0 115025 4 6 1025 JMPZ .+2 ;JUMP IF CLEAR
1374 ERROR BCOF1,"BC OF FLAG" SET WHEN IT SHOULDN'T HAVE,^_
1375 001024 0 116104 4 7 0104 DIAG LOADED BC WITH 7777 THEN SET "DIAG SLVE REQ"
1376
1377 ERLOOP BCOF1 ^SALL
1378 001025 0 002006 0 1 0 006
1379 001026 0 116141 4 7 0141
1380 001027 0 114770 4 6 0770
1381 001030 0 116222 4 7 0222 REPEAT TST
1382 001031 0 114710 4 6 0710
1383
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 6
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
1384 TEST 230,TEST GENERATION OF "SLVE END XFER"
1385 ;***********************************************************************
1386 ;* MCODE5 * TEST 230 * TEST GENERATION OF "SLVE END XFER"
1387 ;***********************************************************************
1388 SALL
1389 001032 0 002346 0 1 0 346
1390 001033 0 116045 4 7 0045
1391
1392 001034 TST230: SALL
1393
1394 ;*TEST THAT "SLVE END XFER" IS GENERATED WHEN "SLVE END XFER ON BC OVERFLOW" IS
1395 ;*SET AND "BC OF FLAG" SETS.
1396
1397 ;*CLEAR "SEX ON BC OVERFLOW" BIT.
1398 ;*GENERATE "BC OF FLAG".
1399 ;*CHECK THAT "SLVE END XFER" IS NOT SET.
1400
1401 001034 0 002377 0 1 0 377 LDBR 377 ;FILL BYTE COUNTER
1402 001035 0 064151 3 2 0 06 11 MOVB BCLO
1403 001036 0 064171 3 2 0 07 11 MOVB BCHI
1404 001037 0 002000 0 1 0 000 LDBR 0
1405 001040 0 064031 3 2 0 01 11 MOVB REG1 ;CLEAR "SLVE REQ"
1406 001041 0 064051 3 2 0 02 11 MOVB REG2 ;CLEAR "SEX ON BC"
1407 001042 0 002100 0 1 0 100 GOSUB DEVRD ;SETUP DEVICE READ
1408 001043 0 177631 7 7 3 11 11
1409 001044 0 064271 3 2 0 13 11 MOVB HSDPIN ;SET "SLVE RDY DLY 2"
1410 001045 0 002004 0 1 0 004 LDBR DSLVRQ ;SET "SLVE REQ" TO SET "BC OF FLAG"
1411 001046 0 064031 3 2 0 01 11 MOVB REG1 ;AND CLEAR "SEX ON BC" BIT
1412 001047 0 000000 0 0 0 000 NOP ;DELAY BEFORE DOING DATI
1413 001050 0 022003 1 1 0 00 03 DATI REG3,BR ;READ REG3
1414 001051 0 014000 0 6 0 000 SHR ;MOVE "NOT SLVE END XFER" INTO BIT 0
1415 001052 0 105054 4 2 1054 JMPB0 .+2 ;JUMP IF SET (SLVE END XFER=0)
1416 ERROR TST,"SLVE END XFER" SET WHEN IT SHOULDN'T HAVE,^_
1417 001053 0 116104 4 7 0104 DIAG CLEARED "SEX ON BC" AND SET "BC OF FLAG"
1418
1419 ERLOOP TST ^SALL
1420 001054 0 002000 0 1 0 000
1421 001055 0 116141 4 7 0141
1422 001056 0 115034 4 6 1034
1423 ;*SET "SEX ON BC OVERFLOW" BIT.
1424 ;*CHECK THAT "SLVE END XFER" IS SET.
1425
1426 001057 0 002002 0 1 0 002 LDBR SEBCOV ;SET "SEX ON BC" BIT
1427 001060 0 064051 3 2 0 02 11 MOVB REG2
1428 001061 0 000000 0 0 0 000 NOP ;DELAY BEFORE DOING DATI
1429 001062 0 022003 1 1 0 00 03 DATI REG3,BR ;READ REG3
1430 001063 0 014000 0 6 0 000 SHR ;MOVE "NOT SLVE END XFER" INTO BIT 0
1431 001064 0 105066 4 2 1066 JMPB0 .+2 ;JUMP IF SET (SLVE END XFER=0)
1432 001065 0 101067 4 0 1067 JMP .+2 ;ELSE, OKAY - SHOULD BE = 1
1433 ERROR TST,"SLVE END XFER" DID NOT SET,^_
1434 001066 0 116104 4 7 0104 DIAG SET "BC OF FLAG" THEN SET "SEX ON BC"
1435
1436 ERLOOP TST ^SALL
1437 001067 0 002001 0 1 0 001
1438 001070 0 116141 4 7 0141
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 6-1
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
1439 001071 0 115034 4 6 1034
1440 ;*WRITE REG 0 TO CLEAR "BC OF FLAG".
1441 ;*CHECK THAT "SLVE END XFER" IS CLEARED.
1442
1443 001072 0 064011 3 2 0 00 11 MOVB REG0 ;CLEAR "BC OF FLAG"
1444 001073 0 000000 0 0 0 000 NOP ;DELAY BEFORE DOING DATI
1445 001074 0 022003 1 1 0 00 03 DATI REG3,BR ;READ REG3
1446 001075 0 014000 0 6 0 000 SHR ;MOVE "NOT SLVE END XFER" INTO BIT 0
1447 001076 0 105100 4 2 1100 JMPB0 .+2 ;JUMP IF SET (SLVE END XFER=0)
1448 ERROR TST,"SLVE END XFER" DID NOT CLEAR,^_
1449 001077 0 116104 4 7 0104 DIAG SET "SLVE END XFER" THEN CLEARED "BC OF FLAG"
1450
1451 ERLOOP TST ^SALL
1452 001100 0 002002 0 1 0 002
1453 001101 0 116141 4 7 0141
1454 001102 0 115034 4 6 1034
1455 001103 0 116222 4 7 0222 REPEAT TST
1456 001104 0 115034 4 6 1034
1457
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 7
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
1458 TEST 231,TEST SRR AND CB AND SLVE BUS DRIVERS
1459 ;***********************************************************************
1460 ;* MCODE5 * TEST 231 * TEST SRR AND CB AND SLVE BUS DRIVERS
1461 ;***********************************************************************
1462 SALL
1463 001105 0 002347 0 1 0 347
1464 001106 0 116045 4 7 0045
1465
1466 001107 TST231: SALL
1467
1468 ;*LOOP DATA PATTERNS FROM THE CB BOARD TO THE SRR TO THE CB REG THEN
1469 ;*TO THE SLVE BUS DRIVERS ONTO THE SLVE DATA LINES.
1470
1471 ;*SETUP CB BOARD LOOPING.
1472 ;*CLEAR CLOCK PHASES AND LOAD ROM ADDR WHERE "ROM 02"=1.
1473 ;*SET "DX HIGH SPEED" AND ENABLE SINGLE STEPPING.
1474 ;*SET "DIR TO MSTR" AND "SLVE RDY DLY 2".
1475 ;*CLOCK DATA PATTERN FROM CB BOARD ONTO SLVE DATA LINES.
1476 ;*GENERATE 3 SINGLE STEP PULSES TO SET "RUN" AND CLOCK SRR.
1477 ;*GENERATE 4 SINGLE STEP PULSES TO CLOCK CB.
1478 ;*CLEAR "DIR TO MSTR".
1479 ;*CLOCK THE SLAVE DATA LINES INTO THE DR REG ON THE CB BOARD.
1480 ;*READ THE DR REG FOR THE CORRECT PATTERN.
1481
1482 001107 0 000401 0 0 1 001 LDMARX 1 ;SET MAR EXT BITS
1483 001110 0 002230 0 1 0 230 GOSUB CBLOOP ;GO SETUP CB BOARD LOOPING
1484 001111 0 177631 7 7 3 11 11
1485 001112 0 002001 0 1 0 001 LDBR RMADR8 ;SET ROM ADDR BIT 8
1486 001113 0 064051 3 2 0 02 11 MOVB REG2
1487 001114 0 002021 0 1 0 021 LDBR ^D17 ;SET LOOP COUNT MINUS 1
1488 001115 0 072031 3 5 0 01 11 MOVB AC1
1489 001116 0 001230 0 0 2 230 LDMAR SDPAT&377 ;SET MAR TO DATA PATTERN ADDR
1490 001117 0 002002 0 1 0 002 LDBR BCLKEN ;CLEAR "DX HIGH SPEED" AND ENABLE BASE CLK
1491 001120 0 064031 3 2 0 01 11 MOVB REG1
1492 001121 0 002324 0 1 0 324 LDBR CC4 ;SET ROM ADDR TO POINT TO LOC WITH
1493 001122 0 064211 3 2 0 10 11 MOVB DFRMAD ;"ROM 02" =1
1494 001123 0 002217 0 1 0 217 GOSUB ENSS ;SET "DX HIGH SPEED" AND ENABLE SINGLE STEP
1495 001124 0 177631 7 7 3 11 11
1496 001125 0 002100 0 1 0 100 SDLOOP: GOSUB DEVRD ;SETUP DEVICE READ
1497 001126 0 177631 7 7 3 11 11
1498 001127 0 064271 3 2 0 13 11 MOVB HSDPIN ;TO SET "SLVE RDY DLY 2"
1499 001130 0 002240 0 1 0 240 GOSUB CLKDT ;GO CLOCK DATA ONTO SLAVE DATA LINES
1500 001131 0 177631 7 7 3 11 11
1501 001132 0 002135 0 1 0 135 GOSUB PULSE3 ;CLOCK DATA INTO SRR AND SET RUN
1502 001133 0 177631 7 7 3 11 11
1503 001134 0 002134 0 1 0 134 GOSUB PULSE4 ;CLOCK DATA INTO CB AND CLEAR PHASES
1504 001135 0 177631 7 7 3 11 11
1505 001136 0 002105 0 1 0 105 GOSUB DEVWR ;GO SETUP DEVICE WRITE
1506 001137 0 177631 7 7 3 11 11
1507 001140 0 002257 0 1 0 257 GOSUB RDDATA ;GO READ DATA OFF SLVE DATA LINES
1508 001141 0 177631 7 7 3 11 11
1509 001142 0 040017 2 0 0 00 17 OSM AC0 ;COMPARE IT TO DATA WRIITEN
1510 001143 0 115145 4 6 1145 JMPZ .+2 ;JUMP IF CORRECT
1511 ERRORM SDLOOP,LOOPED DATA IS INCORRECT,^_
1512 <DIAG CLOCKED DATA INTO CB REG WITH "DIR TO MSTR" SET THEN
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 7-1
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
1513 001144 0 116104 4 7 0104 CLEARED "DIR TO MSTR" AND READ SLAVE DATA LINES>
1514
1515 ERLOOP SDLOOP ^SALL
1516 001145 0 002100 0 1 0 100
1517 001146 0 116145 4 7 0145
1518 001147 0 115125 4 6 1125
1519 001150 0 073427 3 5 3 01 07 DECR AC1,I ;DEC LOOP COUNT AND INC PATTERN ADDR
1520 001151 0 115153 4 6 1153 JMPZ .+2 ;JUMP IF DONE
1521 001152 0 101125 4 0 1125 JMP SDLOOP ;ELSE, CONTINUE
1522
1523 001153 0 116222 4 7 0222 REPEAT TST
1524 001154 0 115107 4 6 1107
1525
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 8
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
1526 TEST 232,TEST CLEARING OF SRR AND CB
1527 ;***********************************************************************
1528 ;* MCODE5 * TEST 232 * TEST CLEARING OF SRR AND CB
1529 ;***********************************************************************
1530 SALL
1531 001155 0 002350 0 1 0 350
1532 001156 0 116045 4 7 0045
1533
1534 001157 TST232: SALL
1535
1536 ;*SET "DIR TO MSTR".
1537 ;*USING CB BOARD LOOPING AND SINGLE STEPPING, CLOCK ALL ONES INTO
1538 ;*THE SRR AND CB.
1539 ;*DO A HS DP INIT.
1540 ;*CLEAR "DIR TO MSTR".
1541 ;*CLOCK THE SLAVE DATA LINES INTO THE DR REG ON THE CB BOARD.
1542 ;*CHECK THE DR REG FOR ALL ZEROS.
1543
1544 001157 0 002230 0 1 0 230 GOSUB CBLOOP ;SETUP CB BOARD LOOPING
1545 001160 0 177631 7 7 3 11 11
1546 001161 0 002001 0 1 0 001 LDBR RMADR8 ;SET ROM ADDR BIT 8
1547 001162 0 064051 3 2 0 02 11 MOVB REG2
1548 001163 0 002002 0 1 0 002 LDBR BCLKEN ;CLEAR CLOCK PHASES
1549 001164 0 064031 3 2 0 01 11 MOVB REG1
1550 001165 0 002324 0 1 0 324 LDBR CC4 ;SET ROM ADDR TO LOC WITH
1551 001166 0 064211 3 2 0 10 11 MOVB DFRMAD ;"ROM 02"=1
1552 001167 0 002217 0 1 0 217 GOSUB ENSS ;SET "DX HIGH SPEED" AND ENABLE SINGLE STEP
1553 001170 0 177631 7 7 3 11 11
1554 001171 0 002100 0 1 0 100 GOSUB DEVRD ;SET DEVICE READ
1555 001172 0 177631 7 7 3 11 11
1556 001173 0 064271 3 2 0 13 11 MOVB HSDPIN ;SET "SLVE RDY DLY 2"
1557 001174 0 010377 0 4 0 377 LDMEM -1 ;CLOCK ALL ONES DATA ONTO
1558 001175 0 002244 0 1 0 244 GOSUB CLKDAT ;SLAVE DATA LINES
1559 001176 0 177631 7 7 3 11 11
1560 001177 0 002135 0 1 0 135 GOSUB PULSE3 ;CLOCK DATA INTO SRR AND SET RUN
1561 001200 0 177631 7 7 3 11 11
1562 001201 0 002134 0 1 0 134 GOSUB PULSE4 ;CLOCK DATA INTO CB AND CLEAR PHASES
1563 001202 0 177631 7 7 3 11 11
1564 001203 0 064271 3 2 0 13 11 MOVB HSDPIN ;CLEAR SRR AND CLOCK ZEROS INTO CB
1565 001204 0 002105 0 1 0 105 GOSUB DEVWR ;SETUP DEVICE WRITE
1566 001205 0 177631 7 7 3 11 11
1567 001206 0 002257 0 1 0 257 GOSUB RDDATA ;READ SLAVE DATA LINES
1568 001207 0 177631 7 7 3 11 11
1569 001210 0 040017 2 0 0 00 17 OSM AC0 ;CHECK FOR IT
1570 001211 0 115213 4 6 1213 JMPZ .+2 ;JUMP IF CORRECT
1571 ERRORM TST,"HS DP INIT" DID NOT CLOCK ALL ZEROS INTO CB,^_
1572 <DIAG LOADED ALL ONES INTO SRR AND CB THEN
1573 001212 0 116104 4 7 0104 DID A HS DP INIT>
1574
1575 ERLOOP TST ^SALL
1576 001213 0 002100 0 1 0 100
1577 001214 0 116145 4 7 0145
1578 001215 0 115157 4 6 1157
1579 ;*SET "DIR TO MSTR".
1580 ;*USING CB BOARD LOOPING AND SINGLE STEPPING, CLOCK ALL ONES INTO THE SRR.
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 8-1
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
1581 ;*SET "SLVE END XFER" ON THE CB BOARD.
1582 ;*CLOCK THE CB.
1583 ;*CLEAR "DIR TO MSTR"
1584 ;*CLOCK THE SLAVE DATA LINES INTO THE DR REG ON THE CB BOARD.
1585 ;*CHECK THE DR REG FOR ALL ZEROS.
1586
1587 001216 0 002100 0 1 0 100 SRR1: GOSUB DEVRD ;SET DEVICE READ
1588 001217 0 177631 7 7 3 11 11
1589 001220 0 064271 3 2 0 13 11 MOVB HSDPIN ;SET "SLVE RDY DLY 2"
1590 001221 0 010377 0 4 0 377 LDMEM -1 ;CLOCK ALL ONES DATA ONTO
1591 001222 0 002244 0 1 0 244 GOSUB CLKDAT ;SLAVE DATA LINES
1592 001223 0 177631 7 7 3 11 11
1593 001224 0 002135 0 1 0 135 GOSUB PULSE3 ;CLOCK DATA INTO SRR AND SET RUN
1594 001225 0 177631 7 7 3 11 11
1595 001226 0 002054 0 1 0 054 GOSUB SWEX ;GO SET "SLVE END XFER" (CLEARS SRR)
1596 001227 0 177631 7 7 3 11 11
1597 001230 0 002134 0 1 0 134 GOSUB PULSE4 ;CLOCK DATA INTO CB AND CLEAR PHASES
1598 001231 0 177631 7 7 3 11 11
1599 001232 0 002105 0 1 0 105 GOSUB DEVWR ;SETUP DEVICE WRITE
1600 001233 0 177631 7 7 3 11 11
1601 001234 0 002257 0 1 0 257 GOSUB RDDATA ;READ SLAVE DATA LINES
1602 001235 0 177631 7 7 3 11 11
1603 001236 0 040017 2 0 0 00 17 OSM AC0 ;CHECK FOR IT
1604 001237 0 115241 4 6 1241 JMPZ .+2 ;JUMP IF CORRECT
1605 ERRORM SRR1,"SLVE END XFER" DID NOT CLEAR SRR,^_
1606 <DIAG LOADED ALL ONES INTO SRR THEN SET "SLVE END XFER"
1607 001240 0 116104 4 7 0104 AND CLOCKED CB>
1608
1609 ERLOOP SRR1 ^SALL
1610 001241 0 002101 0 1 0 101
1611 001242 0 116145 4 7 0145
1612 001243 0 115216 4 6 1216
1613 001244 0 002065 0 1 0 065 GOSUB CLRSEX ;CLEAR "SLVE END XFER"
1614 001245 0 177631 7 7 3 11 11
1615 001246 0 116222 4 7 0222 REPEAT TST
1616 001247 0 115157 4 6 1157
1617
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 9
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
1618 TEST 233,TEST "SLVE PE"
1619 ;***********************************************************************
1620 ;* MCODE5 * TEST 233 * TEST "SLVE PE"
1621 ;***********************************************************************
1622 SALL
1623 001250 0 002351 0 1 0 351
1624 001251 0 116045 4 7 0045
1625
1626 001252 TST233: SALL
1627
1628 ;*TEST THAT "SLVE PE" SETS WHEN EVEN PARITY DATA IS CLOCKED INTO THE CB
1629 ;*AND DOES NOT SET FOR ODD PARITY.
1630
1631 ;*SET "DIR TO MSTR".
1632 ;*CLOCK ODD PARITY DATA PATTERNS FROM CB BOARD INTO CB.
1633 ;*CHECK THAT "SLVE PE" IS NOT SET.
1634
1635 001252 0 010003 0 4 0 003 LDMEM 3 ;SETUP ADDITIONAL PNT ROUTINE NUMBER
1636 001253 0 002224 0 1 0 224 GOSUB SETPNT
1637 001254 0 177631 7 7 3 11 11
1638 001255 0 000401 0 0 1 001 LDMARX 1 ;SET MAR EXT BITS
1639 001256 0 002230 0 1 0 230 GOSUB CBLOOP ;GO SETUP CB BOARD LOOPING
1640 001257 0 177631 7 7 3 11 11
1641 001260 0 002001 0 1 0 001 LDBR RMADR8 ;SET ROM ADDR BIT 8
1642 001261 0 064051 3 2 0 02 11 MOVB REG2
1643 001262 0 002021 0 1 0 021 LDBR ^D17 ;SET LOOP COUNT MINUS 1
1644 001263 0 072031 3 5 0 01 11 MOVB AC1
1645 001264 0 001230 0 0 2 230 LDMAR SDPAT&377 ;SET MAR TO DATA PATTERN ADDR
1646 001265 0 002002 0 1 0 002 LDBR BCLKEN ;CLEAR "DX HIGH SPEED" AND ENABLE BASE CLK
1647 001266 0 064031 3 2 0 01 11 MOVB REG1
1648 001267 0 002324 0 1 0 324 LDBR CC4 ;SET ROM ADDR TO POINT TO LOC WITH
1649 001270 0 064211 3 2 0 10 11 MOVB DFRMAD ;"ROM 02" =1
1650 001271 0 002217 0 1 0 217 GOSUB ENSS ;SET "DX HIGH SPEED" AND ENABLE SINGLE STEP
1651 001272 0 177631 7 7 3 11 11
1652 001273 0 002100 0 1 0 100 SPARLP: GOSUB DEVRD ;SETUP DEVICE READ
1653 001274 0 177631 7 7 3 11 11
1654 001275 0 064271 3 2 0 13 11 MOVB HSDPIN ;TO SET "SLVE RDY DLY 2"
1655 001276 0 002074 0 1 0 074 GOSUB SETDAT ;GO SETUP DATA FOR ERROR PRINTOUT
1656 001277 0 177631 7 7 3 11 11
1657 001300 0 002244 0 1 0 244 GOSUB CLKDAT ;GO CLOCK DATA ONTO SLAVE DATA LINES
1658 001301 0 177631 7 7 3 11 11
1659 001302 0 002135 0 1 0 135 GOSUB PULSE3 ;CLOCK DATA INTO SRR AND SET RUN
1660 001303 0 177631 7 7 3 11 11
1661 001304 0 002134 0 1 0 134 GOSUB PULSE4 ;CLOCK DATA INTO CB AND CLEAR PHASES
1662 001305 0 177631 7 7 3 11 11
1663 001306 0 022016 1 1 0 00 16 DATI REG16,BR ;READ REG 16 FOR "SLVE PE" BIT
1664 001307 0 105311 4 2 1311 JMPB0 .+2 ;JUMP IF SET, SHOULDN'T BE
1665 001310 0 101312 4 0 1312 JMP .+2 ;ELSE, OKAY
1666 ERROR SPARLP,"SLVE PE" SET WHEN IT SHOULDN'T HAVE,^_
1667 001311 0 116104 4 7 0104 DIAG CLOCKED GOOD PARITY DATA INTO CB WITH "DIR TO MSTR" SET,PNT
1668
1669 ERLOOP SPARLP ^SALL
1670 001312 0 002200 0 1 0 200
1671 001313 0 116141 4 7 0141
1672 001314 0 115273 4 6 1273
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 9-1
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
1673 ;*CLEAR "DIR TO MSTR" TO ENABLE SLVE BUS DRIVERS.
1674 ;*SET AND CLEAR "SLVE ACK" ON CB BOARD TO GATE "DP PE FLAG".
1675 ;*CHECK THAT "DP PE FLAG" IS NOT SET.
1676
1677 001315 0 002105 0 1 0 105 GOSUB DEVWR ;SETUP DEVICE WRITE
1678 001316 0 177631 7 7 3 11 11
1679 001317 0 002033 0 1 0 033 LDBR 33 ;SELECT CHANNEL BUS INTERFACE
1680 001320 0 066371 3 3 0 17 11 MOVB IOSEL
1681 001321 0 002002 0 1 0 002 LDBR CLRFLG ;CLEAR "DP PE FLAG"
1682 001322 0 064011 3 2 0 00 11 MOVB CSR0
1683 001323 0 064111 3 2 0 04 11 MOVB SLAK25 ;CLOCK "DP PE FLAG"
1684 001324 0 000000 0 0 0 000 NOP ;DELAY BEFORE DOING DATI
1685 001325 0 032000 1 5 0 00 00 DATI CSR0,AC0 ;READ "DP PE FLAG"
1686 001326 0 002022 0 1 0 022 LDBR 22 ;SELECT DATA PATH
1687 001327 0 066371 3 3 0 17 11 MOVB IOSEL
1688 001330 0 062010 3 1 0 00 10 MOV AC0,BR ;MOVE BIT TO BR FOR TESTING
1689 001331 0 014000 0 6 0 000 SHR ;MOVE BIT TO BIT 4
1690 001332 0 107334 4 3 1334 JMPB4 .+2 ;JUMP IF "DP PE FLAG" SET, SHOULDN'T HAVE
1691 001333 0 101335 4 0 1335 JMP .+2 ;ELSE, OKAY
1692 ERROR SPARLP,"DP PE FLAG" ON CB BOARD SET WHEN IT SHOULDN'T HAVE,^_
1693 <DIAG CLOCKED DATA INTO CB REG THEN CLEARED "DIR TO MSTR"
1694 001334 0 116104 4 7 0104 AND SET "SLVE ACK" ON CB BOARD>,PNT
1695
1696 ERLOOP SPARLP ^SALL
1697 001335 0 002201 0 1 0 201
1698 001336 0 116141 4 7 0141
1699 001337 0 115273 4 6 1273
1700 001340 0 073427 3 5 3 01 07 DECR AC1,I ;DEC LOOP COUNT AND INC PATTERN ADDR
1701 001341 0 115343 4 6 1343 JMPZ .+2 ;JUMP IF DONE
1702 001342 0 101273 4 0 1273 JMP SPARLP ;ELSE, CONTINUE
1703
1704 ;*SET "DIR TO MSTR".
1705 ;*CLOCK ALL ZEROS EVEN PARITY DATA INTO CB FROM CB BOARD.
1706 ;*CHECK THAT "SLVE PE" IS SET.
1707 ;*SET "DIR TO MSTR".
1708
1709 001343 0 002100 0 1 0 100 SPAR1: GOSUB DEVRD ;SET DEVICE READ
1710 001344 0 177631 7 7 3 11 11
1711 001345 0 064271 3 2 0 13 11 MOVB HSDPIN ;SET "SLVE RDY DLY 2"
1712 001346 0 002033 0 1 0 033 LDBR 33 ;SELECT CHANNEL BUS INTERFACE
1713 001347 0 066371 3 3 0 17 11 MOVB IOSEL
1714 001350 0 002005 0 1 0 005 LDBR LOOPEN+CHANL ;SET LOOP ENABLE AND CLEAR EV PAR BIT
1715 001351 0 064031 3 2 0 01 11 MOVB CSR1 ;AND CHANNEL MODE
1716 001352 0 002377 0 1 0 377 LDBR -1 ;CLOCK ALL ZEROS (INCLUDING PARITY BIT)
1717 001353 0 002251 0 1 0 251 GOSUB CLKIT ;ONTO SLAVE DATA LINES
1718 001354 0 177631 7 7 3 11 11
1719 001355 0 002135 0 1 0 135 GOSUB PULSE3 ;CLOCK DATA INTO SRR AND SET RUN
1720 001356 0 177631 7 7 3 11 11
1721 001357 0 002134 0 1 0 134 GOSUB PULSE4 ;CLOCK DATA INTO CB AND CLEAR PHASES
1722 001360 0 177631 7 7 3 11 11
1723 001361 0 022016 1 1 0 00 16 DATI REG16,BR ;READ REG 16 FOR "SLVE PE"
1724 001362 0 105364 4 2 1364 JMPB0 .+2 ;JUMP IF SET, SHOULD BE
1725 ERROR SPAR1,"SLVE PE" DID NOT SET,^_
1726 <DIAG CLOCKED EVEN PARITY DATA (ALL ZER0S)
1727 001363 0 116104 4 7 0104 INTO CB REG WITH "DIR TO MSTR" SET>
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 9-2
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
1728
1729 ERLOOP SPAR1 ^SALL
1730 001364 0 002002 0 1 0 002
1731 001365 0 116141 4 7 0141
1732 001366 0 115343 4 6 1343
1733 001367 0 001000 0 0 2 000 LDMAR 0 ;CLEAR MAR
1734 001370 0 002100 0 1 0 100 SPAR2: GOSUB DEVRD ;SET DEVICE READ
1735 001371 0 177631 7 7 3 11 11
1736 001372 0 064271 3 2 0 13 11 MOVB HSDPIN ;SET "SLVE RDY DLY 2"
1737 001373 0 010377 0 4 0 377 LDMEM -1 ;CLOCK ALL ONES DATA ONTO
1738 001374 0 002244 0 1 0 244 GOSUB CLKDAT ;SLAVE DATA LINES
1739 001375 0 177631 7 7 3 11 11
1740 001376 0 002054 0 1 0 054 GOSUB SWEX ;GO SET "SLVE END XFER" (CLEARS SRR)
1741 001377 0 177631 7 7 3 11 11
1742 001400 0 002135 0 1 0 135 GOSUB PULSE3 ;CLOCK DATA INTO SRR AND SET RUN
1743 001401 0 177631 7 7 3 11 11
1744 001402 0 002134 0 1 0 134 GOSUB PULSE4 ;CLOCK DATA INTO CB AND CLEAR PHASES
1745 001403 0 177631 7 7 3 11 11
1746 001404 0 022016 1 1 0 00 16 DATI REG16,BR ;READ REG 16 FOR "SLVE PE" BIT
1747 001405 0 105407 4 2 1407 JMPB0 .+2 ;JUMP IF SET, SHOULDN'T BE
1748 001406 0 101410 4 0 1410 JMP .+2 ;ELSE, OKAY
1749 ERROR SPAR2,"SLVE PE" SET WHEN IT SHOULDN'T HAVE,^_
1750 001407 0 116104 4 7 0104 DIAG SET "SLVE END XFER" THEN CLOCKED CB WITH "DIR TO MSTR" SET
1751
1752 ERLOOP SPAR2 ^SALL
1753 001410 0 002003 0 1 0 003
1754 001411 0 116141 4 7 0141
1755 001412 0 115370 4 6 1370
1756 001413 0 002065 0 1 0 065 GOSUB CLRSEX ;CLEAR "SLVE END XFER"
1757 001414 0 177631 7 7 3 11 11
1758 001415 0 116222 4 7 0222 REPEAT TST
1759 001416 0 115252 4 6 1252
1760
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 10
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
1761 TEST 234,TEST "DP PE FLAG" USING "SLVE PE"
1762 ;***********************************************************************
1763 ;* MCODE5 * TEST 234 * TEST "DP PE FLAG" USING "SLVE PE"
1764 ;***********************************************************************
1765 SALL
1766 001417 0 002352 0 1 0 352
1767 001420 0 116045 4 7 0045
1768
1769 001421 TST234: SALL
1770
1771 ;*SETUP CB BOARD LOOPING AND CLEAR CLOCK PHASES.
1772 ;*LOAD ROM ADDR WHERE "ROM 02"=1.
1773 ;*SET "DX HIGH SPEED" AND ENABLE SINGLE STEP.
1774 ;*SET "DIR TO MSTR" AND "SLVE RDY DLY 2".
1775 ;*CLOCK ALL ZEROS, EVEN PARITY DATA ONTO THE SLVE DATA LINES.
1776 ;*GENERATE 3 SINGLE STEP PULSES TO CLOCK THE SRR AND SET "RUN".
1777 ;*GENERATE 3 MORE SINGLE STEP PULSES TO CLOCK THE CB AND SET "SLVE PE".
1778 ;*CHECK THAT "DP PE FLAG" IS NOT SET YET.
1779
1780 001421 0 064011 3 2 0 00 11 MOVB REG0 ;CLEAR FLAGS
1781 001422 0 002230 0 1 0 230 GOSUB CBLOOP ;SETUP CB BOARD LOOPING
1782 001423 0 177631 7 7 3 11 11
1783 001424 0 002002 0 1 0 002 LDBR BCLKEN ;CLEAR CLOCK PHASES
1784 001425 0 064031 3 2 0 01 11 MOVB REG1
1785 001426 0 002001 0 1 0 001 LDBR RMADR8 ;SET ROM ADDR BIT 8
1786 001427 0 064051 3 2 0 02 11 MOVB REG2
1787 001430 0 002324 0 1 0 324 LDBR CC4 ;SET ROM ADDR TO POINT TO LOC WITH
1788 001431 0 064211 3 2 0 10 11 MOVB DFRMAD ;"ROM 02"=1
1789 001432 0 002217 0 1 0 217 GOSUB ENSS ;SET "DX HIGH SPEED" AND ENABLE SINGLE STEP
1790 001433 0 177631 7 7 3 11 11
1791 001434 0 002100 0 1 0 100 GOSUB DEVRD ;SETUP DEVICE READ
1792 001435 0 177631 7 7 3 11 11
1793 001436 0 064271 3 2 0 13 11 MOVB HSDPIN ;SET "SLVE RDY DLY 2"
1794 001437 0 002033 0 1 0 033 LDBR 33 ;SELECT CHANNEL BUS INTERFACE
1795 001440 0 066371 3 3 0 17 11 MOVB IOSEL
1796 001441 0 002005 0 1 0 005 LDBR LOOPEN+CHANL ;SET LOOP ENABLE, CLEAR EV PAR
1797 001442 0 064031 3 2 0 01 11 MOVB CSR1 ;AND SET CHANNEL MODE
1798 001443 0 002377 0 1 0 377 LDBR -1 ;CLOCK ALL ZEROS, EVEN PARITY DATA ONTO
1799 001444 0 002251 0 1 0 251 GOSUB CLKIT ;THE SLVE DATA LINES
1800 001445 0 177631 7 7 3 11 11
1801 001446 0 002135 0 1 0 135 GOSUB PULSE3 ;CLOCK DATA INTO SRR AND SET RUN
1802 001447 0 177631 7 7 3 11 11
1803 001450 0 002135 0 1 0 135 GOSUB PULSE3 ;CLOCK DATA INTO CB
1804 001451 0 177631 7 7 3 11 11
1805 001452 0 022000 1 1 0 00 00 DATI REG0,BR ;READ REG0
1806 001453 0 014000 0 6 0 000 SHR ;MOVE "DP PE FLAG" INTO BIT 0
1807 001454 0 105456 4 2 1456 JMPB0 .+2 ;JUMP IF SET, SHOULDN'T BE
1808 001455 0 101457 4 0 1457 JMP .+2 ;JUMP IF CLEAR
1809 ERROR TST,"DP PE FLAG" SET BEFORE IT SHOULD HAVE,^_
1810 <DIAG SET "CC 2" AND "DIR TO MSTR" AND "SLVE PE" THEN
1811 001456 0 116104 4 7 0104 GENERATED 3 SINGLE STEP PULSES>
1812
1813 ERLOOP TST ^SALL
1814 001457 0 002000 0 1 0 000
1815 001460 0 116141 4 7 0141
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 10-1
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
1816 001461 0 115421 4 6 1421
1817 ;*GENERATE A SINGLE STEP PULSE TO CLOCK "DP PE FLAG".
1818 ;*CHECK THAT IT IS SET.
1819
1820 001462 0 064251 3 2 0 12 11 MOVB CLKPLS ;GEN ANOTHER SINGLE STEP PULSE
1821 001463 0 000000 0 0 0 000 NOP ;DELAY BEFORE DOING DATI
1822 001464 0 022000 1 1 0 00 00 DATI REG0,BR ;READ REG0
1823 001465 0 014000 0 6 0 000 SHR ;MOVE "DP PE FLAG" INTO BIT 0
1824 001466 0 105470 4 2 1470 JMPB0 .+2 ;JUMP IF SET, SHOULD BE
1825 ERROR TST,"DP PE FLAG" DID NOT SET,^_
1826 <DIAG SET "CC 2" AND "DIR TO MSTR" AND "SLVE PE" THEN
1827 001467 0 116104 4 7 0104 GENERATED 4 SINGLE STEP PULSES>
1828
1829 ERLOOP TST ^SALL
1830 001470 0 002001 0 1 0 001
1831 001471 0 116141 4 7 0141
1832 001472 0 115421 4 6 1421
1833 ;*CHECK THAT "DP PE FLAG" GENERATES AN INTERRUPT.
1834
1835 001473 0 102167 4 1 0167 JMPI ZRTN ;JUMP IF INTERRUPT OCCURRED
1836 001474 0 115476 4 6 1476 JMPZ .+2 ;JUMP IF INTERRUPT OCCURRED
1837 001475 0 116104 4 7 0104 ERROR TST,"DP PE FLAG" DID NOT CAUSE INTERRUPT
1838
1839 ERLOOP TST ^SALL
1840 001476 0 002002 0 1 0 002
1841 001477 0 116141 4 7 0141
1842 001500 0 115421 4 6 1421
1843 ;*CLEAR "ROM 02" AND SET "RUN".
1844 ;*GENERATE 4 SINGLE STEP PULSES TO CLOCK "DP PE FLAG".
1845 ;*CHECK THAT "DP PE FLAG" STAYS SET.
1846
1847 001501 0 002000 0 1 0 000 LDBR 0 ;CLEAR "DX HIGH SPEED"
1848 001502 0 064031 3 2 0 01 11 MOVB REG1
1849 001503 0 002320 0 1 0 320 LDBR ZEROS ;CLEAR "CC 2"
1850 001504 0 064211 3 2 0 10 11 MOVB DFRMAD
1851 001505 0 002001 0 1 0 001 LDBR DXHISP ;SET "DX HIGH SPEED"
1852 001506 0 064031 3 2 0 01 11 MOVB REG1
1853 001507 0 064311 3 2 0 14 11 MOVB SETRUN ;SET "RUN"
1854 001510 0 002134 0 1 0 134 GOSUB PULSE4 ;CLOCK "DP PE FLAG" FLOP AGAIN
1855 001511 0 177631 7 7 3 11 11
1856 001512 0 022000 1 1 0 00 00 DATI REG0,BR ;READ REG0
1857 001513 0 014000 0 6 0 000 SHR ;MOVE "DP PE FLAG" INTO BIT 0
1858 001514 0 105516 4 2 1516 JMPB0 .+2 ;JUMP IF SET, SHOULD BE
1859 ERROR TST,"DP PE FLAG" DID NOT STAY SET,^_
1860 <DIAG SET "DP PE FLAG" THEN CLEARED "CC 2" AND
1861 001515 0 116104 4 7 0104 GENERATED 4 SINGLE STEP PULSES>
1862
1863 ERLOOP TST ^SALL
1864 001516 0 002003 0 1 0 003
1865 001517 0 116141 4 7 0141
1866 001520 0 115421 4 6 1421
1867 ;*WRITE REG 0.
1868 ;*CHECK THAT "DP PE FLAG" IS CLEARED.
1869
1870 001521 0 064011 3 2 0 00 11 MOVB REG0 ;CLEAR FLAGS
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 10-2
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
1871 001522 0 000000 0 0 0 000 NOP ;DELAY BEFORE DOING DATI
1872 001523 0 022000 1 1 0 00 00 DATI REG0,BR ;READ REG0
1873 001524 0 014000 0 6 0 000 SHR ;MOVE "DP PE FLAG" INTO BIT 0
1874 001525 0 105527 4 2 1527 JMPB0 .+2 ;JUMP IF SET, SHOULDN'T BE
1875 001526 0 101530 4 0 1530 JMP .+2 ;JUMP IF CLEAR
1876 ERROR TST,"DP PE FLAG" DID NOT CLEAR,^_
1877 001527 0 116104 4 7 0104 DIAG SET "DP PE FLAG" THEN WROTE REG 0
1878
1879 ERLOOP TST ^SALL
1880 001530 0 002004 0 1 0 004
1881 001531 0 116141 4 7 0141
1882 001532 0 115421 4 6 1421
1883 ;*SET "RUN".
1884 ;*GENERATE 4 SINGLE STEP PULSES.
1885 ;*CHECK THAT "DP PE FLAG" IS NOT SET. ("CC 2"=0)
1886
1887 001533 0 064011 3 2 0 00 11 SDDPE1: MOVB REG0 ;CLEAR FLAG
1888 001534 0 064311 3 2 0 14 11 MOVB SETRUN ;SET "RUN"
1889 001535 0 002134 0 1 0 134 GOSUB PULSE4 ;CLOCK "DP PE FLAG" FLOP
1890 001536 0 177631 7 7 3 11 11
1891 001537 0 022000 1 1 0 00 00 DATI REG0,BR ;READ REG0
1892 001540 0 014000 0 6 0 000 SHR ;MOVE "DP PE FLAG" INTO BIT 0
1893 001541 0 105543 4 2 1543 JMPB0 .+2 ;JUMP IF SET, SHOULDN'T BE
1894 001542 0 101544 4 0 1544 JMP .+2 ;JUMP IF CLEAR
1895 ERROR SDDPE1,"DP PE FLAG" SET WHEN IT SHOULDN'T HAVE,^_
1896 <DIAG SET "SLVE PE" AND "DIR TO MSTR" AND CLEARED "CC 2"
1897 001543 0 116104 4 7 0104 THEN GENERATED 4 SINGLE STEP PULSES>
1898
1899 ERLOOP SDDPE1 ^SALL
1900 001544 0 002005 0 1 0 005
1901 001545 0 116141 4 7 0141
1902 001546 0 115533 4 6 1533
1903 ;*SET "DIR TO MSTR" AND "ROM 02".
1904 ;*SET "RUN" AND GENERATE 2 SINGLE STEP PULSES.
1905 ;*CLEAR "DIR TO MSTR".
1906 ;*GENERATE 2 MORE SINGLE STEP PULSES.
1907 ;*CHECK THAT "DP PE FLAG" IS NOT SET.
1908
1909 001547 0 002100 0 1 0 100 SDDPE2: GOSUB DEVRD ;SETUP DEVICE READ
1910 001550 0 177631 7 7 3 11 11
1911 001551 0 064011 3 2 0 00 11 MOVB REG0 ;CLEAR FLAG
1912 001552 0 002000 0 1 0 000 LDBR 0 ;CLEAR "DX HIGH SPEED"
1913 001553 0 064031 3 2 0 01 11 MOVB REG1
1914 001554 0 002324 0 1 0 324 LDBR CC4 ;SET "CC 2"
1915 001555 0 064211 3 2 0 10 11 MOVB DFRMAD
1916 001556 0 002001 0 1 0 001 LDBR DXHISP ;SET "DX HIGH SPEED"
1917 001557 0 064031 3 2 0 01 11 MOVB REG1
1918 001560 0 064311 3 2 0 14 11 MOVB SETRUN ;SET "RUN"
1919 001561 0 002136 0 1 0 136 GOSUB PULSE2 ;CLOCK DATA INTO CB
1920 001562 0 177631 7 7 3 11 11
1921 001563 0 002105 0 1 0 105 GOSUB DEVWR ;SETUP DEVICE WRITE
1922 001564 0 177631 7 7 3 11 11
1923 001565 0 002136 0 1 0 136 GOSUB PULSE2 ;CLOCK "DP PE FLAG" FLOP
1924 001566 0 177631 7 7 3 11 11
1925 001567 0 022000 1 1 0 00 00 DATI REG0,BR ;READ REG0
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 10-3
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
1926 001570 0 014000 0 6 0 000 SHR ;MOVE "DP PE FLAG" INTO BIT 0
1927 001571 0 105573 4 2 1573 JMPB0 .+2 ;JUMP IF SET, SHOULDN'T BE
1928 001572 0 101574 4 0 1574 JMP .+2 ;JUMP IF CLEAR
1929 ERROR SDDPE2,"DP PE FLAG" SET WHEN IT SHOULDN'T HAVE,^_
1930 <DIAG SET "SLVE PE" AND "CC 2" AND CLEARED "DIR TO MSTR" THEN
1931 001573 0 116104 4 7 0104 CLOCKED THE "DP PE FLAG" FLOP>
1932
1933 ERLOOP SDDPE2 ^SALL
1934 001574 0 002006 0 1 0 006
1935 001575 0 116141 4 7 0141
1936 001576 0 115547 4 6 1547
1937 ;*SET "DIR TO MSTR" AND "SLVE RDY DLY 2".
1938 ;*CLOCK ALL ZEROS ODD PARITY DATA ONTO THE SLVE DATA LINES.
1939 ;*GENERATE 3 SINGLE STEP PULSES TO CLOCK THE SRR AND SET "RUN".
1940 ;*GENERATE 4 SINGLE STEP PULSES TO CLOCK CB AND CLEAR "SLVE PE" AND
1941 ;*CLOCK "DP PE FLAG" FLOP.
1942 ;*CHECK THAT "DP PE FLAG" IS NOT SET.
1943
1944 001577 0 064011 3 2 0 00 11 SDDPE3: MOVB REG0 ;CLEAR FLAG
1945 001600 0 002100 0 1 0 100 GOSUB DEVRD ;SET DEVICE READ
1946 001601 0 177631 7 7 3 11 11
1947 001602 0 064271 3 2 0 13 11 MOVB HSDPIN ;SET "SLVE RDY DLY 2"
1948 001603 0 002230 0 1 0 230 GOSUB CBLOOP ;SETUP FOR GOOD PARITY
1949 001604 0 177631 7 7 3 11 11
1950 001605 0 010000 0 4 0 000 LDMEM 0 ;CLOCK ALL ZEROS, ODD PARITY DATA ONTO
1951 001606 0 002244 0 1 0 244 GOSUB CLKDAT ;THE SLVE DATA LINES
1952 001607 0 177631 7 7 3 11 11
1953 001610 0 002135 0 1 0 135 GOSUB PULSE3 ;CLOCK DATA INTO SRR AND SET "RUN"
1954 001611 0 177631 7 7 3 11 11
1955 001612 0 002134 0 1 0 134 GOSUB PULSE4 ;CLOCK "DP PE FLAG" FLOP
1956 001613 0 177631 7 7 3 11 11
1957 001614 0 022000 1 1 0 00 00 DATI REG0,BR ;READ REG0
1958 001615 0 014000 0 6 0 000 SHR ;MOVE "DP PE FLAG" INTO BIT 0
1959 001616 0 105620 4 2 1620 JMPB0 .+2 ;JUMP IF SET, SHOULDN'T BE
1960 001617 0 101621 4 0 1621 JMP .+2 ;JUMP IF CLEAR
1961 ERROR SDDPE3,"DP PE FLAG" SET WHEN IT SHOULDN'T HAVE,^_
1962 <DIAG SET "CC 2" AND "DIR TO MSTR" AND CLEARED "SLVE PE"
1963 001620 0 116104 4 7 0104 THEN GENERATED 4 SINGLE STEP PULSES>
1964
1965 ERLOOP SDDPE3 ^SALL
1966 001621 0 002007 0 1 0 007
1967 001622 0 116141 4 7 0141
1968 001623 0 115577 4 6 1577
1969 001624 0 116222 4 7 0222 REPEAT TST
1970 001625 0 115421 4 6 1421
1971
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 11
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
1972 TEST 235,TEST CLEARING OF AR BY HS DP INIT
1973 ;***********************************************************************
1974 ;* MCODE5 * TEST 235 * TEST CLEARING OF AR BY HS DP INIT
1975 ;***********************************************************************
1976 SALL
1977 001626 0 002353 0 1 0 353
1978 001627 0 116045 4 7 0045
1979
1980 001630 TST235: SALL
1981
1982 ;*CHECK THAT DOING A HS DP INIT CLEARS THE AR. SINCE DEMUX HAS NOT BEEN
1983 ;*TESTED YET, LOAD AR USING ALL SHIFT VALUES WITH MASK OF ALL ONES.
1984
1985 ;*SETUP CB BOARD LOOPING.
1986 ;*CLEAR THE CLOCK PHASES.
1987 ;*LOAD ROM ADDR FOR SHIFT=0 AND MASK=ALL 1'S.
1988 ;*ENABLE SINGLE STEP AND SET "DX HIGH SPEED".
1989 ;*SET "DIR TO MSTR" AND "SLVE RDY DLY 2" WITH A HS DP INIT.
1990 ;*CLOCK ALL ONES DATA ONTO SLVE DATA LINES.
1991 ;*GENERATE 3 SINGLE STEP PULSES TO CLOCK SRR AND SET "RUN".
1992 ;*GENERATE 4 SINGLE STEP PULSES TO CLOCK CB AND ENABLE THEN DISABLE DEMUX.
1993 ;*DO A HS DP INIT.
1994 ;*CHECK THAT THE AR IS ALL ZEROS.
1995 ;*REPEAT PROCEDURE FOR ALL SHIFT VALUES (0-15).
1996
1997 001630 0 001000 0 0 2 000 LDMAR 0 ;RESET MAR TO ZERO
1998 001631 0 010004 0 4 0 004 LDMEM 4 ;SET ADDITIONAL PNT ROUTINE NUMBER
1999 001632 0 002224 0 1 0 224 GOSUB SETPNT
2000 001633 0 177631 7 7 3 11 11
2001 001634 0 000401 0 0 1 001 LDMARX 1 ;SET MAR EXT BITS
2002 001635 0 002001 0 1 0 001 LDBR RMADR8 ;SET ROM ADDR BIT 8
2003 001636 0 064051 3 2 0 02 11 MOVB REG2
2004 001637 0 002230 0 1 0 230 GOSUB CBLOOP ;SETUP CB BOARD LOOPING
2005 001640 0 177631 7 7 3 11 11
2006 001641 0 002000 0 1 0 000 LDBR 0 ;INIT SHIFT COUNT VALUE
2007 001642 0 072031 3 5 0 01 11 MOVB AC1
2008 001643 0 002002 0 1 0 002 ARLP: LDBR BCLKEN ;CLEAR CLOCK PHASES
2009 001644 0 064031 3 2 0 01 11 MOVB REG1
2010 001645 0 002340 0 1 0 340 LDBR DSHF0 ;START ADDR OF DEMUX SHIFT PROGS
2011 001646 0 062020 3 1 0 01 00 ADB AC1,BR ;INDEX BY SHIFT COUNT VALUE
2012 001647 0 064211 3 2 0 10 11 MOVB DFRMAD
2013 001650 0 002217 0 1 0 217 GOSUB ENSS ;SET "DX HIGH SPEED" AND ENABLE SINGLE STEP
2014 001651 0 177631 7 7 3 11 11
2015 001652 0 002100 0 1 0 100 GOSUB DEVRD ;SETUP DEVICE READ
2016 001653 0 177631 7 7 3 11 11
2017 001654 0 064271 3 2 0 13 11 MOVB HSDPIN ;SET "SLVE RDY DLY 2"
2018 001655 0 001000 0 0 2 000 LDMAR 0 ;CLEAR MAR
2019 001656 0 010377 0 4 0 377 LDMEM -1 ;CLOCK ALL ONES DATA ONTO
2020 001657 0 002244 0 1 0 244 GOSUB CLKDAT ;THE SLVE DATA LINES
2021 001660 0 177631 7 7 3 11 11
2022 001661 0 002135 0 1 0 135 GOSUB PULSE3 ;CLOCK DATA INTO SRR AND SET RUN
2023 001662 0 177631 7 7 3 11 11
2024 001663 0 002134 0 1 0 134 GOSUB PULSE4 ;CLOCK CB THEN ENABLE AND DISABLE DEMUX
2025 001664 0 177631 7 7 3 11 11
2026 001665 0 064271 3 2 0 13 11 MOVB HSDPIN ;CLEAR AR
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 11-1
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
2027 001666 0 003032 0 1 2 032 LDBR AR0S&377,MAR ;SET ZEROS DATA ADDR
2028 001667 0 072051 3 5 0 02 11 MOVB AC2 ;PUT IT IN AC2 ALSO
2029 001670 0 002265 0 1 0 265 GOSUB ARCHK ;GO CHECK AR FOR ALL ZEROS
2030 001671 0 177631 7 7 3 11 11
2031 001672 0 115674 4 6 1674 JMPZ .+2 ;JUMP IF ALL ZEROS
2032 ERROR ARLP,AR NOT CLEARED BY HS DP INIT,^_
2033 001673 0 116104 4 7 0104 DIAG LOADED DATA INTO AR THEN DID A HS DP INIT,PNT
2034
2035 ERLOOP ARLP ^SALL
2036 001674 0 002200 0 1 0 200
2037 001675 0 116141 4 7 0141
2038 001676 0 115643 4 6 1643
2039 001677 0 072023 3 5 0 01 03 INCR AC1 ;INC SHIFT COUNT VALUE
2040 001700 0 062030 3 1 0 01 10 MOV AC1,BR ;MOVE TO BR FOR TESTING
2041 001701 0 107703 4 3 1703 JMPB4 .+2 ;JUMP IF ALL 16 SHIFTS TESTED.
2042 001702 0 101643 4 0 1643 JMP ARLP ;ELSE, CONTINUE
2043
2044 001703 0 116222 4 7 0222 REPEAT TST
2045 001704 0 115630 4 6 1630
2046 001705 0 002000 0 1 0 000 JUMP NXTBNK ;JUMP TO NEXT BANK OF CRAM
2047 001706 0 160231 7 0 0 11 11
2048 002000 .LOC 2000
2049 002000 NXTBNK:
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 12
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
2050 TEST 236,TEST DEMUX MASKING
2051 ;***********************************************************************
2052 ;* MCODE5 * TEST 236 * TEST DEMUX MASKING
2053 ;***********************************************************************
2054 SALL
2055 002000 1 002354 0 1 0 354
2056 002001 1 117743 4 7 1743
2057
2058 002002 TST236: SALL
2059
2060 ;*TEST DEMUX MASKING BY PUTTING ALL ONES DATA INTO THE CB THEN SETTING
2061 ;*MASKS OF ALL ONES, ALL ZEROS, AND FLOATING ONES. CHECK THE AR FOR
2062 ;*CORRECTLY MASKED DATA.
2063
2064 ;*CLEAR CLOCK PHASES.
2065 ;*SETUP CB BOARD LOOPING.
2066 ;*LOAD ROM ADDR FOR PROG WITH ALL ONES MASK AND SHIFT=0.
2067 ;*ENABLE SINGLE STEP AND SET "DX HIGH SPEED".
2068 ;*SET "DIR TO MSTR" AND "SLVE RDY DLY 2" WITH HS DP INIT.
2069 ;*CLOCK ALL ONES DATA ONTO SLAVE DATA LINES.
2070 ;*GENERATE 3 SINGLE STEP PULSES TO CLOCK SRR AND SET "RUN".
2071 ;*GENERATE 3 MORE SINGLE STEP PULSES TO CLOCK CB AND ENABLE DEMUX.
2072 ;*CHECK THAT AR BITS 7-0 ARE ONES.
2073
2074 002002 1 001000 0 0 2 000 LDMAR 0 ;CLEAR MAR
2075 002003 1 010005 0 4 0 005 LDMEM 5 ;SETUP ADDITIONAL PNT ROUTINE NUMBER
2076 002004 1 117624 4 7 1624 JMPSUB SETPNT
2077 002005 1 000401 0 0 1 001 LDMARX 1 ;SET MAR EXT BITS FOR 2ND 256 WORD BLOCK
2078 002006 1 002002 0 1 0 002 LDBR BCLKEN ;ENABLE BASE CLK
2079 002007 1 064031 3 2 0 01 11 MOVB REG1
2080 002010 1 117630 4 7 1630 JMPSUB CBLOOP ;SETUP LOOPING ON CB BOARD
2081 002011 1 002001 0 1 0 001 LDBR RMADR8 ;SET ROM ADR BIT 8
2082 002012 1 064051 3 2 0 02 11 MOVB REG2
2083 002013 1 002340 0 1 0 340 LDBR DSHF0 ;LOAD ROM ADR FOR ALL ONES MASK
2084 002014 1 064211 3 2 0 10 11 MOVB DFRMAD
2085 002015 1 117617 4 7 1617 JMPSUB ENSS ;SET "DX HIGH SPEED" AND ENABLE SINGLE STEP
2086 002016 1 117500 4 7 1500 JMPSUB DEVRD ;SETUP DEVICE READ
2087 002017 1 064271 3 2 0 13 11 MOVB HSDPIN ;SET "SLVE RDY DLY 2"
2088 002020 1 010377 0 4 0 377 LDMEM -1 ;SETUP ALL ONES DATA
2089 002021 1 117644 4 7 1644 JMPSUB CLKDAT ;CLOCK IT ONTO THE SLVE DATA LINES
2090 002022 1 117535 4 7 1535 JMPSUB PULSE3 ;CLOCK DATA INTO THE SRR AND SET "RUN"
2091 002023 1 117535 4 7 1535 JMPSUB PULSE3 ;SET "EN MUX/DEMUX"
2092 002024 1 003035 0 1 2 035 LDBR AR1S&377,MAR ;SET MAR TO CORRECT DATA
2093 002025 1 072051 3 5 0 02 11 MOVB AC2 ;PUT IT IN AC2 ALSO
2094 002026 1 002377 0 1 0 377 LDBR -1 ;SETUP MASK
2095 002027 1 072071 3 5 0 03 11 MOVB AC3
2096 002030 1 117665 4 7 1665 JMPSUB ARCHK ;CHECK AR FOR CORRECT DATA
2097 002031 1 114033 4 6 0033 JMPZ .+2 ;JUMP IF CORRECT
2098 002032 1 117754 4 7 1754 ERROR TST,AR DATA FROM DEMUX IS INCORRECT,,PNT
2099
2100 ERLOOP TST ^SALL
2101 002033 1 002200 0 1 0 200
2102 002034 1 117746 4 7 1746
2103 002035 1 114002 4 6 0002
2104 ;*CLEAR CLOCK PHASES.
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 12-1
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
2105 ;*LOAD ROM ADDR TO CLOCK CB.
2106 ;*SET "DIR TO MSTR" AND "SLVE RDY DLY 2" WITH HS DP INIT.
2107 ;*ENABLE SINGLE STEP AND SET "DX HIGH SPEED".
2108 ;*CLOCK ALL ONES DATA ONTO SLAVE DATA LINES.
2109 ;*SET "RUN" AND CLEAR "DX HIGH SPEED".
2110 ;*LOAD ROM ADDR FOR ZERO MASK, THIS CLEARS "ROM 02" WHICH CLOCKS CB.
2111 ;*GENERATE 3 SINGLE STEP PULSES TO ENABLE DEMUX.
2112 ;*CHECK THAT AR BITS 7-0 ARE ALL ZEROS.
2113
2114 002036 1 001000 0 0 2 000 DMSK: LDMAR 0 ;REINIT MAR
2115 002037 1 002002 0 1 0 002 LDBR BCLKEN ;ENABLE BASE CLK
2116 002040 1 064031 3 2 0 01 11 MOVB REG1
2117 002041 1 002324 0 1 0 324 LDBR CC4 ;SET ROM TO POINT TO LOC WITH
2118 002042 1 064211 3 2 0 10 11 MOVB DFRMAD ;"ROM 02"=1
2119 002043 1 117500 4 7 1500 JMPSUB DEVRD ;SETUP DEVICE READ
2120 002044 1 064271 3 2 0 13 11 MOVB HSDPIN ;SET "SLVE RDY DLY 2"
2121 002045 1 117617 4 7 1617 JMPSUB ENSS ;SET "DX HIGH SPEED" AND ENABLE SINGLE STEP
2122 002046 1 010377 0 4 0 377 LDMEM -1 ;SETUP ALL ONES DATA
2123 002047 1 117644 4 7 1644 JMPSUB CLKDAT ;CLOCK IT ONTO THE SLVE DATA LINES
2124 002050 1 064311 3 2 0 14 11 MOVB SETRUN ;CLEAR "CLR RUN"
2125 002051 1 002000 0 1 0 000 LDBR 0 ;CLEAR "DX HIGH SPEED"
2126 002052 1 064031 3 2 0 01 11 MOVB REG1
2127 002053 1 002327 0 1 0 327 LDBR MSK0 ;SET ROM ADDR TO POINT TO LOC WITH
2128 002054 1 064211 3 2 0 10 11 MOVB DFRMAD ;ALL ZEROS MASK
2129 002055 1 117535 4 7 1535 JMPSUB PULSE3 ;SET "EN MUX/DEMUX"
2130 002056 1 003032 0 1 2 032 LDBR AR0S&377,MAR ;SET MAR TO ALL ZEROS CORRECT DATA
2131 002057 1 072051 3 5 0 02 11 MOVB AC2 ;PUT IT IN AC2 ALSO
2132 002060 1 002000 0 1 0 000 LDBR 0 ;SETUP MASK FOR PRINTOUT
2133 002061 1 072071 3 5 0 03 11 MOVB AC3
2134 002062 1 117665 4 7 1665 JMPSUB ARCHK ;GO CHECK AR DATA
2135 002063 1 114065 4 6 0065 JMPZ .+2 ;JUMP IF ALL ZEROS
2136 002064 1 117754 4 7 1754 ERROR DMSK,AR DATA FROM DEMUX IS INCORRECT,,PNT
2137
2138 ERLOOP DMSK ^SALL
2139 002065 1 002201 0 1 0 201
2140 002066 1 117746 4 7 1746
2141 002067 1 114036 4 6 0036
2142 ;*CLEAR CLOCK PHASES.
2143 ;*LOAD ROM ADDR TO CLOCK CB.
2144 ;*SET "DIR TO MSTR" AND "SLVE RDY DLY 2" WITH HS DP INIT.
2145 ;*ENABLE SINGLE STEP AND SET "DX HIGH SPEED".
2146 ;*CLOCK ALL ONES DATA ONTO SLAVE DATA LINES.
2147 ;*SET "RUN" AND CLEAR "DX HIGH SPEED".
2148 ;*LOAD ROM ADDR FOR TEST MASK, THIS CLEARS "ROM 02" WHICH CLOCKS CB.
2149 ;*GENERATE 3 SINGLE STEP PULSES TO ENABLE DEMUX.
2150 ;*CHECK AR BITS 7-0 FOR CORRECT MASKED DATA.
2151 ;*REPEAT FOR EIGHT 1-BIT MASKS.
2152
2153 002070 1 002040 0 1 0 040 LDBR ARDA0&377 ;START ADDR OF CORRECT DATA
2154 002071 1 072051 3 5 0 02 11 MOVB AC2
2155 002072 1 002000 0 1 0 000 LDBR 0 ;INIT MASK INDEX
2156 002073 1 072031 3 5 0 01 11 MOVB AC1
2157 002074 1 002001 0 1 0 001 LDBR 1 ;INIT MASK
2158 002075 1 072071 3 5 0 03 11 MOVB AC3
2159 002076 1 001000 0 0 2 000 DMSKLP: LDMAR 0 ;REINIT MAR
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 12-2
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
2160 002077 1 002002 0 1 0 002 LDBR BCLKEN ;ENABLE BASE CLK
2161 002100 1 064031 3 2 0 01 11 MOVB REG1
2162 002101 1 002324 0 1 0 324 LDBR CC4 ;SET ROM TO POINT TO LOC WITH
2163 002102 1 064211 3 2 0 10 11 MOVB DFRMAD ;"ROM 02"=1
2164 002103 1 117500 4 7 1500 JMPSUB DEVRD ;SETUP DEVICE READ
2165 002104 1 064271 3 2 0 13 11 MOVB HSDPIN ;SET "SLVE RDY DLY 2"
2166 002105 1 117617 4 7 1617 JMPSUB ENSS ;SET "DX HIGH SPEED" AND ENABLE SINGLE STEP
2167 002106 1 010377 0 4 0 377 LDMEM -1 ;SETUP ALL ONES DATA
2168 002107 1 117644 4 7 1644 JMPSUB CLKDAT ;CLOCK IT ONTO THE SLVE DATA LINES
2169 002110 1 064311 3 2 0 14 11 MOVB SETRUN ;CLEAR "CLR RUN"
2170 002111 1 002000 0 1 0 000 LDBR 0 ;CLEAR "DX HIGH SPEED"
2171 002112 1 064031 3 2 0 01 11 MOVB REG1
2172 002113 1 002330 0 1 0 330 LDBR MSK1 ;START OF ROM MASK LOC
2173 002114 1 062020 3 1 0 01 00 ADB AC1,BR ;INDEX BY MASK INDEX
2174 002115 1 064211 3 2 0 10 11 MOVB DFRMAD
2175 002116 1 117535 4 7 1535 JMPSUB PULSE3 ;SET "EN MUX/DEMUX"
2176 002117 1 061050 3 0 2 02 10 MOV AC2,MAR ;SET MAR TO CORRECT DATA ADDR
2177 002120 1 117665 4 7 1665 JMPSUB ARCHK ;GO CHECK AR DATA
2178 002121 1 114123 4 6 0123 JMPZ .+2 ;JUMP IF ALL ZEROS
2179 002122 1 117754 4 7 1754 ERROR DMSKLP,AR DATA FROM DEMUX IS INCORRECT,,PNT
2180
2181 ERLOOP DMSKLP ^SALL
2182 002123 1 002202 0 1 0 202
2183 002124 1 117746 4 7 1746
2184 002125 1 114076 4 6 0076
2185 002126 1 072065 3 5 0 03 05 SHLR AC3 ;SHIFT MASK
2186 002127 1 002003 0 1 0 003 LDBR 3 ;ADVANCE CORRECT DATA POINTER
2187 002130 1 072040 3 5 0 02 00 ADBR AC2
2188 002131 1 072023 3 5 0 01 03 INCR AC1 ;INC MASK INDEX
2189 002132 1 062025 3 1 0 01 05 SHL AC1,BR ;SHIFT IT AND PUT IN BR
2190 002133 1 106135 4 3 0135 JMPB4 .+2 ;JUMP IF ALL 8 MASKS TESTED
2191 002134 1 100076 4 0 0076 JMP DMSKLP ;ELSE, CONTINUE
2192
2193 002135 1 117756 4 7 1756 REPEAT TST
2194 002136 1 114002 4 6 0002
2195
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 13
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
2196 TEST 237,TEST DEMUX SHIFTING
2197 ;***********************************************************************
2198 ;* MCODE5 * TEST 237 * TEST DEMUX SHIFTING
2199 ;***********************************************************************
2200 SALL
2201 002137 1 002355 0 1 0 355
2202 002140 1 117743 4 7 1743
2203
2204 002141 TST237: SALL
2205
2206 ;*FOR EACH SHIFT COUNT VALUE (0-15), CLOCK FLOATING ONES PATTERNS
2207 ;*FROM THE CB BOARD THRU THE DEMUX AND INTO THE AR.
2208
2209 ;*SETUP CB BOARD LOOPING.
2210 ;*CLEAR CLOCK PHASES AND LOAD ROM ADDR FOR DESIRED SHIFT COUNT.
2211 ;*SET "DX HIGH SPEED" AND ENABLE SINGLE STEPPING.
2212 ;*SET "DIR TO MSTR" AND "SLVE RDY DLY 2".
2213 ;*CLOCK DATA FROM CB BOARD ONTO SLVE DATA LINES.
2214 ;*GENERATE 3 SINGLE STEP PULSES TO CLOCK SRR AND SET "RUN".
2215 ;*GENERATE 3 MORE SINGLE STEP PULSES TO CLOCK CB AND ENABLE DEMUX.
2216 ;*CHECK AR FOR CORRECTED SHIFTED DATA.
2217
2218 002141 1 002000 0 1 0 000 LDBR 0 ;SETUP SHIFT COUNT VALUE
2219 002142 1 073071 3 5 2 03 11 MOVB AC3,MAR ;AND CLEAR MAR
2220 002143 1 010006 0 4 0 006 LDMEM 6 ;SETUP ADDITIONAL PNT ROUTINE #
2221 002144 1 117624 4 7 1624 JMPSUB SETPNT
2222 002145 1 000401 0 0 1 001 LDMARX 1 ;SETUP MAR EXT BITS
2223 002146 1 002001 0 1 0 001 LDBR RMADR8 ;SET ROM ADDR BIT 8
2224 002147 1 064051 3 2 0 02 11 MOVB REG2
2225 002150 1 117630 4 7 1630 JMPSUB CBLOOP ;SETUP LOOPING ON CB BOARD
2226 002151 1 002001 0 1 0 001 DMXLPO: LDBR DPDAT&377 ;SETUP LOAD DATA POINTER
2227 002152 1 072031 3 5 0 01 11 MOVB AC1
2228 002153 1 002012 0 1 0 012 LDBR ARDATS&377 ;GET ADDR OF "CORRECT DATA START ADDR" TABLE
2229 002154 1 061060 3 0 2 03 00 ADB AC3,MAR ;INDEX BY SHIFT COUNT AND SET MAR WITH ADDR
2230 002155 1 052051 2 5 0 02 11 MOVMEM AC2 ;SET AC2 TO BE CORRECT DATA POINTER
2231 002156 1 002002 0 1 0 002 DMXLPI: LDBR BCLKEN ;ENABLE BASE CLK ANDCLEAR "DX HIGH SPEED"
2232 002157 1 064031 3 2 0 01 11 MOVB REG1
2233 002160 1 002340 0 1 0 340 LDBR DSHF0 ;START ADDR OF DEMUX SHIFT PROGS
2234 002161 1 062060 3 1 0 03 00 ADB AC3,BR ;INDEX BY SHIFT COUNT
2235 002162 1 064211 3 2 0 10 11 MOVB DFRMAD ;LOAD THAT ADDR
2236 002163 1 117617 4 7 1617 JMPSUB ENSS ;SET "DX HIGH SPEED" AND ENABLE SINGLE STEP
2237 002164 1 117500 4 7 1500 JMPSUB DEVRD ;SETUP DEVICE READ
2238 002165 1 064271 3 2 0 13 11 MOVB HSDPIN ;SET "SLVE RDY DLY 2"
2239 002166 1 001000 0 0 2 000 LDMAR 0 ;SET MAR TO LOC 0
2240 002167 1 070050 3 4 0 02 10 MOV AC2,MEM ;SAVE CORRECT DATA PTR THERE
2241 002170 1 061030 3 0 2 01 10 MOV AC1,MAR ;SET MAR TO LOAD DATA ADDR
2242 002171 1 117474 4 7 1474 JMPSUB SETDAT ;SETUP DEMUX SHIFT CNT FOR PRINTOUT
2243 002172 1 117644 4 7 1644 JMPSUB CLKDAT ;GO CLOCK DATA INTO SRR FROM CB BOARD
2244 002173 1 117535 4 7 1535 JMPSUB PULSE3 ;CLOCK DATA INTO SRR AND SET "RUN"
2245 002174 1 117535 4 7 1535 JMPSUB PULSE3 ;SET "EN MUX/DEMUX"
2246 002175 1 001000 0 0 2 000 LDMAR 0 ;SET MAR TO LOC 0
2247 002176 1 053051 2 5 2 02 11 MOVMEM AC2,MAR ;RESTORE CORRECT DATA ADDR
2248 002177 1 117665 4 7 1665 JMPSUB ARCHK ;GO CHECK CONTENTS OF AR
2249 002200 1 114202 4 6 0202 JMPZ .+2 ;JUMP IF CORRECT
2250 002201 1 117754 4 7 1754 ERROR DMXLPI,AR DATA FROM DEMUX INCORRECT,,PNT
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 13-1
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
2251
2252 ERLOOP DMXLPI ^SALL
2253 002202 1 002200 0 1 0 200
2254 002203 1 117746 4 7 1746
2255 002204 1 114156 4 6 0156
2256 002205 1 002003 0 1 0 003 LDBR 3 ;SETUP CONSTANT
2257 002206 1 072040 3 5 0 02 00 ADBR AC2 ;ADVANCE CORRECT DATA POINTER
2258 002207 1 072023 3 5 0 01 03 INCR AC1 ;INCREMENT LOAD DATA POINTER
2259 002210 1 061030 3 0 2 01 10 MOV AC1,MAR ;SET MAR TO POINT TO LOAD DATA
2260 002211 1 042011 2 1 0 00 11 MOVMEM BR ;MOVE LOAD DATA TO CHECK FOR ONES
2261 002212 1 114214 4 6 0214 JMPZ .+2 ;JUMP IF DONE, ALL ONES MARKS END
2262 002213 1 100156 4 0 0156 JMP DMXLPI ;ELSE CONTINUE
2263 002214 1 072063 3 5 0 03 03 INCR AC3 ;INCREMENT ROM ADDR
2264 002215 1 062070 3 1 0 03 10 MOV AC3,BR ;MOVE INDEX TO BR
2265 002216 1 106220 4 3 0220 JMPB4 .+2 ;JUMP IF TESTED ALL SHIFTS (16)
2266 002217 1 100151 4 0 0151 JMP DMXLPO ;ELSE CONTINUE
2267
2268 002220 1 117756 4 7 1756 REPEAT TST
2269 002221 1 114141 4 6 0141
2270
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 14
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
2271 TEST 238,TEST AR TO CB GATING
2272 ;***********************************************************************
2273 ;* MCODE5 * TEST 238 * TEST AR TO CB GATING
2274 ;***********************************************************************
2275 SALL
2276 002222 1 002356 0 1 0 356
2277 002223 1 117743 4 7 1743
2278
2279 002224 TST238: SALL
2280
2281 ;*CLOCK DATA FROM THE CB BOARD INTO BITS 8-1 OF THE AR WITH "DIR TO MSTR" SET.
2282 ;*THEN CLEAR "DIR TO MSTR" AND CLOCK THE AR DATA INTO THE CB.
2283
2284 ;*SETUP CB BOARD LOOPING AND CLEAR THE CLOCK PHASES.
2285 ;*LOAD ROM ADDR FOR PROGRAM WHICH LOADS AR.
2286 ;*SET "DX HIGH SPEED" AND ENABLE SINGLE STEP.
2287 ;*SET "DIR TO MSTR" AND "SLVE RDY DLY 2".
2288 ;*CLOCK DATA FROM CB BOARD ONTO SLVE DATA LINES.
2289 ;*GENERATE 7 SINGLE STEP PULSES TO LOAD BITS 7-0 OF AR.
2290 ;*CLOCK NEXT DATA FROM CB BOARD ONTO SLVE DATA LINES.
2291 ;*GENERATE 7 SINGLE STEP PULSES TO LOAD BITS 15-8 OF AR.
2292 ;*CLEAR "DIR TO MSTR" AND SET "RUN".
2293 ;*GENERATE 2 SINGLE STEP PULSES TO CLOCK AR BITS 8-1 INTO CB.
2294 ;*READ SLVE DATA LINES FROM CB BOARD AND CHECK DATA.
2295
2296 002224 1 000401 0 0 1 001 LDMARX 1 ;SET MAR EXT BITS
2297 002225 1 002001 0 1 0 001 LDBR RMADR8 ;SET ROM ADDR BIT 8
2298 002226 1 064051 3 2 0 02 11 MOVB REG2
2299 002227 1 117630 4 7 1630 JMPSUB CBLOOP ;GO SETUP CB BOARD LOOPING
2300 002230 1 002011 0 1 0 011 LDBR ^D9 ;SET LOOP COUNT MINUS 1
2301 002231 1 072031 3 5 0 01 11 MOVB AC1
2302 002232 1 002230 0 1 0 230 LDBR SDPAT&377 ;SETUP CORRECT DATA ADDR IN AC3
2303 002233 1 072071 3 5 0 03 11 MOVB AC3
2304 002234 1 002252 0 1 0 252 LDBR CBPAT&377 ;SETUP LOAD DATA IN AC2
2305 002235 1 072051 3 5 0 02 11 MOVB AC2
2306 002236 1 002002 0 1 0 002 ARCB: LDBR BCLKEN ;CLEAR "DX HIGH SPEED" AND ENABLE BASE CLK
2307 002237 1 064031 3 2 0 01 11 MOVB REG1
2308 002240 1 002310 0 1 0 310 LDBR DMXSHF ;SETUP FOR ROM PROGRAM TO LOAD AR
2309 002241 1 064211 3 2 0 10 11 MOVB DFRMAD
2310 002242 1 117617 4 7 1617 JMPSUB ENSS ;SET "DX HIGH SPEED" AND ENABLE SINGLE STEP
2311 002243 1 117500 4 7 1500 JMPSUB DEVRD ;SETUP DEVICE READ
2312 002244 1 064271 3 2 0 13 11 MOVB HSDPIN ;TO SET "SLVE RDY DLY 2"
2313 002245 1 061050 3 0 2 02 10 MOV AC2,MAR ;SET MAR TO LOAD DATA ADDR
2314 002246 1 117644 4 7 1644 JMPSUB CLKDAT ;GO CLOCK DATA ONTO SLAVE DATA LINES
2315 002247 1 117531 4 7 1531 JMPSUB PULSE7 ;CLOCK DATA INTO AR 7-0
2316 002250 1 001400 0 0 3 000 IMAR ;INC LOAD DATA ADDR
2317 002251 1 117644 4 7 1644 JMPSUB CLKDAT ;CLOCK NEXT 8 DATA BITS INTO
2318 002252 1 117531 4 7 1531 JMPSUB PULSE7 ;AR BITS 15-8
2319 002253 1 117505 4 7 1505 JMPSUB DEVWR ;GO SETUP DEVICE WRITE
2320 002254 1 064311 3 2 0 14 11 MOVB SETRUN ;SET "RUN"
2321 002255 1 117536 4 7 1536 JMPSUB PULSE2 ;CLOCK AR DATA INTO CB
2322 002256 1 117657 4 7 1657 JMPSUB RDDATA ;GO READ DATA OFF SLVE DATA LINES
2323 002257 1 061070 3 0 2 03 10 MOV AC3,MAR ;SET MAR TO CORRECT DATA
2324 002260 1 040017 2 0 0 00 17 OSM AC0 ;COMPARE IT TO DATA WRIITEN
2325 002261 1 114263 4 6 0263 JMPZ .+2 ;JUMP IF CORRECT
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 14-1
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
2326 ERRORM ARCB,CB DATA FROM AR IS INCORRECT,^_
2327 <DIAG LOADED AR (8-1) WITH DATA PATTERN THEN CLEARED
2328 002262 1 117754 4 7 1754 "DIR TO MSTR" AND CLOCKED AR DATA INTO CB>
2329
2330 ERLOOP ARCB ^SALL
2331 002263 1 002100 0 1 0 100
2332 002264 1 117751 4 7 1751
2333 002265 1 114236 4 6 0236
2334 002266 1 072063 3 5 0 03 03 INCR AC3 ;INC CORRECT DATA POINTER
2335 002267 1 072043 3 5 0 02 03 INCR AC2 ;INC LOAD DATA POINTER
2336 002270 1 072043 3 5 0 02 03 INCR AC2
2337 002271 1 073427 3 5 3 01 07 DECR AC1,I ;DEC LOOP COUNT AND INC PATTERN ADDR
2338 002272 1 114274 4 6 0274 JMPZ .+2 ;JUMP IF DONE
2339 002273 1 100236 4 0 0236 JMP ARCB ;ELSE, CONTINUE
2340
2341 002274 1 117756 4 7 1756 REPEAT TST
2342 002275 1 114224 4 6 0224
2343
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 15
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
2344 TEST 239,TEST MUX MASKING
2345 ;***********************************************************************
2346 ;* MCODE5 * TEST 239 * TEST MUX MASKING
2347 ;***********************************************************************
2348 SALL
2349 002276 1 002357 0 1 0 357
2350 002277 1 117743 4 7 1743
2351
2352 002300 TST239: SALL
2353
2354 ;*TEST MUX MASKING BY PUTTING ALL ONES DATA INTO THE SB THEN SETTING
2355 ;*MASKS OF ALL ONES, ALL ZEROS, AND FLOATING ONES. CHECK THE AR FOR
2356 ;*CORRECTLY MASKED DATA.
2357
2358 ;*SETUP CB BOARD LOOPING.
2359 ;*CLEAR CLOCK PHASES.
2360 ;*LOAD ROM ADDR FOR MASK OF ALL ONES.
2361 ;*ENABLE SINGLE STEP AND SET "DX HIGH SPEED".
2362 ;*SET "DIR TO MSTR".
2363 ;*DO A HS DP INIT TO CLOCK ALL 1'S INTO SB FROM "NOT" AR.
2364 ;*SET "RUN" AND GENERATE A SINGLE STEP PULSE TO CLOCK SB AGAIN.
2365 ;*CLEAR "DIR TO MSTR".
2366 ;*GENERATE 3 MORE SINGLE STEP PULSES TO ENABLE THEN DISABLE MUX.
2367 ;*CHECK AR BITS 8-1 FOR ALL ONES.
2368
2369 002300 1 001000 0 0 2 000 LDMAR 0 ;CLEAR MAR
2370 002301 1 010007 0 4 0 007 LDMEM 7 ;SETUP ADDITIONAL PNTROUTINE NUMBER
2371 002302 1 117624 4 7 1624 JMPSUB SETPNT
2372 002303 1 002001 0 1 0 001 LDBR RMADR8 ;SET ROM ADDR BIT 8
2373 002304 1 064051 3 2 0 02 11 MOVB REG2
2374 002305 1 117630 4 7 1630 JMPSUB CBLOOP ;SETUP CB BOARD LOOPING
2375 002306 1 002002 0 1 0 002 LDBR BCLKEN ;CLEAR CLOCK PHASES
2376 002307 1 064031 3 2 0 01 11 MOVB REG1
2377 002310 1 002360 0 1 0 360 LDBR MSK1S ;SET ROM ADDR FOR ALL ONES MASK
2378 002311 1 064211 3 2 0 10 11 MOVB DFRMAD
2379 002312 1 117617 4 7 1617 JMPSUB ENSS ;SET "DX HIGH SPEED" AND ENABLE SINGLE STEP
2380 002313 1 117500 4 7 1500 JMPSUB DEVRD ;SETUP DEVICE READ
2381 002314 1 064271 3 2 0 13 11 MOVB HSDPIN ;CLOCK 1'S INTO SB FROM AR
2382 002315 1 064311 3 2 0 14 11 MOVB SETRUN ;SET "RUN"
2383 002316 1 064251 3 2 0 12 11 MOVB CLKPLS ;CLOCK SB
2384 002317 1 117505 4 7 1505 JMPSUB DEVWR ;SETUP DEVICE WRITE
2385 002320 1 117536 4 7 1536 JMPSUB PULSE2 ;ENABLE MUX
2386 002321 1 010377 0 4 0 377 LDMEM -1 ;SET MEM TO CORRECT DATA
2387 002322 1 117720 4 7 1720 JMPSUB ARCHK7 ;GO CHECK FOR CORRECT AR DATA
2388 002323 1 114325 4 6 0325 JMPZ .+2 ;JUMP IF CORRECT
2389 ERRORM TST,AR DATA FROM MUX IS INCORRECT,^_
2390 <DIAG CLOCKED ONES INTO SB BITS 7-0 THEN CLEARED AR
2391 002324 1 117754 4 7 1754 AND ENABLED MUX WITH SHIFT COUNT=0 AND MASK=377>
2392
2393 ERLOOP TST ^SALL
2394 002325 1 002100 0 1 0 100
2395 002326 1 117751 4 7 1751
2396 002327 1 114300 4 6 0300
2397 ;*CLEAR CLOCK PHASES.
2398 ;*LOAD ROM ADDR FOR MASK OF ALL ZEROS.
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 15-1
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
2399 ;*ENABLE SINGLE STEP AND SET "DX HIGH SPEED".
2400 ;*SET "DIR TO MSTR".
2401 ;*DO A HS DP INIT TO CLOCK ALL 1'S INTO SB FROM "NOT" AR.
2402 ;*CLEAR "DIR TO MSTR".
2403 ;*SET "RUN" AND GENERATE 4 SINGLE STEP PULSES TO ENABLE THEN DISABLE MUX.
2404 ;*CHECK AR BITS 8-1 FOR ALL ZEROS.
2405
2406 002330 1 002002 0 1 0 002 MMSK: LDBR BCLKEN ;CLEAR CLOCK PHASES
2407 002331 1 064031 3 2 0 01 11 MOVB REG1
2408 002332 1 002327 0 1 0 327 LDBR MSK0 ;SET ROM ADDR FOR ZERO MASK
2409 002333 1 064211 3 2 0 10 11 MOVB DFRMAD ;THIS CLOCK SB.
2410 002334 1 117617 4 7 1617 JMPSUB ENSS ;SET "DX HIGH SPEED" AND ENABLE SINGLE STEP
2411 002335 1 117500 4 7 1500 JMPSUB DEVRD ;SETUP DEVICE READ
2412 002336 1 064271 3 2 0 13 11 MOVB HSDPIN ;CLOCK 1'S INTO SB FROM AR
2413 002337 1 117505 4 7 1505 JMPSUB DEVWR ;SETUP DEVICE WRITE
2414 002340 1 064311 3 2 0 14 11 MOVB SETRUN ;SET "RUN"
2415 002341 1 117534 4 7 1534 JMPSUB PULSE4 ;ENABLE MUX
2416 002342 1 010000 0 4 0 000 LDMEM 0 ;SETUP CORRECT DATA
2417 002343 1 117720 4 7 1720 JMPSUB ARCHK7 ;CHECK FOR CORRECT AR DATA
2418 002344 1 114346 4 6 0346 JMPZ .+2 ;JUMP IF CORRECT, ALL ZEROS
2419 ERRORM TST,AR DATA FROM MUX IS INCORRECT,^_
2420 <DIAG CLOCKED ONES INTO SB BITS 7-0 THEN CLEARED AR
2421 002345 1 117754 4 7 1754 AND ENABLED MUX WITH SHIFT COUNT=0 AND MASK=0>
2422
2423 ERLOOP TST ^SALL
2424 002346 1 002101 0 1 0 101
2425 002347 1 117751 4 7 1751
2426 002350 1 114300 4 6 0300
2427 ;*CLEAR CLOCK PHASES.
2428 ;*LOAD ROM ADDR FOR DESIRED MASK.
2429 ;*ENABLE SINGLE STEP AND SET "DX HIGH SPEED".
2430 ;*SET "DIR TO MSTR".
2431 ;*DO A HS DP INIT TO CLOCK ALL 1'S INTO SB FROM "NOT" AR.
2432 ;*CLEAR "DIR TO MSTR".
2433 ;*SET "RUN" AND GENERATE 4 SINGLE STEP PULSES TO ENABLE THEN DISABLE MUX.
2434 ;*CHECK AR BITS 8-1 FOR CORRECTLY MASKED DATA.
2435
2436 002351 1 000402 0 0 1 002 LDMARX 2 ;SET MAR EXT BITS
2437 002352 1 001130 0 0 2 130 LDMAR ARDM0&377 ;SETUP CORRECT DATA START ADDR
2438 002353 1 002000 0 1 0 000 LDBR 0 ;INIT MASK INDEX
2439 002354 1 072031 3 5 0 01 11 MOVB AC1
2440 002355 1 002002 0 1 0 002 MMSKLP: LDBR BCLKEN ;CLEAR CLOCK PHASES
2441 002356 1 064031 3 2 0 01 11 MOVB REG1
2442 002357 1 002330 0 1 0 330 LDBR MSK1 ;START ADDR OF ROM MASK LOCS
2443 002360 1 062020 3 1 0 01 00 ADB AC1,BR ;INDEX BY MASK INDEX
2444 002361 1 064211 3 2 0 10 11 MOVB DFRMAD ;LOAD ADDR, CLOCKS SB
2445 002362 1 117617 4 7 1617 JMPSUB ENSS ;SET "DX HIGH SPEED" AND ENABLE SINGLE STEP
2446 002363 1 117500 4 7 1500 JMPSUB DEVRD ;SETUP DEVICE READ
2447 002364 1 064271 3 2 0 13 11 MOVB HSDPIN ;CLOCK 1'S INTO SB FROM AR
2448 002365 1 117505 4 7 1505 JMPSUB DEVWR ;SETUP DEVICE WRITE
2449 002366 1 064311 3 2 0 14 11 MOVB SETRUN ;SET "RUN"
2450 002367 1 117534 4 7 1534 JMPSUB PULSE4 ;ENABLE MUX
2451 002370 1 002011 0 1 0 011 LDBR 11 ;SELECT MASSBUS INTERFACE
2452 002371 1 066371 3 3 0 17 11 MOVB IOSEL
2453 002372 1 046011 2 3 0 00 11 MOVMEM MPGP10 ;STORE MASK FOR PRINTOUT
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 15-2
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
2454 002373 1 002022 0 1 0 022 LDBR 22 ;SELECT DATA PATH
2455 002374 1 066371 3 3 0 17 11 MOVB IOSEL
2456 002375 1 117720 4 7 1720 JMPSUB ARCHK7 ;CHECK FOR CORRECT AR DATA
2457 002376 1 114400 4 6 0400 JMPZ .+2 ;JUMP IF CORRECT, ALL ZEROS
2458 002377 1 117754 4 7 1754 ERRORM MMSKLP,AR DATA FROM MUX IS INCORRECT,,PNT
2459
2460 ERLOOP MMSKLP ^SALL
2461 002400 1 002302 0 1 0 302
2462 002401 1 117751 4 7 1751
2463 002402 1 114355 4 6 0355
2464 002403 1 073423 3 5 3 01 03 INCR AC1,I ;INC MASK INDEX AND CORRECT DATA ADDR
2465 002404 1 062025 3 1 0 01 05 SHL AC1,BR ;SHIFT IT AND PUT IN BR
2466 002405 1 106407 4 3 0407 JMPB4 .+2 ;JUMP IF TESTED ALL 8 MASKS
2467 002406 1 100355 4 0 0355 JMP MMSKLP ;ELSE, CONTINUE
2468
2469 002407 1 117756 4 7 1756 REPEAT TST
2470 002410 1 114300 4 6 0300
2471
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 16
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
2472 TEST 240,TEST MUX SHIFTING
2473 ;***********************************************************************
2474 ;* MCODE5 * TEST 240 * TEST MUX SHIFTING
2475 ;***********************************************************************
2476 SALL
2477 002411 1 002360 0 1 0 360
2478 002412 1 117743 4 7 1743
2479
2480 002413 TST240: SALL
2481
2482 ;*FOR EACH SHIFT COUNT VALUE (0-15), CLOCK FLOATING ONES PATTERNS INTO THE
2483 ;*SB FROM THE CB BOARD. THEN CLEAR "DIR TO MSTR" AND CLOCK THE PATTERN
2484 ;*THRU THE MUX AND INTO THE AR.
2485
2486 ;*SETUP CB BOARD LOOPING.
2487 ;*CLEAR THE CLOCK PHASES.
2488 ;*LOAD ROM ADDR FOR PROG TO LOAD AR FROM THE CB BOARD.
2489 ;*ENABLE SINGLE STEP AND SET "DX HIGH SPEED".
2490 ;*SET "DIR TO MSTR" AND "SLVE RDY DLY 2" WITH A HS DP INIT.
2491 ;*USING SINGLE STEPPING, CLOCK FLOATING PATTERN INTO AR.
2492 ;*LOAD ROM ADDR FOR MUX SHIFTING.
2493 ;*SET "RUN" AND GENERATE A SINGLE STEP PULSE TO CLOCK SB.
2494 ;*CLEAR "DIR TO MSTR".
2495 ;*GENERATE 3 MORE SINGLE STEP PULSES TO ENABLE THEN DISABLE MUX.
2496 ;*CHECK AR FOR CORRECT SHIFTED DATA.
2497
2498 002413 1 002000 0 1 0 000 LDBR 0 ;INITIALIZE MUX SHIFT COUNT
2499 002414 1 073031 3 5 2 01 11 MOVB AC1,MAR ;AND CLEAR MAR
2500 002415 1 010010 0 4 0 010 LDMEM 8 ;SET ADDITIONAL PNT ROUTINE NUMBER
2501 002416 1 117624 4 7 1624 JMPSUB SETPNT
2502 002417 1 117630 4 7 1630 JMPSUB CBLOOP ;SETUP CB BOARD LOOPING
2503 002420 1 000402 0 0 1 002 LDMARX 2 ;SET MAR EXT BITS FOR 3RD 256 WORD BLOCK
2504 002421 1 002076 0 1 0 076 MUXLPO: LDBR ARDATM&377 ;START OF "CORRECT MUX DATA ADDR" TABLE
2505 002422 1 061020 3 0 2 01 00 ADB AC1,MAR ;INDEX INTO TABLE AND SET MAR
2506 002423 1 052051 2 5 0 02 11 MOVMEM AC2 ;SETUP CORRECT DATA ADDR
2507 002424 1 003007 0 1 2 007 LDBR MUXDAT&377,MAR ;INITIALIZE LOAD DATA ADDR
2508 002425 1 072071 3 5 0 03 11 MOVB AC3
2509 002426 1 002002 0 1 0 002 MUXLPI: LDBR BCLKEN ;CLEAR CLOCK PHASES
2510 002427 1 064031 3 2 0 01 11 MOVB REG1
2511 002430 1 002001 0 1 0 001 LDBR RMADR8 ;SET ROM ADDR BIT 8
2512 002431 1 064051 3 2 0 02 11 MOVB REG2
2513 002432 1 002310 0 1 0 310 LDBR DMXSHF ;SET ROM ADDR TO LOAD AR
2514 002433 1 064211 3 2 0 10 11 MOVB DFRMAD
2515 002434 1 117617 4 7 1617 JMPSUB ENSS ;SET "DX HIGH SPEED" AND ENABLE SINGLE STEP
2516 002435 1 117500 4 7 1500 JMPSUB DEVRD ;SETUP DEVICE READ
2517 002436 1 064271 3 2 0 13 11 MOVB HSDPIN ;SET "SLVE RDY DLY 2"
2518 002437 1 002011 0 1 0 011 LDBR 11 ;SELECT MASSBUS INTERFACE
2519 002440 1 066371 3 3 0 17 11 MOVB IOSEL
2520 002441 1 047451 2 3 3 02 11 MOVMEM MPGP12,I ;STORE LOAD DATA FOR PRINTOUT
2521 002442 1 047471 2 3 3 03 11 MOVMEM MPGP13,I
2522 002443 1 046151 2 3 0 06 11 MOVMEM MPGP16
2523 002444 1 061070 3 0 2 03 10 MOV AC3,MAR ;RESTORE MAR
2524 002445 1 062030 3 1 0 01 10 MOV AC1,BR ;GET SHIFT CNT
2525 002446 1 066171 3 3 0 07 11 MOVB MPGP17 ;STORE IT FOR PRINTOUT
2526 002447 1 002022 0 1 0 022 LDBR 22 ;SELECT DATA PATH
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 16-1
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
2527 002450 1 066371 3 3 0 17 11 MOVB IOSEL
2528 002451 1 117640 4 7 1640 JMPSUB CLKDT ;CLOCK TABLE DATA INTO SRR
2529 002452 1 117531 4 7 1531 JMPSUB PULSE7 ;CLOCK DATA INTO AR BITS 7-0
2530 002453 1 001400 0 0 3 000 IMAR ;INC LOAD DATA ADDR
2531 002454 1 117640 4 7 1640 JMPSUB CLKDT ;CLOCK NEXT DATA INTO SRR
2532 002455 1 117531 4 7 1531 JMPSUB PULSE7 ;CLOCK DATA INTO AR BITS 15-8
2533 002456 1 001400 0 0 3 000 IMAR ;INC LOAD DATA ADDR
2534 002457 1 117640 4 7 1640 JMPSUB CLKDT ;CLOCK NEXT DATA INTO SRR
2535 002460 1 117531 4 7 1531 JMPSUB PULSE7 ;CLOCK DATA INTO AR BITS 17-16
2536 002461 1 002000 0 1 0 000 LDBR 0 ;CLEAR "DX HIGH SPEED"
2537 002462 1 064031 3 2 0 01 11 MOVB REG1
2538 002463 1 002360 0 1 0 360 LDBR MSHF0 ;START ADDR OF MUX SHIFT PROGS
2539 002464 1 062020 3 1 0 01 00 ADB AC1,BR ;INDEX BY SHIFT CNT
2540 002465 1 064211 3 2 0 10 11 MOVB DFRMAD ;LOAD ROM ADDR WITH DESIRED MUX SHIFT LOC
2541 002466 1 064311 3 2 0 14 11 MOVB SETRUN ;SET "RUN"
2542 002467 1 064251 3 2 0 12 11 MOVB CLKPLS ;CLOCK SB
2543 002470 1 117505 4 7 1505 JMPSUB DEVWR ;SETUP DEVICE WRITE
2544 002471 1 117536 4 7 1536 JMPSUB PULSE2 ;ENABLE MUX
2545 002472 1 061050 3 0 2 02 10 MOV AC2,MAR ;SET MAR TO CORRECT DATA ADDR
2546 002473 1 117720 4 7 1720 JMPSUB ARCHK7 ;GO CHECK FOR CORRECT AR DATA
2547 002474 1 114476 4 6 0476 JMPZ .+2 ;JUMP IF CORRECT
2548 002475 1 117754 4 7 1754 ERRORM MUXLPI,AR DATA FROM MUX INCORRECT,,PNT
2549
2550 ERLOOP MUXLPI ^SALL
2551 002476 1 002300 0 1 0 300
2552 002477 1 117751 4 7 1751
2553 002500 1 114426 4 6 0426
2554 002501 1 072043 3 5 0 02 03 INCR AC2 ;INC CORRECT DATA ADDR
2555 002502 1 002003 0 1 0 003 LDBR 3 ;ADVANCE LOAD DATA ADDR
2556 002503 1 072060 3 5 0 03 00 ADBR AC3
2557 002504 1 061070 3 0 2 03 10 MOV AC3,MAR ;SET MAR TO LOAD DATA
2558 002505 1 040011 2 0 0 00 11 MOVMEM ;CHECK FOR ALL ONES END OF DATA MARKER
2559 002506 1 114510 4 6 0510 JMPZ .+2 ;JUMP IF AT END OF TABLE
2560 002507 1 100426 4 0 0426 JMP MUXLPI ;ELSE, CONTINUE
2561 002510 1 072023 3 5 0 01 03 INCR AC1 ;INC MUX SHIFT COUNT
2562 002511 1 062030 3 1 0 01 10 MOV AC1,BR ;MOVE IT TO BR
2563 002512 1 106514 4 3 0514 JMPB4 .+2 ;JUMP IF DONE ALL SHIFTS
2564 002513 1 100421 4 0 0421 JMP MUXLPO ;ELSE, CONTINUE
2565
2566 002514 1 117756 4 7 1756 REPEAT TST
2567 002515 1 114413 4 6 0413
2568
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 17
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
2569 TEST 241,TEST GENERATING "MSTR REQ" ON MB BOARD
2570 ;***********************************************************************
2571 ;* MCODE5 * TEST 241 * TEST GENERATING "MSTR REQ" ON MB BOARD
2572 ;***********************************************************************
2573 SALL
2574 002516 1 002361 0 1 0 361
2575 002517 1 117743 4 7 1743
2576
2577 002520 TST241: SALL
2578
2579 ;*TEST THAT "MSTR REQ" SETS AND CLEARS CORRECTLY ON THE MASSBUS
2580 ;*DATA BOARD.
2581
2582 ;*ENABLE SINGLE STEPPING AND SET "DX HIGH SPEED".
2583 ;*CLEAR "MSTR RDY DLY 2".
2584 ;*SETUP THE RH20 FOR A WRITE XFER.
2585 ;*SET THE "START" BIT.
2586 ;*CHECK THAT "MSTR REQ" IS SET.
2587
2588 002520 1 117600 4 7 1600 JMPSUB ABTXFR ;ABORT THE XFER
2589 002521 1 002005 0 1 0 005 LDBR 5 ;SETUP DATA PATTERN NUMBER
2590 002522 1 072011 3 5 0 00 11 MOVB AC0
2591 002523 1 117605 4 7 1605 JMPSUB SETCNT ;GO SETUP HOST DATA FOR XFER
2592 002524 1 002000 0 1 0 000 LDBR 0 ;ENABLE SINGLE STEP
2593 002525 1 064031 3 2 0 01 11 MOVB REG1
2594 002526 1 002001 0 1 0 001 LDBR DXHISP ;SET "DX HIGH SPEED"
2595 002527 1 064031 3 2 0 01 11 MOVB REG1
2596 002530 1 117500 4 7 1500 JMPSUB DEVRD ;SETUP FOR DEVICE READ
2597 002531 1 064271 3 2 0 13 11 MOVB HSDPIN ;CLEAR "MSTR RDY DLY 2"
2598 002532 1 117541 4 7 1541 JMPSUB STXFRW ;SETUP FOR A DEVICE WRITE XFER
2599 002533 1 117567 4 7 1567 JMPSUB STRMB ;START THE XFER, SET "MSTR REQ"
2600 002534 1 022001 1 1 0 00 01 DATI REG1,BR ;READ REG 1
2601 002535 1 110537 4 4 0537 JMPB7 .+2 ;JUMP IF "MSTR REQ" SET
2602 ERROR TST,"MSTR REQ" DIDN'T SET,^_
2603 002536 1 117754 4 7 1754 DIAG STARTED A DEVICE WRITE XFER
2604
2605 ERLOOP TST ^SALL
2606 002537 1 002000 0 1 0 000
2607 002540 1 117746 4 7 1746
2608 002541 1 114520 4 6 0520
2609 ;*SEND "EBL" TO ABORT PREVIOUS XFER.
2610 ;*SETUP FOR A WRITE XFER AND SET "MSTR REQ".
2611 ;*DO A MICROBUS INIT.
2612 ;*CHECK THAT "MSTR REQ" IS CLEARED.
2613
2614 002542 1 117600 4 7 1600 MRQ1: JMPSUB ABTXFR ;END THE XFER
2615 002543 1 002001 0 1 0 001 LDBR DXHISP ;SET "DX HIGH SPEED"
2616 002544 1 064031 3 2 0 01 11 MOVB REG1
2617 002545 1 117500 4 7 1500 JMPSUB DEVRD ;SET "DIR TO MSTR"
2618 002546 1 064271 3 2 0 13 11 MOVB HSDPIN ;CLEAR "MSTR RDY DLY 2"
2619 002547 1 117541 4 7 1541 JMPSUB STXFRW ;SETUP FOR A DEVICE WRITE XFER
2620 002550 1 117567 4 7 1567 JMPSUB STRMB ;START THE XFER, SET "MSTR REQ"
2621 002551 1 117406 4 7 1406 JMPSUB INITL ;DO A DEVICE RESET
2622 002552 1 022001 1 1 0 00 01 DATI REG1,BR ;READ REG 1
2623 002553 1 110555 4 4 0555 JMPB7 .+2 ;JUMP IF "MSTR REQ" SET, SHOULDN'T BE
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 17-1
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
2624 002554 1 100556 4 0 0556 JMP .+2 ;JUMP IF CLEARED
2625 ERROR MRQ1,"MSTR REQ" DIDN'T CLEAR,^_
2626 002555 1 117754 4 7 1754 DIAG SET "MSTR REQ" THEN DID A DEVICE RESET
2627
2628 ERLOOP MRQ1 ^SALL
2629 002556 1 002001 0 1 0 001
2630 002557 1 117746 4 7 1746
2631 002560 1 114542 4 6 0542
2632 ;*SEND "EBL" TO ABORT PREVIOUS XFER.
2633 ;*SETUP FOR A WRITE XFER AND SET "MSTR REQ".
2634 ;*CLEAR "DX HIGH SPEED".
2635 ;*CHECK THAT "MSTR REQ" IS CLEARED.
2636
2637 002561 1 117600 4 7 1600 MRQ2: JMPSUB ABTXFR ;END THE XFER
2638 002562 1 002001 0 1 0 001 LDBR DXHISP ;SET "DX HIGH SPEED"
2639 002563 1 064031 3 2 0 01 11 MOVB REG1
2640 002564 1 117500 4 7 1500 JMPSUB DEVRD ;SET "DIR TO MSTR"
2641 002565 1 064271 3 2 0 13 11 MOVB HSDPIN ;CLEAR "MSTR RDY DLY 2"
2642 002566 1 117541 4 7 1541 JMPSUB STXFRW ;SETUP FOR A DEVICE WRITE XFER
2643 002567 1 117567 4 7 1567 JMPSUB STRMB ;START THE XFER, SET "MSTR REQ"
2644 002570 1 002000 0 1 0 000 LDBR 0 ;CLEAR "DX HIGH SPEED"
2645 002571 1 064031 3 2 0 01 11 MOVB REG1
2646 002572 1 000000 0 0 0 000 NOP ;DELAY BEFORE DOING DATI
2647 002573 1 022001 1 1 0 00 01 DATI REG1,BR ;READ REG 1
2648 002574 1 110576 4 4 0576 JMPB7 .+2 ;JUMP IF "MSTR REQ" SET, SHOULDN'T BE
2649 002575 1 100577 4 0 0577 JMP .+2 ;JUMP IF CLEARED
2650 ERROR MRQ2,"MSTR REQ" DIDN'T CLEAR,^_
2651 002576 1 117754 4 7 1754 DIAG SET "MSTR REQ" THEN CLEARED "DX HIGH SPEED"
2652
2653 ERLOOP MRQ2 ^SALL
2654 002577 1 002002 0 1 0 002
2655 002600 1 117746 4 7 1746
2656 002601 1 114561 4 6 0561
2657 ;*SEND "EBL" TO ABORT THE PREVIOUS XFER.
2658 ;*DO A MICROBUS INIT TO CLEAR "MSTR REQ".
2659 ;*SET "MSTR RDY DLY 2".
2660 ;*SET "MSTR REQ", THIS SHOULD GENERATE "MSTR ACK" WHICH SHOULD CLEAR
2661 ;*"MSTR REQ".
2662 ;*WAIT FOR "MSTR REQ" TO SET AGAIN.
2663
2664 002602 1 117600 4 7 1600 MRQ3: JMPSUB ABTXFR ;ABORT THE XFER
2665 002603 1 117406 4 7 1406 JMPSUB INITL ;CLEAR "MSTR REQ" ON MB BOARD
2666 002604 1 002002 0 1 0 002 LDBR BCLKEN ;ENABLE BASE CLK
2667 002605 1 064031 3 2 0 01 11 MOVB REG1
2668 002606 1 002001 0 1 0 001 LDBR RMADR8 ;SET ROM ADDR BIT 8
2669 002607 1 064051 3 2 0 02 11 MOVB REG2
2670 002610 1 002322 0 1 0 322 LDBR CC0 ;CLEAR CC BITS
2671 002611 1 064211 3 2 0 10 11 MOVB DFRMAD
2672 002612 1 002003 0 1 0 003 LDBR BCLKEN+DXHISP ;SET "DX HIGH SPEED" AND ENABLE BASE CLK
2673 002613 1 064031 3 2 0 01 11 MOVB REG1
2674 002614 1 117541 4 7 1541 JMPSUB STXFRW ;SETUP FOR A DEVICE WRITE XFER
2675 002615 1 064271 3 2 0 13 11 MOVB HSDPIN ;SET "MSTR RDY DLY 2"
2676 002616 1 117567 4 7 1567 JMPSUB STRMB ;START THE XFER, SET "MSTR REQ"
2677 002617 1 020001 1 0 0 00 01 DATI REG1 ;DELAY UNTIL "MSTR REQ" HAS TIME TO SET AGAIN
2678 002620 1 020001 1 0 0 00 01 DATI REG1 ;DELAY UNTIL "MSTR REQ" HAS TIME TO SET AGAIN
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 17-2
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
2679 002621 1 020001 1 0 0 00 01 DATI REG1 ;DELAY UNTIL "MSTR REQ" HAS TIME TO SET AGAIN
2680 002622 1 020001 1 0 0 00 01 DATI REG1
2681 002623 1 020001 1 0 0 00 01 DATI REG1
2682 002624 1 022001 1 1 0 00 01 DATI REG1,BR ;READ REG 1
2683 002625 1 110627 4 4 0627 JMPB7 .+2 ;JUMP IF "MSTR REQ" SET, SHOULD BE
2684 ERROR MRQ3,"MSTR REQ" DIDN'T SET,^_
2685 002626 1 117754 4 7 1754 DIAG SET "MSTR REQ" ON MB BOARD THEN SET AND CLEARED "MSTR ACK"
2686
2687 ERLOOP MRQ3 ^SALL
2688 002627 1 002003 0 1 0 003
2689 002630 1 117746 4 7 1746
2690 002631 1 114602 4 6 0602
2691 ;*SEND "EBL" TO ABORT PREVIOUS XFER.
2692 ;*DO A MICROBUS INIT TO CLEAR "MSTR REQ".
2693 ;*SETUP FOR A READ XFER AND SET "START".
2694 ;*CHECK THAT "MSTR REQ" IS SET.
2695
2696 002632 1 117600 4 7 1600 MRQ4: JMPSUB ABTXFR ;END THE XFER
2697 002633 1 117406 4 7 1406 JMPSUB INITL ;CLEAR "MSTR REQ" ON MB BOARD
2698 002634 1 002001 0 1 0 001 LDBR DXHISP ;SET "DX HIGH SPEED"
2699 002635 1 064031 3 2 0 01 11 MOVB REG1
2700 002636 1 117550 4 7 1550 JMPSUB STXFRR ;SETUP FOR A DEVICE READ XFER
2701 002637 1 064271 3 2 0 13 11 MOVB HSDPIN ;CLEAR "MSTR RDY DLY 2"
2702 002640 1 117567 4 7 1567 JMPSUB STRMB ;START THE XFER, SET "MSTR REQ"
2703 002641 1 022001 1 1 0 00 01 DATI REG1,BR ;READ REG 1
2704 002642 1 110644 4 4 0644 JMPB7 .+2 ;JUMP IF "MSTR REQ" SET
2705 ERROR MRQ4,"MSTR REQ" DIDN'T SET,^_
2706 002643 1 117754 4 7 1754 DIAG STARTED A DEVICE READ XFER
2707
2708 ERLOOP MRQ4 ^SALL
2709 002644 1 002004 0 1 0 004
2710 002645 1 117746 4 7 1746
2711 002646 1 114632 4 6 0632
2712 002647 1 117600 4 7 1600 JMPSUB ABTXFR ;END THE XFER
2713 002650 1 117406 4 7 1406 JMPSUB INITL ;CLEAR "MSTR REQ" ON MB BOARD
2714
2715 002651 1 117756 4 7 1756 REPEAT TST
2716 002652 1 114520 4 6 0520
2717
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 18
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
2718 TEST 242,TEST MSTR BUS DRIVERS
2719 ;***********************************************************************
2720 ;* MCODE5 * TEST 242 * TEST MSTR BUS DRIVERS
2721 ;***********************************************************************
2722 SALL
2723 002653 1 002362 0 1 0 362
2724 002654 1 117743 4 7 1743
2725
2726 002655 TST242: SALL
2727
2728 ;*CLOCK DATA PATTERNS FROM THE CB BOARD THRU THE FORMATTER AND INTO
2729 ;*THE MASSBUS DATA BOARD BUFFER.
2730
2731 ;*SETUP CB BOARD LOOPING.
2732 ;*CLEAR CLOCK PHASES.
2733 ;*LOAD ROM ADDR FOR PROGRAM TO SEND DATA FROM CB TO MASSBUS.
2734 ;*SET "DX HIGH SPEED" AND ENABLE SINGLE STEP.
2735 ;*SETUP THE RH20 FOR A READ XFER.
2736 ;*DO A HS DP INIT.
2737 ;*SET THE "START" BIT.
2738 ;*USING SINGLE STEPPING, CLOCK DATA FROM CB INTO AR BITS 17-0.
2739 ;*CLOCK THE AR INTO THE SB AND THRU THE MSTR BUS DRIVERS INTO THE
2740 ;*MASSBUS DATA BOARD BUFFER.
2741 ;*CHECK THAT THE DATA IN THE BUFFER IS CORRECT.
2742
2743 002655 1 001000 0 0 2 000 LDMAR 0 ;CLEAR MAR
2744 002656 1 010004 0 4 0 004 LDMEM 4 ;SETUP ADDITIONAL PNT ROUTINE NUMBER
2745 002657 1 117624 4 7 1624 JMPSUB SETPNT
2746 002660 1 002005 0 1 0 005 LDBR 5 ;SETUP DATA PATTERN NUMBER
2747 002661 1 072011 3 5 0 00 11 MOVB AC0
2748 002662 1 117605 4 7 1605 JMPSUB SETCNT ;SETUP DATA FOR HOST
2749 002663 1 117630 4 7 1630 JMPSUB CBLOOP ;SETUP CB BOARD LOOPING
2750 002664 1 000402 0 0 1 002 LDMARX 2 ;SET MAR EXT BITS FOR 3RD 256 WORD BLOCK
2751 002665 1 002001 0 1 0 001 LDBR RMADR8 ;SET ROM ADDR BIT 8
2752 002666 1 064051 3 2 0 02 11 MOVB REG2
2753 002667 1 003001 0 1 2 001 LDBR MUXDT1&377,MAR ;INITIALIZE LOAD DATA ADDR
2754 002670 1 072051 3 5 0 02 11 MOVB AC2
2755 002671 1 002002 0 1 0 002 MBDLP: LDBR BCLKEN ;CLEAR CLOCK PHASES
2756 002672 1 064031 3 2 0 01 11 MOVB REG1
2757 002673 1 002310 0 1 0 310 LDBR DMXSHF ;SET ROM ADDR TO LOAD AR
2758 002674 1 064211 3 2 0 10 11 MOVB DFRMAD
2759 002675 1 117617 4 7 1617 JMPSUB ENSS ;SET "DX HIGH SPEED" AND ENABLE SINGLE STEP
2760 002676 1 117550 4 7 1550 JMPSUB STXFRR ;SETUP FOR DEVICE READ
2761 002677 1 064271 3 2 0 13 11 MOVB HSDPIN ;SET "SLVE RDY DLY 2"
2762 002700 1 117567 4 7 1567 JMPSUB STRMB ;START THE XFER
2763 002701 1 117644 4 7 1644 JMPSUB CLKDAT ;CLOCK TABLE DATA INTO SRR
2764 002702 1 117531 4 7 1531 JMPSUB PULSE7 ;CLOCK DATA INTO AR BITS 7-0
2765 002703 1 001400 0 0 3 000 IMAR ;INC LOAD DATA ADDR
2766 002704 1 117644 4 7 1644 JMPSUB CLKDAT ;CLOCK NEXT DATA INTO SRR
2767 002705 1 117531 4 7 1531 JMPSUB PULSE7 ;CLOCK DATA INTO AR BITS 15-8
2768 002706 1 001400 0 0 3 000 IMAR ;INC LOAD DATA ADDR
2769 002707 1 117644 4 7 1644 JMPSUB CLKDAT ;CLOCK NEXT DATA INTO SRR
2770 002710 1 117531 4 7 1531 JMPSUB PULSE7 ;CLOCK DATA INTO AR BITS 17-16
2771 002711 1 117531 4 7 1531 JMPSUB PULSE7 ;SEND DATA TO MSTR
2772 002712 1 117600 4 7 1600 JMPSUB ABTXFR ;END THE XFER
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 18-1
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
2773 002713 1 002011 0 1 0 011 LDBR 11 ;SELECT MASSBUS INTERFACE
2774 002714 1 066371 3 3 0 17 11 MOVB IOSEL
2775 002715 1 032005 1 5 0 00 05 DATI MPDB0,AC0 ;READ DATA BUFFER BITS 7-0
2776 002716 1 032106 1 5 0 04 06 DATI MPDB1,AC4 ;READ DATA BUFFER BITS 15-8
2777 002717 1 032127 1 5 0 05 07 DATI MPDB2,AC5 ;READ DATA BUFFER BITS 17-16
2778 002720 1 002003 0 1 0 003 LDBR 3 ;SET MASK
2779 002721 1 072133 3 5 0 05 13 LANDBR AC5 ;ISOLATE BITS 17-16
2780 002722 1 002022 0 1 0 022 LDBR 22 ;SELECT DATA PATH
2781 002723 1 066371 3 3 0 17 11 MOVB IOSEL
2782 002724 1 117512 4 7 1512 JMPSUB SETUP ;GO SETUP CORRECT AND ACTUAL FOR PRINTOUT
2783 002725 1 061050 3 0 2 02 10 MOV AC2,MAR ;SET MEM TO CORRECT DATA ADDR
2784 002726 1 041417 2 0 3 00 17 OSM AC0,I ;CHECK BITS 7-0
2785 002727 1 114731 4 6 0731 JMPZ .+2 ;JUMP IF CORRECT
2786 002730 1 100736 4 0 0736 JMP MBERR ;ELSE, REPORT ERROR
2787 002731 1 041517 2 0 3 04 17 OSM AC4,I ;CHECK BITS 15-8
2788 002732 1 114734 4 6 0734 JMPZ .+2 ;JUMP IF CORRECT
2789 002733 1 100736 4 0 0736 JMP MBERR ;ELSE, REPORT ERROR
2790 002734 1 040137 2 0 0 05 17 OSM AC5 ;CHECK BITS 17-16
2791 002735 1 114737 4 6 0737 JMPZ .+2 ;JUMP IF CORRECT
2792 MBERR: ERROR MBDLP,DATA ERROR,^_
2793 002736 1 117754 4 7 1754 DIAG CLOCKED DATA FROM FORMATTER TO MB DATA BUFFER,PNT
2794
2795 ERLOOP MBDLP ^SALL
2796 002737 1 002200 0 1 0 200
2797 002740 1 117746 4 7 1746
2798 002741 1 114671 4 6 0671
2799 002742 1 002003 0 1 0 003 LDBR 3 ;ADVANCE LOAD DATA ADDR
2800 002743 1 073040 3 5 2 02 00 ADBR AC2,MAR ;SET MAR TO LOAD DATA ADDR
2801 002744 1 040011 2 0 0 00 11 MOVMEM ;CHECK FOR ALL ONES END OF DATA MARKER
2802 002745 1 114747 4 6 0747 JMPZ .+2 ;JUMP IF AT END OF TABLE
2803 002746 1 100671 4 0 0671 JMP MBDLP ;ELSE, CONTINUE
2804
2805 002747 1 117756 4 7 1756 REPEAT TST
2806 002750 1 114655 4 6 0655
2807
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 19
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
2808 TEST 243,TEST MRR
2809 ;***********************************************************************
2810 ;* MCODE5 * TEST 243 * TEST MRR
2811 ;***********************************************************************
2812 SALL
2813 002751 1 002363 0 1 0 363
2814 002752 1 117743 4 7 1743
2815
2816 002753 TST243: SALL
2817
2818 ;*SEND DATA FROM THE HOST THRU THE MASSBUS INTERFACE AND INTO THE AR
2819 ;*OF THE FORMATTER.
2820
2821 ;*SETUP FOR CB BOARD LOOPING.
2822 ;*CLEAR CLOCK PHASES.
2823 ;*LOAD ROM ADDR FOR PROGRAM TO RECEIVE DATA FROM MASSBUS INTERFACE.
2824 ;*SET "DX HIGH SPEED" AND ENABLE SINGLE STEPPING.
2825 ;*SETUP RH20 FOR WRITE XFER.
2826 ;*DO A HS DP INIT.
2827 ;*SET THE "START" BIT.
2828 ;*USING SINGLE STEPPING, CLOCK THE DATA INTO THE MRR AND SB.
2829 ;*THEN FORMAT IT AND SEND IT TO THE CB BOARD.
2830 ;*CHECK THE DATA AS IT PASSES THRU THE AR.
2831
2832 002753 1 001000 0 0 2 000 LDMAR 0 ;CLEAR MAR
2833 002754 1 010004 0 4 0 004 LDMEM 4 ;SET ADDITIONAL PNT ROUTINE NUMBER
2834 002755 1 117624 4 7 1624 JMPSUB SETPNT
2835 002756 1 002005 0 1 0 005 LDBR 5 ;SETUP DATA PATTERN NUMBER
2836 002757 1 072011 3 5 0 00 11 MOVB AC0
2837 002760 1 117605 4 7 1605 JMPSUB SETCNT ;SETUP DATA FOR HOST
2838 002761 1 117630 4 7 1630 JMPSUB CBLOOP ;SETUP CB BOARD LOOPING
2839 002762 1 000402 0 0 1 002 LDMARX 2 ;SET MAR EXT BITS FOR 3RD 256 WORD BLOCK
2840 002763 1 002001 0 1 0 001 LDBR RMADR8 ;SET ROM ADDR BIT 8
2841 002764 1 064051 3 2 0 02 11 MOVB REG2
2842 002765 1 002001 0 1 0 001 LDBR MUXDT1&377 ;INITIALIZE CORRECT DATA ADDR
2843 002766 1 072051 3 5 0 02 11 MOVB AC2
2844 002767 1 002002 0 1 0 002 MSTRI: LDBR BCLKEN ;CLEAR CLOCK PHASES
2845 002770 1 064031 3 2 0 01 11 MOVB REG1
2846 002771 1 002314 0 1 0 314 LDBR MUXSHF ;SET ROM TO LOAD SB
2847 002772 1 064211 3 2 0 10 11 MOVB DFRMAD
2848 002773 1 117617 4 7 1617 JMPSUB ENSS ;ENABLE SINGLE STEP AND SET "DX HIGH SPEED"
2849 002774 1 117541 4 7 1541 JMPSUB STXFRW ;SETUP FOR DEVICE WRITE XFER
2850 002775 1 064271 3 2 0 13 11 MOVB HSDPIN ;SET "MSTR RDY DLY 2"
2851 002776 1 117567 4 7 1567 JMPSUB STRMB ;START THE XFER
2852 002777 1 117535 4 7 1535 JMPSUB PULSE3 ;CLOCK DATA TO MRR AND SET RUN
2853 003000 1 117727 4 7 1727 JMPSUB GETAR ;CLOCK DATA INTO AR AND PUT INTO BR
2854 003001 1 072131 3 5 0 05 11 MOVB AC5 ;SAVE IN AC5
2855 003002 1 117635 4 7 1635 JMPSUB SETSLV ;SET "SLVE REQ" ON CB BOARD
2856 003003 1 117727 4 7 1727 JMPSUB GETAR ;CLOCK DATA INTO AR AND PUT INTO BR
2857 003004 1 072111 3 5 0 04 11 MOVB AC4 ;SAVE IN AC4
2858 003005 1 117635 4 7 1635 JMPSUB SETSLV ;SET "SLVE REQ" ON CB BOARD
2859 003006 1 117535 4 7 1535 JMPSUB PULSE3 ;SEND BYTE AND SET RUN AGAIN
2860 003007 1 117727 4 7 1727 JMPSUB GETAR ;CLOCK DATA INTO AR AND PUT INTO BR
2861 003010 1 072011 3 5 0 00 11 MOVB AC0 ;SAVE IN AC0
2862 003011 1 117600 4 7 1600 JMPSUB ABTXFR ;END THE XFER
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 19-1
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
2863 003012 1 117512 4 7 1512 JMPSUB SETUP ;SETUP CORRECT AND ACTUAL FOR PRINTOUT
2864 003013 1 062110 3 1 0 04 10 MOV AC4,BR ;SAVE DATA
2865 003014 1 072031 3 5 0 01 11 MOVB AC1
2866 003015 1 062130 3 1 0 05 10 MOV AC5,BR ;SAVE DATA
2867 003016 1 072071 3 5 0 03 11 MOVB AC3
2868 003017 1 117733 4 7 1733 JMPSUB MBPAR ;GO CHECK MASSBUS PARITY
2869 003020 1 115022 4 6 1022 JMPZ .+2 ;JUMP IF OKAY
2870 ERROR MSTRI,DATA PARITY ERROR ON MASSBUS INTERFACE,^_
2871 003021 1 117754 4 7 1754 DIAG CLOCKED DATA FROM HOST TO DATA PATH INTERFACE,PNT
2872
2873 ERLOOP MSTRI ^SALL
2874 003022 1 002200 0 1 0 200
2875 003023 1 117746 4 7 1746
2876 003024 1 114767 4 6 0767
2877 003025 1 061050 3 0 2 02 10 MOV AC2,MAR ;SET MAR TO CORRECT DATA
2878 003026 1 041417 2 0 3 00 17 OSM AC0,I ;CHECK IF BITS 7-0 ARE OKAY
2879 003027 1 115031 4 6 1031 JMPZ .+2 ;JUMP IF CORRECT
2880 003030 1 101040 4 0 1040 JMP MSTRER ;ELSE, REPORT ERROR
2881 003031 1 041437 2 0 3 01 17 OSM AC1,I ;CHECK IF BITS 15-8 ARE OKAY
2882 003032 1 115034 4 6 1034 JMPZ .+2 ;JUMP IF CORRECT
2883 003033 1 101040 4 0 1040 JMP MSTRER ;ELSE, REPORT ERROR
2884 003034 1 002003 0 1 0 003 LDBR 3 ;SET MASK OF BITS 17-16
2885 003035 1 072073 3 5 0 03 13 LANDBR AC3 ;ISOLATE THEM IN AC5
2886 003036 1 040077 2 0 0 03 17 OSM AC3 ;CHECK IF THEY'RE OKAY
2887 003037 1 115041 4 6 1041 JMPZ .+2 ;JUMP IF CORRECT
2888 MSTRER: ERROR MSTRI,DATA ERROR,^_
2889 003040 1 117754 4 7 1754 DIAG CLOCKED DATA FROM HOST THRU MRR INTO AR,PNT
2890
2891 ERLOOP MSTRI ^SALL
2892 003041 1 002201 0 1 0 201
2893 003042 1 117746 4 7 1746
2894 003043 1 114767 4 6 0767
2895 003044 1 002011 0 1 0 011 LDBR 11 ;SELECT MASSBUS INTERFACE
2896 003045 1 066371 3 3 0 17 11 MOVB IOSEL
2897 003046 1 132000 5 5 0 00 00 DATI MPGP10,AC0 ;READ DATA PATTERN NUMBER
2898 003047 1 062003 3 1 0 00 03 INC AC0,BR ;INCREMENT IT
2899 003050 1 066011 3 3 0 00 11 MOVB MPGP10 ;AND STORE IT
2900 003051 1 002022 0 1 0 022 LDBR 22 ;SELECT DATA PATH
2901 003052 1 066371 3 3 0 17 11 MOVB IOSEL
2902 003053 1 002003 0 1 0 003 LDBR 3 ;ADVANCE CORRECT DATA POINTER
2903 003054 1 073040 3 5 2 02 00 ADBR AC2,MAR
2904 003055 1 040011 2 0 0 00 11 MOVMEM ;TEST NEXT ENTRY
2905 003056 1 115060 4 6 1060 JMPZ .+2 ;ALL ONES MEANS END OF TABLE
2906 003057 1 100767 4 0 0767 JMP MSTRI ;ELSE, CONTINUE
2907
2908 003060 1 117756 4 7 1756 REPEAT TST
2909 003061 1 114753 4 6 0753
2910
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 20
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
2911 TEST 244,TEST CLEARING OF MRR AND SB
2912 ;***********************************************************************
2913 ;* MCODE5 * TEST 244 * TEST CLEARING OF MRR AND SB
2914 ;***********************************************************************
2915 SALL
2916 003062 1 002364 0 1 0 364
2917 003063 1 117743 4 7 1743
2918
2919 003064 TST244: SALL
2920
2921 ;*TEST THAT A HS DP INIT CLEARS THE MRR AND CLOCKS IT INTO THE SB.
2922
2923 ;*CLEAR THE CLOCK PHASES AND ENABLE SINGLE STEP.
2924 ;*SET "DIR TO MSTR".
2925 ;*DO A HS DP INIT, SHOULD CLOCK "NOT AR" INTO SB.
2926 ;*CLEAR "DIR TO MSTR".
2927 ;*DO A HS DP INIT, SHOULD CLOCK MRR INTO SB.
2928 ;*LOAD ROM ADDR FOR PROGRAM TO CLOCK SB INTO AR.
2929 ;*SET "DX HIGH SPEED" AND "RUN".
2930 ;*SINGLE STEP SB BITS 7-0 INTO AR.
2931 ;*SET "RUN" AGAIN AND SINGLE STEP SB BITS 15-8 INTO AR.
2932 ;*SET "RUN" AGAIN AND SINGLE STEP SB BITS 17-16 INTO AR.
2933 ;*CHECK THAT ALL SB BITS ARE ZEROS.
2934
2935 003064 1 001000 0 0 2 000 LDMAR 0 ;CLEAR MAR
2936 003065 1 010004 0 4 0 004 LDMEM 4 ;SETUP ADDITIONAL PNT ROUTINE NUMBER
2937 003066 1 117624 4 7 1624 JMPSUB SETPNT
2938 003067 1 002001 0 1 0 001 LDBR RMADR8 ;SET ROM ADDR BIT 8
2939 003070 1 064051 3 2 0 02 11 MOVB REG2
2940 003071 1 002002 0 1 0 002 LDBR BCLKEN ;CLEAR CLOCK PHASES
2941 003072 1 064031 3 2 0 01 11 MOVB REG1
2942 003073 1 002000 0 1 0 000 LDBR 0 ;ENABLE SINGLE STEP
2943 003074 1 064031 3 2 0 01 11 MOVB REG1
2944 003075 1 117500 4 7 1500 JMPSUB DEVRD ;SETUP DEVICE READ
2945 003076 1 064271 3 2 0 13 11 MOVB HSDPIN ;CLEAR AR, CLOCK "NOT AR" INTO SB
2946 003077 1 117505 4 7 1505 JMPSUB DEVWR ;SETUP DEVICE WRITE
2947 003100 1 064271 3 2 0 13 11 MOVB HSDPIN ;CLEAR MRR, CLOCK MRR INTO SB
2948 003101 1 002314 0 1 0 314 LDBR MUXSHF ;SET ROM TO CLOCK SB DATA INTO AR
2949 003102 1 064211 3 2 0 10 11 MOVB DFRMAD
2950 003103 1 002001 0 1 0 001 LDBR DXHISP ;SET "DX HIGH SPEED"
2951 003104 1 064031 3 2 0 01 11 MOVB REG1
2952 003105 1 064311 3 2 0 14 11 MOVB SETRUN ;SET "RUN"
2953 003106 1 117727 4 7 1727 JMPSUB GETAR ;CLOCK DATA INTO AR AND PUT INTO BR
2954 003107 1 072131 3 5 0 05 11 MOVB AC5 ;MOVE THEM TO AC5
2955 003110 1 002003 0 1 0 003 LDBR 3 ;SET MASK OF BITS 17-16
2956 003111 1 072133 3 5 0 05 13 LANDBR AC5 ;ISOLATE THEM IN AC5
2957 003112 1 064311 3 2 0 14 11 MOVB SETRUN ;SET "RUN"
2958 003113 1 117727 4 7 1727 JMPSUB GETAR ;CLOCK DATA INTO AR AND PUT INTO BR
2959 003114 1 072111 3 5 0 04 11 MOVB AC4 ;SAVE THEM IN AC4
2960 003115 1 064311 3 2 0 14 11 MOVB SETRUN ;SET "RUN"
2961 003116 1 117727 4 7 1727 JMPSUB GETAR ;CLOCK DATA INTO AR AND PUT INTO BR
2962 003117 1 072011 3 5 0 00 11 MOVB AC0 ;SAVE THEM IN AC0
2963 003120 1 002011 0 1 0 011 LDBR 11 ;SELECT MASSBUS INTERFACE
2964 003121 1 066371 3 3 0 17 11 MOVB IOSEL
2965 003122 1 002000 0 1 0 000 LDBR 0 ;SETUP CORRECT DATA
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 20-1
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
2966 003123 1 066051 3 3 0 02 11 MOVB MPGP12
2967 003124 1 066071 3 3 0 03 11 MOVB MPGP13
2968 003125 1 066151 3 3 0 06 11 MOVB MPGP16
2969 003126 1 002022 0 1 0 022 LDBR 22 ;SELECT DATA PATH
2970 003127 1 066371 3 3 0 17 11 MOVB IOSEL
2971 003130 1 117515 4 7 1515 JMPSUB SETACT ;SETUP ACTUAL DATA
2972 003131 1 010000 0 4 0 000 LDMEM 0 ;SETUP CORRECT DATA
2973 003132 1 040017 2 0 0 00 17 OSM AC0 ;CHECK BITS 7-0
2974 003133 1 115135 4 6 1135 JMPZ .+2 ;JUMP IF THEY'RE ALL ZEROS
2975 003134 1 101142 4 0 1142 JMP CLRER ;ELSE, REPORT ERROR
2976 003135 1 040117 2 0 0 04 17 OSM AC4 ;CHECK BITS 15-8
2977 003136 1 115140 4 6 1140 JMPZ .+2 ;JUMP IF THEY'RE ALL ZEROS
2978 003137 1 101142 4 0 1142 JMP CLRER ;ELSE, REPORT ERROR
2979 003140 1 040137 2 0 0 05 17 OSM AC5 ;CHECK BITS 17-16
2980 003141 1 115143 4 6 1143 JMPZ .+2 ;JUMP IF THEY'RE ALL ZEROS
2981 CLRER: ERROR TST,MRR DID NOT CLEAR AFTER HS DP INIT,^_
2982 <DIAG CLEARED "DIR TO MSTR" AND DID A HS DP INIT THEN
2983 003142 1 117754 4 7 1754 READ THE SB CONTENTS FROM THE AR>,PNT
2984
2985 ERLOOP TST ^SALL
2986 003143 1 002200 0 1 0 200
2987 003144 1 117746 4 7 1746
2988 003145 1 115064 4 6 1064
2989 003146 1 117756 4 7 1756 REPEAT TST
2990 003147 1 115064 4 6 1064
2991
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 21
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
2992 TEST 245,TEST "MSTR PE"
2993 ;***********************************************************************
2994 ;* MCODE5 * TEST 245 * TEST "MSTR PE"
2995 ;***********************************************************************
2996 SALL
2997 003150 1 002365 0 1 0 365
2998 003151 1 117743 4 7 1743
2999
3000 003152 TST245: SALL
3001
3002 ;*TEST THAT "MSTR PE" SETS WHEN EVEN PARITY DATA IS CLOCKED INTO THE SB
3003 ;*AND DOES NOT SET FOR ODD PARITY DATA.
3004
3005 ;*ENABLE SINGLE STEP AND CLEAR "DX HIGH SPEED".
3006 ;*CLEAR "DIR TO MSTR".
3007 ;*DO A HS DP INIT TO CLOCK ALL ZEROS INTO THE SB.
3008 ;*CHECK THAT "MSTR PE" IS SET.
3009
3010 003152 1 002000 0 1 0 000 LDBR 0 ;ENABLE SINGLE STEP
3011 003153 1 064031 3 2 0 01 11 MOVB REG1
3012 003154 1 117505 4 7 1505 JMPSUB DEVWR ;SETUP DEVICE WRITE
3013 003155 1 064271 3 2 0 13 11 MOVB HSDPIN ;CLOCKED ALL ZEROS INTO SRR, SET "MSTR PE"
3014 003156 1 022016 1 1 0 00 16 DATI REG16,BR ;READ REG 16
3015 003157 1 014000 0 6 0 000 SHR ;RIGHT ADJUST "MSTR PE"
3016 003160 1 105162 4 2 1162 JMPB0 .+2 ;JUMP IF SET, SHOULD BE
3017 ERROR TST,"MSTR PE" DIDN'T SET,^_
3018 003161 1 117754 4 7 1754 DIAG DID A HS DP INIT WITH "DIR TO MSTR" CLEARED
3019
3020 ERLOOP TST ^SALL
3021 003162 1 002000 0 1 0 000
3022 003163 1 117746 4 7 1746
3023 003164 1 115152 4 6 1152
3024 ;*CLEAR CLOCK PHASES.
3025 ;*CLEAR "DIR TO MSTR" AND SET "MSTR RDY DLY 2".
3026 ;*LOAD ROM ADDR FOR PROG TO CLOCK SB.
3027 ;*ENABLE SINGLE STEP AND SET "DX HIGH SPEED".
3028 ;*SETUP RH20 FOR WRITE XFER AND SET "START".
3029 ;*GENERATE 7 SINGLE STEP PULSES TO CLOCK MASSBUS DATA PATTERN INTO SB.
3030 ;*ABORT THE XFER.
3031 ;*CHECK THAT "MSTR PE" IS NOT SET.
3032 ;*REPEAT FOR ONES, ZEROS, FLOATING ONES AND ZEROS PATTERNS.
3033
3034 003165 1 001000 0 0 2 000 LDMAR 0 ;CLEAR MAR
3035 003166 1 010011 0 4 0 011 LDMEM 9 ;SET ADDITIONAL PNT ROUTINE NUMBER
3036 003167 1 117624 4 7 1624 JMPSUB SETPNT
3037 003170 1 002005 0 1 0 005 LDBR 5 ;SETUP DATA PATTERN NUMBER
3038 003171 1 072011 3 5 0 00 11 MOVB AC0
3039 003172 1 117605 4 7 1605 JMPSUB SETCNT ;SETUP DATA FOR HOST
3040 003173 1 002001 0 1 0 001 LDBR RMADR8 ;SET ROM ADDR BIT 8
3041 003174 1 064051 3 2 0 02 11 MOVB REG2
3042 003175 1 000402 0 0 1 002 LDMARX 2 ;SET MAR EXT BITS FOR 3RD 256 WORD BLOCK
3043 003176 1 002001 0 1 0 001 LDBR MUXDT1&377 ;INITIALIZE RECEIVED DATA ADDR
3044 003177 1 072051 3 5 0 02 11 MOVB AC2
3045 003200 1 002002 0 1 0 002 MPARLP: LDBR BCLKEN ;CLEAR CLOCK PHASES
3046 003201 1 064031 3 2 0 01 11 MOVB REG1
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 21-1
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
3047 003202 1 117505 4 7 1505 JMPSUB DEVWR ;SETUP DEVICE WRITE
3048 003203 1 064271 3 2 0 13 11 MOVB HSDPIN ;SET "MSTR RDY DLY 2"
3049 003204 1 002314 0 1 0 314 LDBR MUXSHF ;SET ROM TO LOAD SB
3050 003205 1 064211 3 2 0 10 11 MOVB DFRMAD
3051 003206 1 117617 4 7 1617 JMPSUB ENSS ;ENABLE SINGLE STEP AND SET "DX HIGH SPEED"
3052 003207 1 117541 4 7 1541 JMPSUB STXFRW ;SETUP FOR DEVICE WRITE XFER
3053 003210 1 117567 4 7 1567 JMPSUB STRMB ;START THE XFER
3054 003211 1 117531 4 7 1531 JMPSUB PULSE7 ;CLOCK DATA TO MRR AND SB
3055 003212 1 117600 4 7 1600 JMPSUB ABTXFR ;END THE XFER
3056 003213 1 002011 0 1 0 011 LDBR 11 ;SELECT MASSBUS INTERFACE
3057 003214 1 066371 3 3 0 17 11 MOVB IOSEL
3058 003215 1 117524 4 7 1524 JMPSUB SETCOR ;SETUP CORRECT DATA FOR PRINTOUT
3059 003216 1 002022 0 1 0 022 LDBR 22 ;SELECT DATA PATH
3060 003217 1 066371 3 3 0 17 11 MOVB IOSEL
3061 003220 1 117733 4 7 1733 JMPSUB MBPAR ;GO CHECK MASSBUS PARITY
3062 003221 1 115223 4 6 1223 JMPZ .+2 ;JUMP IF OKAY
3063 ERROR MPARLP,DATA PARITY ERROR ON MASSBUS INTERFACE,^_
3064 003222 1 117754 4 7 1754 DIAG CLOCKED DATA FROM HOST TO DATA PATH INTERFACE,PNT
3065
3066 ERLOOP MPARLP ^SALL
3067 003223 1 002201 0 1 0 201
3068 003224 1 117746 4 7 1746
3069 003225 1 115200 4 6 1200
3070 003226 1 022016 1 1 0 00 16 DATI REG16,BR ;READ REG 16
3071 003227 1 014000 0 6 0 000 SHR ;RIGHT ADJUST "MSTR PE"
3072 003230 1 105232 4 2 1232 JMPB0 .+2 ;JUMP IF SET, SHOULDN'T BE
3073 003231 1 101233 4 0 1233 JMP .+2 ;JUMP IF CLEAR
3074 ERROR MPARLP,<"MSTR PE" SET WHEN GOOD DATA WAS CLOCKED^_
3075 003232 1 117754 4 7 1754 INTO THE SB>,,PNT
3076
3077 ERLOOP MPARLP ^SALL
3078 003233 1 002202 0 1 0 202
3079 003234 1 117746 4 7 1746
3080 003235 1 115200 4 6 1200
3081 003236 1 002011 0 1 0 011 LDBR 11 ;SELECT MASSBUS INTERFACE
3082 003237 1 066371 3 3 0 17 11 MOVB IOSEL
3083 003240 1 132000 5 5 0 00 00 DATI MPGP10,AC0 ;READ DATA PATTERN NUMBER
3084 003241 1 062003 3 1 0 00 03 INC AC0,BR ;INCREMENT IT
3085 003242 1 066011 3 3 0 00 11 MOVB MPGP10 ;AND STORE IT
3086 003243 1 002022 0 1 0 022 LDBR 22 ;SELECT DATA PATH
3087 003244 1 066371 3 3 0 17 11 MOVB IOSEL
3088 003245 1 002003 0 1 0 003 LDBR 3 ;ADVANCE CORRECT DATA POINTER
3089 003246 1 073040 3 5 2 02 00 ADBR AC2,MAR
3090 003247 1 040011 2 0 0 00 11 MOVMEM ;TEST NEXT ENTRY
3091 003250 1 115252 4 6 1252 JMPZ .+2 ;ALL ONES MEANS END OF TABLE
3092 003251 1 101200 4 0 1200 JMP MPARLP ;ELSE, CONTINUE
3093
3094 003252 1 117756 4 7 1756 REPEAT TST
3095 003253 1 115152 4 6 1152
3096
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 22
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
3097 TEST 246,TEST "DP PE FLAG" USING "MSTR PE"
3098 ;***********************************************************************
3099 ;* MCODE5 * TEST 246 * TEST "DP PE FLAG" USING "MSTR PE"
3100 ;***********************************************************************
3101 SALL
3102 003254 1 002366 0 1 0 366
3103 003255 1 117743 4 7 1743
3104
3105 003256 TST246: SALL
3106
3107 ;*CLEAR CLOCK PHASES.
3108 ;*SET "ROM 01".
3109 ;*ENABLE SINGLE STEP AND SET "DX HIGH SPEED".
3110 ;*CLEAR "DIR TO MSTR".
3111 ;*DO A HS DP INIT TO SET "MSTR PE".
3112 ;*SET "RUN" AND GENERATE 4 SINGLE STEP PULSES.
3113 ;*CHECK THAT "DP PE FLAG" IS SET.
3114
3115 003256 1 002002 0 1 0 002 LDBR BCLKEN ;CLEAR CLOCK PHASES
3116 003257 1 064031 3 2 0 01 11 MOVB REG1
3117 003260 1 002001 0 1 0 001 LDBR RMADR8 ;SET ROM ADDR BIT 8
3118 003261 1 064051 3 2 0 02 11 MOVB REG2
3119 003262 1 002323 0 1 0 323 LDBR CC2 ;SET ROM ADDR TO POINT TO LOC WITH
3120 003263 1 064211 3 2 0 10 11 MOVB DFRMAD ;"ROM 01"=1
3121 003264 1 117617 4 7 1617 JMPSUB ENSS ;SET "DX HIGH SPEED" AND ENABLE SINGLE STEP
3122 003265 1 117505 4 7 1505 JMPSUB DEVWR ;SETUP DEVICE WRITE
3123 003266 1 064271 3 2 0 13 11 MOVB HSDPIN ;CLOCK ZEROS INTO SB, SET "MSTR PE"
3124 003267 1 064311 3 2 0 14 11 MOVB SETRUN ;CLEAR "CLR RUN"
3125 003270 1 117534 4 7 1534 JMPSUB PULSE4 ;GEN 4 SINGLE STEP PULSES
3126 003271 1 022000 1 1 0 00 00 DATI REG0,BR ;READ REG0
3127 003272 1 014000 0 6 0 000 SHR ;MOVE "DP PE FLAG" INTO BIT 0
3128 003273 1 105275 4 2 1275 JMPB0 .+2 ;JUMP IF SET, SHOULD BE
3129 ERROR TST,"DP PE FLAG" DID NOT SET,^_
3130 <DIAG SET "CC 1" AND "MSTR PE" AND CLEARED "DIR TO MSTR" THEN
3131 003274 1 117754 4 7 1754 GENERATED 4 SINGLE STEP PULSES>
3132
3133 ERLOOP TST ^SALL
3134 003275 1 002000 0 1 0 000
3135 003276 1 117746 4 7 1746
3136 003277 1 115256 4 6 1256
3137 ;*WRITE REG 0 TO CLEAR "DP PE FLAG".
3138 ;*CLEAR "ROM 01".
3139 ;*SET "RUN" AND GENERATE 4 SINGLE STEP PULSES.
3140 ;*CHECK THAT "DP PE FLAG" IS NOT SET.
3141
3142 003300 1 064011 3 2 0 00 11 MDPPE1: MOVB REG0 ;CLEAR FLAG
3143 003301 1 002000 0 1 0 000 LDBR 0 ;CLEAR "DX HIGH SPEED"
3144 003302 1 064031 3 2 0 01 11 MOVB REG1
3145 003303 1 002320 0 1 0 320 LDBR ZEROS ;CLEAR "ROM 01"
3146 003304 1 064211 3 2 0 10 11 MOVB DFRMAD
3147 003305 1 002001 0 1 0 001 LDBR DXHISP ;SET "DX HIGH SPEED"
3148 003306 1 064031 3 2 0 01 11 MOVB REG1
3149 003307 1 064311 3 2 0 14 11 MOVB SETRUN ;SET "RUN"
3150 003310 1 117534 4 7 1534 JMPSUB PULSE4 ;CLOCK "DP PE FLAG" FLOP
3151 003311 1 022000 1 1 0 00 00 DATI REG0,BR ;READ REG0
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 22-1
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
3152 003312 1 014000 0 6 0 000 SHR ;MOVE "DP PE FLAG" INTO BIT 0
3153 003313 1 105315 4 2 1315 JMPB0 .+2 ;JUMP IF SET, SHOULDN'T BE
3154 003314 1 101316 4 0 1316 JMP .+2 ;JUMP IF CLEAR
3155 ERROR MDPPE1,"DP PE FLAG" SET WHEN IT SHOULDN'T HAVE,^_
3156 <DIAG SET "MSTR PE" AND CLEARED "CC 1" AND "DIR TO MSTR"
3157 003315 1 117754 4 7 1754 THEN GENERATED 4 SINGLE STEP PULSES>
3158
3159 ERLOOP MDPPE1 ^SALL
3160 003316 1 002001 0 1 0 001
3161 003317 1 117746 4 7 1746
3162 003320 1 115300 4 6 1300
3163 ;*CLEAR "DIR TO MSTR" AND SET "ROM 01".
3164 ;*SET "RUN" AND GENERATE 2 SINGLE STEP PULSES.
3165 ;*SET "DIR TO MSTR" AND GENERATE 2 MORE SINGLE STEP PULSES.
3166 ;*CHECK THAT "DP PE FLAG" IS NOT SET.
3167
3168 003321 1 064011 3 2 0 00 11 MDPPE2: MOVB REG0 ;CLEAR FLAG
3169 003322 1 117505 4 7 1505 JMPSUB DEVWR ;SETUP DEVICE WRITE
3170 003323 1 002000 0 1 0 000 LDBR 0 ;CLEAR "DX HIGH SPEED"
3171 003324 1 064031 3 2 0 01 11 MOVB REG1
3172 003325 1 002323 0 1 0 323 LDBR CC2 ;SET "CC 1"
3173 003326 1 064211 3 2 0 10 11 MOVB DFRMAD
3174 003327 1 002001 0 1 0 001 LDBR DXHISP ;SET "DX HIGH SPEED"
3175 003330 1 064031 3 2 0 01 11 MOVB REG1
3176 003331 1 064311 3 2 0 14 11 MOVB SETRUN ;SET "RUN"
3177 003332 1 117536 4 7 1536 JMPSUB PULSE2 ;CLOCK ZEROS TO SB
3178 003333 1 117500 4 7 1500 JMPSUB DEVRD ;SETUP DEVICE READ
3179 003334 1 117536 4 7 1536 JMPSUB PULSE2 ;CLOCK "DP PE FLAG" FLOP
3180 003335 1 022000 1 1 0 00 00 DATI REG0,BR ;READ REG0
3181 003336 1 014000 0 6 0 000 SHR ;MOVE "DP PE FLAG" INTO BIT 0
3182 003337 1 105341 4 2 1341 JMPB0 .+2 ;JUMP IF SET, SHOULDN'T BE
3183 003340 1 101342 4 0 1342 JMP .+2 ;JUMP IF CLEAR
3184 ERROR MDPPE2,"DP PE FLAG" SET WHEN IT SHOULDN'T HAVE,^_
3185 <DIAG SET "MSTR PE" AND "CC 1" AND "DIR TO MSTR" THEN
3186 003341 1 117754 4 7 1754 GENERATED 4 SINGLE STEP PULSES>
3187
3188 ERLOOP MDPPE2 ^SALL
3189 003342 1 002002 0 1 0 002
3190 003343 1 117746 4 7 1746
3191 003344 1 115321 4 6 1321
3192 003345 1 002005 0 1 0 005 LDBR 5 ;SETUP DATA PATTERN NUMBER
3193 003346 1 072011 3 5 0 00 11 MOVB AC0
3194 003347 1 117605 4 7 1605 JMPSUB SETCNT ;SETUP DATA FOR HOST
3195 ;*CLEAR "DIR TO MSTR" AND SET "MSTR RDY DLY 2" WITH HS DP INIT.
3196 ;*LOAD ROM ADDR FOR PROG TO LOAD SB.
3197 ;*ENABLE SINGLE STEP AND SET "DX HIGH SPEED".
3198 ;*SETUP RH20 FOR A WRITE XFER AND SET "START".
3199 ;*GENERATE 7 SINGLE STEP PULSES TO CLOCK GOOD DATA INTO SB.
3200 ;*ABORT THE XFER.
3201 ;*CHECK THAT "DP PE FLAG" IS NOT SET.
3202
3203 003350 1 064011 3 2 0 00 11 MDPPE3: MOVB REG0 ;CLEAR FLAG
3204 003351 1 002000 0 1 0 000 LDBR 0 ;CLEAR "DX HIGH SPEED"
3205 003352 1 064031 3 2 0 01 11 MOVB REG1
3206 003353 1 117505 4 7 1505 JMPSUB DEVWR ;SETUP DEVICE WRITE
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 22-2
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
3207 003354 1 064271 3 2 0 13 11 MOVB HSDPIN ;SET "MSTR RDY DLY 2"
3208 003355 1 002314 0 1 0 314 LDBR MUXSHF ;SET ROM TO LOAD SB
3209 003356 1 064211 3 2 0 10 11 MOVB DFRMAD
3210 003357 1 117617 4 7 1617 JMPSUB ENSS ;ENABLE SINGLE STEP AND SET "DX HIGH SPEED"
3211 003360 1 117541 4 7 1541 JMPSUB STXFRW ;SETUP FOR DEVICE WRITE XFER
3212 003361 1 117567 4 7 1567 JMPSUB STRMB ;START THE XFER
3213 003362 1 117531 4 7 1531 JMPSUB PULSE7 ;CLOCK DATA TO MRR AND SB
3214 003363 1 117600 4 7 1600 JMPSUB ABTXFR ;END THE XFER
3215 003364 1 117733 4 7 1733 JMPSUB MBPAR ;GO CHECK MASSBUS PARITY
3216 003365 1 115367 4 6 1367 JMPZ .+2 ;JUMP IF OKAY
3217 ERROR MDPPE3,DATA PARITY ERROR ON MASSBUS INTERFACE,^_
3218 003366 1 117754 4 7 1754 DIAG CLOCKED DATA FROM HOST TO DATA PATH INTERFACE
3219
3220 ERLOOP MDPPE3 ^SALL
3221 003367 1 002003 0 1 0 003
3222 003370 1 117746 4 7 1746
3223 003371 1 115350 4 6 1350
3224 003372 1 022000 1 1 0 00 00 DATI REG0,BR ;READ REG0
3225 003373 1 014000 0 6 0 000 SHR ;MOVE "DP PE FLAG" INTO BIT 0
3226 003374 1 105376 4 2 1376 JMPB0 .+2 ;JUMP IF SET, SHOULDN'T BE
3227 003375 1 101377 4 0 1377 JMP .+2 ;JUMP IF CLEAR
3228 ERROR MDPPE3,"DP PE FLAG" SET WHEN IT SHOULDN'T HAVE,^_
3229 <DIAG SET "CC 1" AND CLEARED "MSTR PE" AND "DIR TO MSTR"
3230 003376 1 117754 4 7 1754 THEN GENERATED 4 SINGLE STEP PULSES>
3231
3232 ERLOOP MDPPE3 ^SALL
3233 003377 1 002004 0 1 0 004
3234 003400 1 117746 4 7 1746
3235 003401 1 115350 4 6 1350
3236 003402 1 117406 4 7 1406 JMPSUB INITL ;DO A DEVICE RESET
3237
3238 003403 1 117756 4 7 1756 REPEAT TST
3239 003404 1 115256 4 6 1256
3240
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 23
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
3241 003405 1 101741 4 0 1741 JMP END ;JUMP AROUND SUBROUTINES
3242
3243 ;DO A MICROBUS INIT AND ZERO MEMORY POINTER.
3244 003406 1 002222 0 1 0 222 INITL: LDBR INIT+22 ;SET INIT
3245 003407 1 066371 3 3 0 17 11 MOVB IOSEL
3246 003410 1 002022 0 1 0 022 LDBR 22 ;CLR INIT & SELECT DP
3247 003411 1 066371 3 3 0 17 11 MOVB IOSEL
3248 003412 1 001000 0 0 2 000 LDMAR 0 ;PUT MEMORY ADDRESS TO 0
3249 003413 1 010000 0 4 0 000 LDMEM 0 ;CLR MEMORY LOC. 0
3250 003414 1 016000 0 7 0 000 RETURN
3251
3252 ;LOAD THE MC WITH A DATA PATTERN FROM MEMORY AND CLOCK THE MC.
3253 ;THEN READ THE "MC OF FLAG" BIT. RETURN WITH Z CLEARED IF IT IS SET
3254 ;AND Z SET IF IT IS CLEARED.
3255 003415 1 064011 3 2 0 00 11 MCFTST: MOVB REG0 ;CLEAR "MC OF FLAG"
3256 003416 1 002000 0 1 0 000 LDBR 0 ;CLEAR "DIAG MSTR REQ"
3257 003417 1 064031 3 2 0 01 11 MOVB REG1
3258 003420 1 045531 2 2 3 05 11 MOVMEM MCHI,I ;SET HI ORDER MC BITS
3259 003421 1 044111 2 2 0 04 11 MOVMEM MCLO ;SET LOW ORDER MC BITS
3260 003422 1 117505 4 7 1505 JMPSUB DEVWR ;SETUP DEVICE WRITE
3261 003423 1 064271 3 2 0 13 11 MOVB HSDPIN ;SET "MSTR RDY DLY 2"
3262 003424 1 002010 0 1 0 010 LDBR DMSTRQ ;SET "DIAG MSTR REQ"
3263 003425 1 064031 3 2 0 01 11 MOVB REG1
3264 003426 1 000000 0 0 0 000 NOP ;DELAY BEFORE DOING DATI
3265 003427 1 032100 1 5 0 04 00 DATI REG0,AC4 ;READ REG 0
3266 003430 1 062105 3 1 0 04 05 SHFTIT: SHL AC4,BR ;MOVE "MC OF FLAG" TO BIT 4
3267 003431 1 107433 4 3 1433 JMPB4 .+2 ;JUMP IF SET, SHOULDN'T BE
3268 003432 1 016377 0 7 0 377 RETURN -1 ;GIVE NO ERROR RETURN
3269 003433 1 016000 0 7 0 000 RETURN ;GIVE ERROR RETURN
3270
3271 ;THIS SUBROUTINE IS USED IN THE "BC OF FLAG" TEST.
3272 ;LOAD THE BC WITH DATA FROM MEMORY THEN GENERATE "SET SLVE ACK".
3273 ;CHECK "BC OF FLAG", RETURN WITH "Z" SET IF FLAG IS NOT SET.
3274 ;RETURN WITH "Z" CLEARED IF IT IS SET.
3275 003434 1 064011 3 2 0 00 11 BCFTST: MOVB REG0 ;WRITE REG 0 TO CLEAR FLAGS
3276 003435 1 002000 0 1 0 000 LDBR 0 ;CLEAR "SLVE REQ"
3277 003436 1 064031 3 2 0 01 11 MOVB REG1
3278 003437 1 045571 2 2 3 07 11 MOVMEM BCHI,I ;SET HI ORDER BC BITS
3279 003440 1 044151 2 2 0 06 11 MOVMEM BCLO ;SET LOW ORDER BC BITS
3280 003441 1 117500 4 7 1500 JMPSUB DEVRD ;SETUP DEVICE READ
3281 003442 1 064271 3 2 0 13 11 MOVB HSDPIN ;SET "SLVE RDY DLY 2"
3282 003443 1 002004 0 1 0 004 LDBR DSLVRQ ;SET "SLVE REQ"
3283 003444 1 064031 3 2 0 01 11 MOVB REG1
3284 003445 1 002373 0 1 0 373 LDBR 373 ;SET MASK OF ALL BUT "BC OF FLAG" BIT
3285 003446 1 072011 3 5 0 00 11 MOVB AC0 ;MOVE MASK TO AC0
3286 003447 1 022000 1 1 0 00 00 DATI REG0,BR ;READ REG 0
3287 003450 1 060012 3 0 0 00 12 LORCB AC0 ;IF BIT IS CLEAR, RESULT IS ALL ONES
3288 003451 1 115453 4 6 1453 JMPZ .+2 ;JUMP IF CLEAR
3289 003452 1 016000 0 7 0 000 RETURN ;GIVE ERROR RETURN
3290 003453 1 016377 0 7 0 377 RETURN -1 ;GIVE NO ERROR RETURN
3291
3292 ;SET "SLVE WOR END XFER" ON THE CB BOARD BY SETTING "STA IN".
3293 ;IT IS ASSUMED THAT "DX HIGH SPEED" AND "DIR TO MSTR" ARE SET.
3294 003454 1 002033 0 1 0 033 SWEX: LDBR 33 ;SELECT CHANNEL BUS INTERFACE
3295 003455 1 066371 3 3 0 17 11 MOVB IOSEL
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 23-1
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
3296 003456 1 002004 0 1 0 004 LDBR LOOPEN ;SET LOOP ENABLE
3297 003457 1 064031 3 2 0 01 11 MOVB CSR1
3298 003460 1 002001 0 1 0 001 LDBR STAINL ;SET "STA IN"
3299 003461 1 064051 3 2 0 02 11 MOVB TOR0
3300 003462 1 002022 0 1 0 022 RTRN: LDBR 22 ;SELECT DATA PATH
3301 003463 1 066371 3 3 0 17 11 MOVB IOSEL
3302 003464 1 016000 0 7 0 000 RETURN
3303
3304 ;CLEAR "SLVE WOR END XFER" ON THE CB BOARD BY CLEARING "STA IN".
3305 003465 1 002033 0 1 0 033 CLRSEX: LDBR 33 ;SELECT CHANNEL BUS INTERFACE
3306 003466 1 066371 3 3 0 17 11 MOVB IOSEL
3307 003467 1 002000 0 1 0 000 LDBR 0 ;CLEAR "STA IN"
3308 003470 1 064051 3 2 0 02 11 MOVB TOR0
3309 003471 1 002000 0 1 0 000 LDBR 0 ;CLEAR LOOP ENABLE
3310 003472 1 064031 3 2 0 01 11 MOVB CSR1
3311 003473 1 101462 4 0 1462 JMP RTRN
3312
3313 ;STORE DATA FROM MEMORY INTO GP REG 2 FOR ERROR PRINTOUTS.
3314 003474 1 002011 0 1 0 011 SETDAT: LDBR 11 ;SELECT MASSBUS INTERFACE
3315 003475 1 066371 3 3 0 17 11 MOVB IOSEL
3316 003476 1 044311 2 2 0 14 11 MOVMEM MPGP4 ;STORE DATA
3317 003477 1 101462 4 0 1462 JMP RTRN
3318
3319 ;SET "DIR TO MSTR" IN THE MASSBUS INTERFACE.
3320 003500 1 002011 0 1 0 011 DEVRD: LDBR 11 ;SELECT MASSBUS INTERFACE
3321 003501 1 066371 3 3 0 17 11 MOVB IOSEL
3322 003502 1 002000 0 1 0 000 LDBR 0 ;SETUP FOR DEVICE READ
3323 003503 1 064031 3 2 0 01 11 MOVB MPSCR1
3324 003504 1 101462 4 0 1462 JMP RTRN
3325
3326 ;CLEAR "DIR TO MSTR" IN THE MASSBUS INTERFACE.
3327 003505 1 002011 0 1 0 011 DEVWR: LDBR 11 ;SELECT MASSBUS INTERFACE
3328 003506 1 066371 3 3 0 17 11 MOVB IOSEL
3329 003507 1 002010 0 1 0 010 LDBR DTD ;SETUP FOR DEVICE WRITE
3330 003510 1 064031 3 2 0 01 11 MOVB MPSCR1
3331 003511 1 101462 4 0 1462 JMP RTRN
3332
3333 ;SETUP THE 18 BIT CORRECT AND ACTUAL DATA FOR ERROR PRINTOUTS.
3334 ;IT IS ASSUMED THAT THE CORRECT DATA IS IN MEMORY POINTED TO BY AC2.
3335 ;AND ACTUAL DATA IS IN AC0, AC4 AND AC5.
3336 003512 1 002011 0 1 0 011 SETUP: LDBR 11 ;SELECT MASSBUS INTERFACE
3337 003513 1 066371 3 3 0 17 11 MOVB IOSEL
3338 003514 1 117524 4 7 1524 JMPSUB SETCOR ;SETUP CORRECT DATA
3339 003515 1 062010 3 1 0 00 10 SETACT: MOV AC0,BR ;GET SB BITS 7-0
3340 003516 1 066111 3 3 0 04 11 MOVB MPGP14 ;STORE FOR PRINTOUT
3341 003517 1 062110 3 1 0 04 10 MOV AC4,BR ;GET SB BITS 15-8
3342 003520 1 066131 3 3 0 05 11 MOVB MPGP15 ;STORE FOR PRINTOUT
3343 003521 1 062130 3 1 0 05 10 MOV AC5,BR ;GET SB BITS 17-16
3344 003522 1 066171 3 3 0 07 11 MOVB MPGP17 ;STORE FOR PRINTOUT
3345 003523 1 101462 4 0 1462 JMP RTRN
3346
3347 ;STORE 18 BIT CORRECT DATA FOR ERROR PRINTOUTS. IT IS ASSUMED THAT THE
3348 ;DATA IS IN MEMORY POINTED TO BY AC2.
3349 003524 1 061050 3 0 2 02 10 SETCOR: MOV AC2,MAR ;SET MAR TO POINT TO CORRECT DATA
3350 003525 1 047451 2 3 3 02 11 MOVMEM MPGP12,I ;STORE IT FOR PRINTOUT
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 23-2
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
3351 003526 1 047471 2 3 3 03 11 MOVMEM MPGP13,I ;STORE IT FOR PRINTOUT
3352 003527 1 046151 2 3 0 06 11 MOVMEM MPGP16 ;STORE IT FOR PRINTOUT
3353 003530 1 016000 0 7 0 000 RETURN
3354
3355 ;GENERATED FROM 2 TO 7 SINGLE STEPS PULSES.
3356 003531 1 064251 3 2 0 12 11 PULSE7: MOVB CLKPLS ;GENERATE A SINGLE STEP PULSE
3357 003532 1 064251 3 2 0 12 11 PULSE6: MOVB CLKPLS ;GENERATE A SINGLE STEP PULSE
3358 003533 1 064251 3 2 0 12 11 PULSE5: MOVB CLKPLS ;GENERATE A SINGLE STEP PULSE
3359 003534 1 064251 3 2 0 12 11 PULSE4: MOVB CLKPLS ;GENERATE A SINGLE STEP PULSE
3360 003535 1 064251 3 2 0 12 11 PULSE3: MOVB CLKPLS ;GENERATE A SINGLE STEP PULSE
3361 003536 1 064251 3 2 0 12 11 PULSE2: MOVB CLKPLS ;GENERATE A SINGLE STEP PULSE
3362 003537 1 064251 3 2 0 12 11 MOVB CLKPLS ;GENERATE A SINGLE STEP PULSE
3363 003540 1 016000 0 7 0 000 RETURN
3364
3365 ;SETUP THE RH20 FOR A DEVICE WRITE. THEN SET "OCCUPIED"
3366 ;IN THE MASSBUS INTERFACE. WAIT FOR "RUN" TO SET. IF IT DOESN'T CONTINUE
3367 ;ANYWAY AND ALLOW THE TEST TO FAIL.
3368 003541 1 117760 4 7 1760 STXFRW: WRITE ;SETUP FOR A DEVICE WRITE
3369 003542 1 002011 0 1 0 011 LDBR 11 ;SELECT MASSBUS INTERFACE
3370 003543 1 066371 3 3 0 17 11 MOVB IOSEL
3371 003544 1 002030 0 1 0 030 LDBR DTD+OCC ;SET MASK OF BITS TO BE SET
3372 003545 1 064031 3 2 0 01 11 MOVB MPSCR1 ;AND WRITE IT TO STATUS REG
3373 003546 1 117557 4 7 1557 JMPSUB RUNWAT ;GO WAIT FOR "RUN" TO SET
3374 003547 1 101462 4 0 1462 JMP RTRN
3375
3376 ;SETUP THE RH20 FOR A DEVICE READ. THEN SET "DIR TO MSTR" AND "OCC"
3377 ;IN THE MASSBUS INTERFACE. WAIT FOR "RUN" TO SET. IF IT DOESN'T CONTINUE
3378 ;ANYWAY AND ALLOW THE TEST TO FAIL.
3379 003550 1 117762 4 7 1762 STXFRR: READ ;SETUP FOR A DEVICE READ
3380 003551 1 002011 0 1 0 011 LDBR 11 ;SELECT MASSBUS INTERFACE
3381 003552 1 066371 3 3 0 17 11 MOVB IOSEL
3382 003553 1 002020 0 1 0 020 LDBR OCC ;SET MASK OF BITS TO BE SET
3383 003554 1 064031 3 2 0 01 11 MOVB MPSCR1 ;AND WRITE IT TO STATUS REG
3384 003555 1 117557 4 7 1557 JMPSUB RUNWAT ;GO WAIT FOR "RUN" TO SET
3385 003556 1 101462 4 0 1462 JMP RTRN
3386
3387 ;WAIT FOR "RUN" TO SET IN THE MASSBUS INTERFACE.
3388 003557 1 002000 0 1 0 000 RUNWAT: LDBR 0 ;CLEAR WAIT CNT
3389 003560 1 072011 3 5 0 00 11 MOVB AC0
3390 003561 1 072003 3 5 0 00 03 RUNLP: INCR AC0 ;INC WAIT CNT
3391 003562 1 113566 4 5 1566 JMPC RUNBCK ;JUMP IF TIMED OUT, TEST WILL FAIL
3392 003563 1 022000 1 1 0 00 00 DATI MPSCR0,BR ;CHECK "RUN" BIT
3393 003564 1 105566 4 2 1566 JMPB0 .+2 ;JUMP IF SET
3394 003565 1 101561 4 0 1561 JMP RUNLP ;ELSE, KEEP WAITING
3395 003566 1 016000 0 7 0 000 RUNBCK: RETURN
3396
3397 ;START THE PREVIOUSLY SETUP DATA XFER BY SETTING "START" IN THE MASSBUS
3398 ;INTERFACE.
3399 003567 1 002011 0 1 0 011 STRMB: LDBR 11 ;SELECT MASSBUS INTERFACE
3400 003570 1 066371 3 3 0 17 11 MOVB IOSEL
3401 003571 1 032001 1 5 0 00 01 DATI MPSCR1,AC0 ;READ PRESENT STATE OF STATUS
3402 003572 1 002030 0 1 0 030 LDBR OCC+DTD ;SET MASK OF BITS TO KEEP
3403 003573 1 072013 3 5 0 00 13 LANDBR AC0
3404 003574 1 002004 0 1 0 004 LDBR START ;SET MASK OF START BIT
3405 003575 1 062014 3 1 0 00 14 LORB AC0,BR ;SET IT INTO PRESENT STATUS
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 23-3
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
3406 003576 1 064031 3 2 0 01 11 MOVB MPSCR1
3407 003577 1 101462 4 0 1462 JMP RTRN
3408
3409 ;ABORT THE XFER BY CLEARING "OCC" AND SETTING "EBL".
3410 003600 1 002011 0 1 0 011 ABTXFR: LDBR 11 ;SELECT MASSBUS INTERFACE
3411 003601 1 066371 3 3 0 17 11 MOVB IOSEL
3412 003602 1 002001 0 1 0 001 LDBR EBL ;SET MASK OF BIT TO BE SET
3413 003603 1 064031 3 2 0 01 11 MOVB MPSCR1 ;AND WRITE IT TO STATUS REG
3414 003604 1 101462 4 0 1462 JMP RTRN
3415
3416 ;SETUP XFER INFORMATION IN GP REGS FOR THE HOST. IT IS ASSUMED THAT
3417 ;THE DATA PATTERN NUMBER IS IN AC0 AND THAT THE XFER IS FOR 1 WORD AND
3418 ;1 BLOCK.
3419 003605 1 002011 0 1 0 011 SETCNT: LDBR 11 ;SELECT MASSBUS INTERFACE
3420 003606 1 066371 3 3 0 17 11 MOVB IOSEL
3421 003607 1 062010 3 1 0 00 10 MOV AC0,BR ;PUT DATA PATTERN NUMBER INTO BR
3422 003610 1 066011 3 3 0 00 11 MOVB MPGP10 ;AND STORE IT FOR HOST
3423 003611 1 002001 0 1 0 001 LDBR 1 ;SET XFER WORD CNT=1
3424 003612 1 064251 3 2 0 12 11 MOVB MPGP2
3425 003613 1 066031 3 3 0 01 11 MOVB MPGP11 ;SET BLOCK CNT=1
3426 003614 1 002000 0 1 0 000 LDBR 0 ;CLEAR HIGH ORDER WRD CNT BITS
3427 003615 1 064271 3 2 0 13 11 MOVB MPGP3
3428 003616 1 101462 4 0 1462 JMP RTRN
3429
3430 ;ENABLE SINGLE STEPPING AND SET "DX HIGH SPEED".
3431 003617 1 002000 0 1 0 000 ENSS: LDBR 0 ;ENABLE SINGLE STEP
3432 003620 1 064031 3 2 0 01 11 MOVB REG1
3433 003621 1 002001 0 1 0 001 LDBR DXHISP ;SET "DX HIGH SPEED"
3434 003622 1 064031 3 2 0 01 11 MOVB REG1
3435 003623 1 016000 0 7 0 000 RETURN
3436
3437 ;STORE THE ADDITIONAL PNT ROUTINE NUMBER FOR THE HOST TO USE IN
3438 ;ERROR PRINTOUTS. IT IS ASSUMED TO BE IN MEMORY.
3439 003624 1 002011 0 1 0 011 SETPNT: LDBR 11 ;SELECT MASSBUS INTERFACE
3440 003625 1 066371 3 3 0 17 11 MOVB IOSEL
3441 003626 1 044351 2 2 0 16 11 MOVMEM MPGP6 ;STORE ADDITIONAL PNT ROUTINE NUMBER
3442 003627 1 101462 4 0 1462 JMP RTRN
3443
3444 ;SETUP CB BOARD LOOPING. SINCE DATA WILL BE INVERTED, SET "EV PAR" SO
3445 ;ACTUAL DATA WILL HAVE ODD PARITY.
3446 003630 1 002033 0 1 0 033 CBLOOP: LDBR 33 ;SELECT CHANNEL BUS INTERFACE
3447 003631 1 066371 3 3 0 17 11 MOVB IOSEL
3448 003632 1 002045 0 1 0 045 LDBR LOOPEN+EVPAR+CHANL ;SET LOOP ENABLE AND EVEN PARITY
3449 003633 1 064031 3 2 0 01 11 MOVB CSR1 ;AND CHANNEL MODE
3450 003634 1 101462 4 0 1462 JMP RTRN
3451
3452 ;SET "SLVE REQ" ON CB BOARD BY TOGGLING "SRV IN". IT IS ASSUMED THAT
3453 ;LOOP ENABLE IS SET.
3454 003635 1 002033 0 1 0 033 SETSLV: LDBR 33 ;SELECT CHANNEL BUS INTERFACE
3455 003636 1 066371 3 3 0 17 11 MOVB IOSEL
3456 003637 1 101652 4 0 1652 JMP CLKIT1
3457 ;CLOCK THE DATA PROVIDED IN MEMORY ONTO THE SLAVE DATA LINES IN AN
3458 ;INVERTED FORM.
3459 003640 1 002033 0 1 0 033 CLKDT: LDBR 33 ;SELECT CHANNEL BUS INTERFACE
3460 003641 1 066371 3 3 0 17 11 MOVB IOSEL
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 23-4
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
3461 003642 1 042011 2 1 0 00 11 MOVMEM BR ;MOVE LOAD DATA TO BR
3462 003643 1 101651 4 0 1651 JMP CLKIT
3463 ;CLOCK THE DATA PROVIDED IN MEMORY ONTO THE SLAVE DATA LINES.
3464 003644 1 002033 0 1 0 033 CLKDAT: LDBR 33 ;SELECT CHANNEL BUS INTERFACE
3465 003645 1 066371 3 3 0 17 11 MOVB IOSEL
3466 003646 1 002000 0 1 0 000 LDBR 0 ;COMPUTE THE COMPLEMENT OF MEM CONTENTS
3467 003647 1 072011 3 5 0 00 11 MOVB AC0
3468 003650 1 042012 2 1 0 00 12 LORCM AC0,BR ;PUT IT IN BR
3469 003651 1 064231 3 2 0 11 11 CLKIT: MOVB BORLO ;LOAD DATA INTO BOR
3470 003652 1 002200 0 1 0 200 CLKIT1: LDBR SRVINL ;SET "SRV IN"
3471 003653 1 064071 3 2 0 03 11 MOVB TOR1
3472 003654 1 002000 0 1 0 000 LDBR 0 ;CLEAR "SRV IN"
3473 003655 1 064071 3 2 0 03 11 MOVB TOR1
3474 003656 1 101462 4 0 1462 JMP RTRN
3475
3476 ;READ DATA OFF THE SLAVE DATA LINES INTO AC0.
3477 003657 1 002033 0 1 0 033 RDDATA: LDBR 33 ;SELECT CHANNEL BUS INTERFACE
3478 003660 1 066371 3 3 0 17 11 MOVB IOSEL
3479 003661 1 064151 3 2 0 06 11 MOVB CLKDRL ;CLK DRLO REG ON CB BOARD
3480 003662 1 000000 0 0 0 000 NOP ;DELAY BEFORE DOING DATI
3481 003663 1 032006 1 5 0 00 06 DATI DRLO,AC0 ;READ DATA
3482 003664 1 101462 4 0 1462 JMP RTRN
3483
3484 ;READ THE CONTENTS OF THE AR AND COMPARE IT TO CORRECT DATA IN MEMORY.
3485 ;IF AR IS CORRECT, RETURN WITH "Z" SET. IF NOT, SETUP CORRECT AND ACTUAL
3486 ;IN GP REGS AND RETURN WITH "Z" CLEARED.
3487 003665 1 032013 1 5 0 00 13 ARCHK: DATI ARLO,AC0 ;READ AR BITS 7-0
3488 003666 1 032114 1 5 0 04 14 DATI ARHI,AC4 ;READ AR BITS 15-8
3489 003667 1 032135 1 5 0 05 15 DATI REG15,AC5 ;READ REG 15
3490 003670 1 041417 2 0 3 00 17 OSM AC0,I ;CHECK IF CORRECT
3491 003671 1 115673 4 6 1673 JMPZ .+2 ;JUMP IF CORRECT
3492 003672 1 101704 4 0 1704 JMP ARERR ;ELSE, SETUP PRINTOUT DATA
3493 003673 1 041517 2 0 3 04 17 OSM AC4,I ;CHECK IF CORRECT
3494 003674 1 115676 4 6 1676 JMPZ .+2 ;JUMP IF CORRECT
3495 003675 1 101704 4 0 1704 JMP ARERR ;ELSE, SETUP PRINTOUT DATA
3496 003676 1 002003 0 1 0 003 LDBR AR1716 ;SET MASK OF AR BITS 17-16
3497 003677 1 072133 3 5 0 05 13 LANDBR AC5 ;ISOLATE THOSE BITS
3498 003700 1 040137 2 0 0 05 17 OSM AC5 ;CHECK IF CORRECT
3499 003701 1 115703 4 6 1703 JMPZ .+2 ;JUMP IF CORRECT
3500 003702 1 101704 4 0 1704 JMP ARERR ;ELSE, SETUP PRINTOUT DATA
3501 003703 1 016377 0 7 0 377 RETURN -1 ;GIVE NO ERROR RETURN
3502
3503 003704 1 002011 0 1 0 011 ARERR: LDBR 11 ;SELECT MASSBUS INTERFACE
3504 003705 1 066371 3 3 0 17 11 MOVB IOSEL
3505 003706 1 062010 3 1 0 00 10 MOV AC0,BR ;MOVE AR BITS 7-0 INTO BR
3506 003707 1 066111 3 3 0 04 11 MOVB MPGP14 ;AND STORE THEM FOR PRINTOUT
3507 003710 1 062110 3 1 0 04 10 MOV AC4,BR ;MOVE AR BITS 15-8 IN BR
3508 003711 1 066131 3 3 0 05 11 MOVB MPGP15 ;AND STORE THEM FOR PRINTOUT
3509 003712 1 062130 3 1 0 05 10 MOV AC5,BR ;MOVE AR BITS 17-16 INTO BR
3510 003713 1 066171 3 3 0 07 11 MOVB MPGP17 ;AND STORE THEM FOR PRINTOUT
3511 003714 1 117524 4 7 1524 JMPSUB SETCOR ;GO SETUP CORRECT DATA
3512 003715 1 062070 3 1 0 03 10 MOV AC3,BR ;STORE SHIFT CNT/MSK FOR PRINTOUT
3513 003716 1 064331 3 2 0 15 11 MOVB MPGP5
3514 003717 1 101462 4 0 1462 JMP RTRN
3515
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 23-5
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
3516 ;READ AR BITS 8-1 (OUTPUT FROM MUX) AND COMPARE IT TO CORRECT DATA IN MEMORY.
3517 ;IF IT IS CORRECT, RETURN WITH "Z" SET. IF NOT, RETURN WITH "Z" CLEARED.
3518 003720 1 022013 1 1 0 00 13 ARCHK7: DATI ARLO,BR ;READ AR BITS 7-0
3519 003721 1 034014 1 6 0 00 14 DATI ARHI,BRSR ;PUT AR BITS 8-1 INTO BR
3520 003722 1 072011 3 5 0 00 11 MOVB AC0 ;MOVE INTO AC0 FOR COMPARE
3521 003723 1 040017 2 0 0 00 17 OSM AC0 ;CHECK IF DATA CORRECT
3522 003724 1 115726 4 6 1726 JMPZ .+2 ;JUMP IF CORRECT
3523 003725 1 016000 0 7 0 000 RETURN ;GIVE ERROR RETURN
3524 003726 1 016377 0 7 0 377 RETURN -1 ;GO NO ERROR RETURN
3525
3526 ;GENERATE 4 SINGLE STEP PULSES TO CLOCK DATA FROM THE SB INTO THE AR.
3527 ;THEN READ THE AR BITS (8-1) INTO THE BR.
3528 003727 1 117534 4 7 1534 GETAR: JMPSUB PULSE4 ;CLOCK SB DATA INTO AR
3529 003730 1 022013 1 1 0 00 13 DATI ARLO,BR ;READ BITS 7-0 0F AR
3530 003731 1 034014 1 6 0 00 14 DATI ARHI,BRSR ;CREATE AR BITS 8-1 IN BR
3531 003732 1 016000 0 7 0 000 RETURN
3532
3533 ;CHECK IF "DP PARITY ERROR" SET IN THE MASSBUS INTERFACE.
3534 003733 1 002011 0 1 0 011 MBPAR: LDBR 11 ;SELECT MASSBUS INTERFACE
3535 003734 1 066371 3 3 0 17 11 MOVB IOSEL
3536 003735 1 032107 1 5 0 04 07 DATI MPDB2,AC4 ;READ BUFFER WITH PE BIT
3537 003736 1 002022 0 1 0 022 LDBR 22 ;SELECT DATA PATH
3538 003737 1 066371 3 3 0 17 11 MOVB IOSEL
3539 003740 1 101430 4 0 1430 JMP SHFTIT ;GO SHIFT AND TEST PARITY BIT
3540
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 24
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
3541 003741 1 002225 0 1 0 225 END: .ECRAM
3542 003742 1 160211 7 0 0 10 11
3543 003743 1 072131 3 5 0 05 11
3544 003744 1 002044 0 1 0 044
3545 003745 1 160211 7 0 0 10 11
3546 003746 1 072131 3 5 0 05 11
3547 003747 1 002142 0 1 0 142
3548 003750 1 160211 7 0 0 10 11
3549 003751 1 072131 3 5 0 05 11
3550 003752 1 002146 0 1 0 146
3551 003753 1 160211 7 0 0 10 11
3552 003754 1 002104 0 1 0 104
3553 003755 1 160211 7 0 0 10 11
3554 003756 1 002222 0 1 0 222
3555 003757 1 160211 7 0 0 10 11
3556 003760 1 002001 0 1 0 001
3557 003761 1 101765 4 0 1765
3558 003762 1 002002 0 1 0 002
3559 003763 1 101765 4 0 1765
3560 003764 1 002003 0 1 0 003
3561 003765 1 072131 3 5 0 05 11
3562 003766 1 002203 0 1 0 203
3563 003767 1 160211 7 0 0 10 11
3564 003770 1 072131 3 5 0 05 11
3565 003771 1 002215 0 1 0 215
3566 003772 1 160211 7 0 0 10 11
3567 003773 777777 777777 .MEM
3568 000000 000000 000000 0 ;FIRST MEM LOC IS FOR SCRATCH
3569 000001 000000 000377 CTR1: 377
3570 000002 000000 000360 360
3571 000003 000000 000377 CTR2: 377
3572 000004 000000 000017 17
3573 000005 000000 000360 CTR3: 360
3574 000006 000000 000377 377
3575 000007 000000 000017 CTR4: 17
3576 000010 000000 000377 377
3577 000011 000000 000000 CNTCOR: 0
3578 000012 000000 000001 1
3579 000013 000000 000000 0
3580 000014 000000 000002 2
3581 000015 000000 000000 0
3582 000016 000000 000004 4
3583 000017 000000 000000 0
3584 000020 000000 000010 10
3585 000021 000000 000000 0
3586 000022 000000 000020 20
3587 000023 000000 000000 0
3588 000024 000000 000040 40
3589 000025 000000 000000 0
3590 000026 000000 000100 100
3591 000027 000000 000000 0
3592 000030 000000 000200 200
3593 000031 000000 000001 1
3594 000032 000000 000000 0
3595 000033 000000 000002 2
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 24-1
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
3596 000034 000000 000000 0
3597 000035 000000 000004 4
3598 000036 000000 000000 0
3599 000037 000000 000010 10
3600 000040 000000 000000 0
3601 000041 000000 000020 20
3602 000042 000000 000000 0
3603 000043 000000 000040 40
3604 000044 000000 000000 0
3605 000045 000000 000100 100
3606 000046 000000 000000 0
3607 000047 000000 000200 200
3608 000050 000000 000000 0
3609 000051 000000 000000 0
3610 000052 000000 000361 361
3611 000053 000000 000017 17
3612 000054 000000 000020 20
3613 000055 000000 000017 17
3614 000056 000000 000361 361
3615 000057 000000 000000 CNTDAT: 0
3616 000060 000000 000000 0
3617 000061 000000 000000 0
3618 000062 000000 000001 1
3619 000063 000000 000000 0
3620 000064 000000 000003 3
3621 000065 000000 000000 0
3622 000066 000000 000007 7
3623 000067 000000 000000 0
3624 000070 000000 000017 17
3625 000071 000000 000000 0
3626 000072 000000 000037 37
3627 000073 000000 000000 0
3628 000074 000000 000077 77
3629 000075 000000 000000 0
3630 000076 000000 000177 177
3631 000077 000000 000000 0
3632 000100 000000 000377 377
3633 000101 000000 000001 1
3634 000102 000000 000377 377
3635 000103 000000 000003 3
3636 000104 000000 000377 377
3637 000105 000000 000007 7
3638 000106 000000 000377 377
3639 000107 000000 000017 17
3640 000110 000000 000377 377
3641 000111 000000 000037 37
3642 000112 000000 000377 377
3643 000113 000000 000077 77
3644 000114 000000 000377 377
3645 000115 000000 000177 177
3646 000116 000000 000377 377
3647 000117 000000 000000 0
3648 000120 000000 000360 360
3649 000121 000000 000017 17
3650 000122 000000 000017 17
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 24-2
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
3651 000123 000000 000017 17
3652 000124 000000 000360 360
3653 000125 000000 000000 0
3654 000126 000000 000000 0
3655 000127 000000 000000 0
3656 000130 000000 000000 0
3657 000131 000000 000000 0
3658 000132 000000 000000 0
3659 000133 000000 000000 0
3660 000134 000000 000000 0
3661 000135 000000 000000 0
3662 000136 000000 000000 0
3663 000137 000000 000000 0
3664 000140 000000 000000 0
3665 000141 000000 000000 0
3666 000142 000000 000000 0
3667 000143 000000 000000 0
3668 000144 000000 000000 0
3669 000145 000000 000000 0
3670 000146 000000 000000 0
3671 000147 000000 000000 0
3672 000150 000000 000000 0
3673 000151 000000 000000 0
3674 000152 000000 000000 0
3675 000153 000000 000000 0
3676 000154 000000 000000 0
3677 000155 000000 000000 0
3678 000156 000000 000000 0
3679 000157 000000 000000 0
3680 000160 000000 000000 0
3681 000161 000000 000000 0
3682 000162 000000 000000 0
3683 000163 000000 000000 0
3684 000164 000000 000000 0
3685 000165 000000 000000 0
3686 000166 000000 000000 0
3687 000167 000000 000000 0
3688 000170 000000 000000 0
3689 000171 000000 000000 0
3690 000172 000000 000000 0
3691 000173 000000 000000 0
3692 000174 000000 000000 0
3693 000175 000000 000000 0
3694 000176 000000 000000 0
3695 000177 000000 000000 0
3696 000200 000000 000000 0
3697 000201 000000 000000 0
3698 000202 000000 000000 0
3699 000203 000000 000000 0
3700 000204 000000 000000 0
3701 000205 000000 000000 0
3702 000206 000000 000000 0
3703 000207 000000 000000 0
3704 000210 000000 000000 0
3705 000211 000000 000000 0
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 24-3
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
3706 000212 000000 000000 0
3707 000213 000000 000000 0
3708 000214 000000 000000 0
3709 000215 000000 000000 0
3710 000216 000000 000000 0
3711 000217 000000 000000 0
3712 000220 000000 000000 0
3713 000221 000000 000000 0
3714 000222 000000 000000 0
3715 000223 000000 000000 0
3716 000224 000000 000000 0
3717 000225 000000 000000 0
3718 000226 000000 000000 0
3719 000227 000000 000000 0
3720 000230 000000 000000 0
3721 000231 000000 000000 0
3722 000232 000000 000000 0
3723 000233 000000 000000 0
3724 000234 000000 000000 0
3725 000235 000000 000000 0
3726 000236 000000 000000 0
3727 000237 000000 000000 0
3728 000240 000000 000000 0
3729 000241 000000 000000 0
3730 000242 000000 000000 0
3731 000243 000000 000000 0
3732 000244 000000 000000 0
3733 000245 000000 000000 0
3734 000246 000000 000000 0
3735 000247 000000 000000 0
3736 000250 000000 000000 0
3737 000251 000000 000000 0
3738 000252 000000 000000 0
3739 000253 000000 000000 0
3740 000254 000000 000000 0
3741 000255 000000 000000 0
3742 000256 000000 000000 0
3743 000257 000000 000000 0
3744 000260 000000 000000 0
3745 000261 000000 000000 0
3746 000262 000000 000000 0
3747 000263 000000 000000 0
3748 000264 000000 000000 0
3749 000265 000000 000000 0
3750 000266 000000 000000 0
3751 000267 000000 000000 0
3752 000270 000000 000000 0
3753 000271 000000 000000 0
3754 000272 000000 000000 0
3755 000273 000000 000000 0
3756 000274 000000 000000 0
3757 000275 000000 000000 0
3758 000276 000000 000000 0
3759 000277 000000 000000 0
3760 000300 000000 000000 0
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 24-4
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
3761 000301 000000 000000 0
3762 000302 000000 000000 0
3763 000303 000000 000000 0
3764 000304 000000 000000 0
3765 000305 000000 000000 0
3766 000306 000000 000000 0
3767 000307 000000 000000 0
3768 000310 000000 000000 0
3769 000311 000000 000000 0
3770 000312 000000 000000 0
3771 000313 000000 000000 0
3772 000314 000000 000000 0
3773 000315 000000 000000 0
3774 000316 000000 000000 0
3775 000317 000000 000000 0
3776 000320 000000 000000 0
3777 000321 000000 000000 0
3778 000322 000000 000000 0
3779 000323 000000 000000 0
3780 000324 000000 000000 0
3781 000325 000000 000000 0
3782 000326 000000 000000 0
3783 000327 000000 000000 0
3784 000330 000000 000000 0
3785 000331 000000 000000 0
3786 000332 000000 000000 0
3787 000333 000000 000000 0
3788 000334 000000 000000 0
3789 000335 000000 000000 0
3790 000336 000000 000000 0
3791 000337 000000 000000 0
3792 000340 000000 000000 0
3793 000341 000000 000000 0
3794 000342 000000 000000 0
3795 000343 000000 000000 0
3796 000344 000000 000000 0
3797 000345 000000 000000 0
3798 000346 000000 000000 0
3799 000347 000000 000000 0
3800 000350 000000 000000 0
3801 000351 000000 000000 0
3802 000352 000000 000000 0
3803 000353 000000 000000 0
3804 000354 000000 000000 0
3805 000355 000000 000000 0
3806 000356 000000 000000 0
3807 000357 000000 000000 0
3808 000360 000000 000000 0
3809 000361 000000 000000 0
3810 000362 000000 000000 0
3811 000363 000000 000000 0
3812 000364 000000 000000 0
3813 000365 000000 000000 0
3814 000366 000000 000000 0
3815 000367 000000 000000 0
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 24-5
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
3816 000370 000000 000000 0
3817 000371 000000 000000 0
3818 000372 000000 000000 0
3819 000373 000000 000000 0
3820 000374 000000 000000 0
3821 000375 000000 000000 0
3822 000376 000000 000000 0
3823 000377 000000 000000 0
3824 ;START OF 2ND 256 WORD BLOCK OF WORKING MEMORY
3825 000400 000000 000000 0
3826 000401 000000 000001 DPDAT: 1
3827 000402 000000 000002 2
3828 000403 000000 000004 4
3829 000404 000000 000010 10
3830 000405 000000 000020 20
3831 000406 000000 000040 40
3832 000407 000000 000100 100
3833 000410 000000 000200 200
3834 000411 777777 777777 -1
3835 000412 000000 000040 ARDATS: ARDA0&377
3836 000413 000000 000150 ARDA1&377
3837 000414 000000 000046 ARDA2&377
3838 000415 000000 000200 ARDA3&377
3839 000416 000000 000054 ARDA4&377
3840 000417 000000 000057 ARDA5&377
3841 000420 000000 000062 ARDA6&377
3842 000421 000000 000200 ARDA7&377
3843 000422 000000 000070 ARDA10&377
3844 000423 000000 000073 ARDA11&377
3845 000424 000000 000076 ARDA12&377
3846 000425 000000 000101 ARDA13&377
3847 000426 000000 000104 ARDA14&377
3848 000427 000000 000120 ARDA15&377
3849 000430 000000 000112 ARDA16&377
3850 000431 000000 000115 ARDA17&377
3851 000432 000000 000000 AR0S: 0
3852 000433 000000 000000 0
3853 000434 000000 000000 0
3854 000435 000000 000377 AR1S: 377
3855 000436 000000 000000 0
3856 000437 000000 000000 0
3857 000440 000000 000001 ARDA0: 1
3858 000441 000000 000000 0
3859 000442 000000 000000 0
3860 000443 000000 000002 2
3861 000444 000000 000000 0
3862 000445 000000 000000 0
3863 000446 000000 000004 ARDA2: 4
3864 000447 000000 000000 0
3865 000450 000000 000000 0
3866 000451 000000 000010 10
3867 000452 000000 000000 0
3868 000453 000000 000000 0
3869 000454 000000 000020 ARDA4: 20
3870 000455 000000 000000 0
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 24-6
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
3871 000456 000000 000000 0
3872 000457 000000 000040 ARDA5: 40
3873 000460 000000 000000 0
3874 000461 000000 000000 0
3875 000462 000000 000100 ARDA6: 100
3876 000463 000000 000000 0
3877 000464 000000 000000 0
3878 000465 000000 000200 200
3879 000466 000000 000000 0
3880 000467 000000 000000 0
3881 000470 000000 000000 ARDA10: 0
3882 000471 000000 000001 1
3883 000472 000000 000000 0
3884 000473 000000 000000 ARDA11: 0
3885 000474 000000 000002 2
3886 000475 000000 000000 0
3887 000476 000000 000000 ARDA12: 0
3888 000477 000000 000004 4
3889 000500 000000 000000 0
3890 000501 000000 000000 ARDA13: 0
3891 000502 000000 000010 10
3892 000503 000000 000000 0
3893 000504 000000 000000 ARDA14: 0
3894 000505 000000 000020 20
3895 000506 000000 000000 0
3896 000507 000000 000000 0
3897 000510 000000 000040 40
3898 000511 000000 000000 0
3899 000512 000000 000000 ARDA16: 0
3900 000513 000000 000100 100
3901 000514 000000 000000 0
3902 000515 000000 000000 ARDA17: 0
3903 000516 000000 000200 200
3904 000517 000000 000000 0
3905 000520 000000 000000 ARDA15: 0
3906 000521 000000 000000 0
3907 000522 000000 000001 1
3908 000523 000000 000000 0
3909 000524 000000 000000 0
3910 000525 000000 000002 2
3911 000526 000000 000001 1
3912 000527 000000 000000 0
3913 000530 000000 000000 0
3914 000531 000000 000002 2
3915 000532 000000 000000 0
3916 000533 000000 000000 0
3917 000534 000000 000004 4
3918 000535 000000 000000 0
3919 000536 000000 000000 0
3920 000537 000000 000010 10
3921 000540 000000 000000 0
3922 000541 000000 000000 0
3923 000542 000000 000020 20
3924 000543 000000 000000 0
3925 000544 000000 000000 0
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 24-7
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
3926 000545 000000 000040 40
3927 000546 000000 000000 0
3928 000547 000000 000000 0
3929 000550 000000 000002 ARDA1: 2
3930 000551 000000 000000 0
3931 000552 000000 000000 0
3932 000553 000000 000004 4
3933 000554 000000 000000 0
3934 000555 000000 000000 0
3935 000556 000000 000010 10
3936 000557 000000 000000 0
3937 000560 000000 000000 0
3938 000561 000000 000020 20
3939 000562 000000 000000 0
3940 000563 000000 000000 0
3941 000564 000000 000040 40
3942 000565 000000 000000 0
3943 000566 000000 000000 0
3944 000567 000000 000100 100
3945 000570 000000 000000 0
3946 000571 000000 000000 0
3947 000572 000000 000200 200
3948 000573 000000 000000 0
3949 000574 000000 000000 0
3950 000575 000000 000001 1
3951 000576 000000 000000 0
3952 000577 000000 000000 0
3953 000600 ARDA3:
3954 000600 000000 000000 ARDA7: 0
3955 000601 000000 000000 0
3956 000602 000000 000000 0
3957 000603 000000 000000 0
3958 000604 000000 000000 0
3959 000605 000000 000000 0
3960 000606 000000 000000 0
3961 000607 000000 000000 0
3962 000610 000000 000000 0
3963 000611 000000 000000 0
3964 000612 000000 000000 0
3965 000613 000000 000000 0
3966 000614 000000 000000 0
3967 000615 000000 000000 0
3968 000616 000000 000000 0
3969 000617 000000 000000 0
3970 000620 000000 000000 0
3971 000621 000000 000000 0
3972 000622 000000 000000 0
3973 000623 000000 000000 0
3974 000624 000000 000000 0
3975 000625 000000 000000 0
3976 000626 000000 000000 0
3977 000627 000000 000000 0
3978 000630 777777 777777 SDPAT: -1
3979 000631 000000 000000 0
3980 000632 000000 000376 376
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 24-8
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
3981 000633 000000 000375 375
3982 000634 000000 000373 373
3983 000635 000000 000367 367
3984 000636 000000 000357 357
3985 000637 000000 000337 337
3986 000640 000000 000277 277
3987 000641 000000 000177 177
3988 000642 000000 000001 1
3989 000643 000000 000002 2
3990 000644 000000 000004 4
3991 000645 000000 000010 10
3992 000646 000000 000020 20
3993 000647 000000 000040 40
3994 000650 000000 000100 100
3995 000651 000000 000200 200
3996 000652 777777 777777 CBPAT: -1
3997 000653 777777 777777 -1
3998 000654 000000 000000 0
3999 000655 000000 000000 0
4000 000656 000000 000374 374
4001 000657 000000 000001 1
4002 000660 000000 000372 372
4003 000661 000000 000001 1
4004 000662 000000 000366 366
4005 000663 000000 000001 1
4006 000664 000000 000356 356
4007 000665 000000 000001 1
4008 000666 000000 000336 336
4009 000667 000000 000001 1
4010 000670 000000 000276 276
4011 000671 000000 000001 1
4012 000672 000000 000176 176
4013 000673 000000 000001 1
4014 000674 000000 000376 376
4015 000675 000000 000000 0
4016 000676 000000 000002 2
4017 000677 000000 000000 0
4018 000700 000000 000004 4
4019 000701 000000 000000 0
4020 000702 000000 000010 10
4021 000703 000000 000000 0
4022 000704 000000 000020 20
4023 000705 000000 000000 0
4024 000706 000000 000040 40
4025 000707 000000 000000 0
4026 000710 000000 000100 100
4027 000711 000000 000000 0
4028 000712 000000 000200 200
4029 000713 000000 000000 0
4030 000714 000000 000000 0
4031 000715 000000 000001 1
4032 000716 000000 000000 0
4033 000717 000000 000000 0
4034 000720 000000 000000 0
4035 000721 000000 000000 0
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 24-9
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
4036 000722 000000 000000 0
4037 000723 000000 000000 0
4038 000724 000000 000000 0
4039 000725 000000 000000 0
4040 000726 000000 000000 0
4041 000727 000000 000000 0
4042 000730 000000 000000 0
4043 000731 000000 000000 0
4044 000732 000000 000000 0
4045 000733 000000 000000 0
4046 000734 000000 000000 0
4047 000735 000000 000000 0
4048 000736 000000 000000 0
4049 000737 000000 000000 0
4050 000740 000000 000000 0
4051 000741 000000 000000 0
4052 000742 000000 000000 0
4053 000743 000000 000000 0
4054 000744 000000 000000 0
4055 000745 000000 000000 0
4056 000746 000000 000000 0
4057 000747 000000 000000 0
4058 000750 000000 000000 0
4059 000751 000000 000000 0
4060 000752 000000 000000 0
4061 000753 000000 000000 0
4062 000754 000000 000000 0
4063 000755 000000 000000 0
4064 000756 000000 000000 0
4065 000757 000000 000000 0
4066 000760 000000 000000 0
4067 000761 000000 000000 0
4068 000762 000000 000000 0
4069 000763 000000 000000 0
4070 000764 000000 000000 0
4071 000765 000000 000000 0
4072 000766 000000 000000 0
4073 000767 000000 000000 0
4074 000770 000000 000000 0
4075 000771 000000 000000 0
4076 000772 000000 000000 0
4077 000773 000000 000000 0
4078 000774 000000 000000 0
4079 000775 000000 000000 0
4080 000776 000000 000000 0
4081 000777 000000 000000 0
4082 ;START OF 3RD 256 WORD BLOCK OF WORKING MEMORY
4083 001000 000000 000000 0
4084 001001 000000 000377 MUXDT1: 377
4085 001002 000000 000377 377
4086 001003 000000 000003 3
4087 001004 000000 000000 0
4088 001005 000000 000000 0
4089 001006 000000 000000 0
4090 001007 000000 000001 MUXDAT: 1
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 24-10
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
4091 001010 000000 000000 0
4092 001011 000000 000000 0
4093 001012 000000 000002 2
4094 001013 000000 000000 0
4095 001014 000000 000000 0
4096 001015 000000 000004 4
4097 001016 000000 000000 0
4098 001017 000000 000000 0
4099 001020 000000 000010 10
4100 001021 000000 000000 0
4101 001022 000000 000000 0
4102 001023 000000 000020 20
4103 001024 000000 000000 0
4104 001025 000000 000000 0
4105 001026 000000 000040 40
4106 001027 000000 000000 0
4107 001030 000000 000000 0
4108 001031 000000 000100 100
4109 001032 000000 000000 0
4110 001033 000000 000000 0
4111 001034 000000 000200 200
4112 001035 000000 000000 0
4113 001036 000000 000000 0
4114 001037 000000 000000 0
4115 001040 000000 000001 1
4116 001041 000000 000000 0
4117 001042 000000 000000 0
4118 001043 000000 000002 2
4119 001044 000000 000000 0
4120 001045 000000 000000 0
4121 001046 000000 000004 4
4122 001047 000000 000000 0
4123 001050 000000 000000 0
4124 001051 000000 000010 10
4125 001052 000000 000000 0
4126 001053 000000 000000 0
4127 001054 000000 000020 20
4128 001055 000000 000000 0
4129 001056 000000 000000 0
4130 001057 000000 000040 40
4131 001060 000000 000000 0
4132 001061 000000 000000 0
4133 001062 000000 000100 100
4134 001063 000000 000000 0
4135 001064 000000 000000 0
4136 001065 000000 000200 200
4137 001066 000000 000000 0
4138 001067 000000 000000 0
4139 001070 000000 000000 0
4140 001071 000000 000001 1
4141 001072 000000 000000 0
4142 001073 000000 000000 0
4143 001074 000000 000002 2
4144 001075 777777 777777 -1
4145 001076 000000 000130 ARDATM: ARDM0&377
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 24-11
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
4146 001077 000000 000161 ARDM1&377
4147 001100 000000 000126 ARDM2&377
4148 001101 000000 000203 ARDM3&377
4149 001102 000000 000124 ARDM4&377
4150 001103 000000 000123 ARDM5&377
4151 001104 000000 000122 ARDM6&377
4152 001105 000000 000225 ARDM7&377
4153 001106 000000 000120 ARDM10&377
4154 001107 000000 000117 ARDM11&377
4155 001110 000000 000116 ARDM12&377
4156 001111 000000 000137 ARDM13&377
4157 001112 000000 000136 ARDM14&377
4158 001113 000000 000132 ARDM15&377
4159 001114 000000 000134 ARDM16&377
4160 001115 000000 000133 ARDM17&377
4161 001116 000000 000000 ARDM12: 0
4162 001117 000000 000000 ARDM11: 0
4163 001120 000000 000000 ARDM10: 0
4164 001121 000000 000000 0
4165 001122 000000 000000 ARDM6: 0
4166 001123 000000 000000 ARDM5: 0
4167 001124 000000 000000 ARDM4: 0
4168 001125 000000 000000 0
4169 001126 000000 000000 ARDM2: 0
4170 001127 000000 000000 0
4171 001130 000000 000001 ARDM0: 1
4172 001131 000000 000002 2
4173 001132 000000 000004 ARDM15: 4
4174 001133 000000 000010 ARDM17: 10
4175 001134 000000 000020 ARDM16: 20
4176 001135 000000 000040 40
4177 001136 000000 000100 ARDM14: 100
4178 001137 000000 000200 ARDM13: 200
4179 001140 000000 000000 0
4180 001141 000000 000000 0
4181 001142 000000 000000 0
4182 001143 000000 000000 0
4183 001144 000000 000000 0
4184 001145 000000 000000 0
4185 001146 000000 000000 0
4186 001147 000000 000000 0
4187 001150 000000 000000 0
4188 001151 000000 000000 0
4189 001152 000000 000001 1
4190 001153 000000 000002 2
4191 001154 000000 000004 4
4192 001155 000000 000010 10
4193 001156 000000 000020 20
4194 001157 000000 000040 40
4195 001160 000000 000100 100
4196 001161 000000 000200 ARDM1: 200
4197 001162 000000 000001 1
4198 001163 000000 000002 2
4199 001164 000000 000004 4
4200 001165 000000 000010 10
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 24-12
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
4201 001166 000000 000020 20
4202 001167 000000 000040 40
4203 001170 000000 000100 100
4204 001171 000000 000000 0
4205 001172 000000 000000 0
4206 001173 000000 000000 0
4207 001174 000000 000000 0
4208 001175 000000 000000 0
4209 001176 000000 000000 0
4210 001177 000000 000000 0
4211 001200 000000 000000 0
4212 001201 000000 000000 0
4213 001202 000000 000000 0
4214 001203 000000 000000 ARDM3: 0
4215 001204 000000 000000 0
4216 001205 000000 000000 0
4217 001206 000000 000000 0
4218 001207 000000 000000 0
4219 001210 000000 000000 0
4220 001211 000000 000000 0
4221 001212 000000 000000 0
4222 001213 000000 000000 0
4223 001214 000000 000000 0
4224 001215 000000 000000 0
4225 001216 000000 000000 0
4226 001217 000000 000000 0
4227 001220 000000 000000 0
4228 001221 000000 000000 0
4229 001222 000000 000000 0
4230 001223 000000 000000 0
4231 001224 000000 000000 0
4232 001225 000000 000377 ARDM7: 377
4233 001226 000000 000377 377
4234 001227 000000 000377 377
4235 001230 000000 000377 377
4236 001231 000000 000377 377
4237 001232 000000 000377 377
4238 001233 000000 000377 377
4239 001234 000000 000377 377
4240 001235 000000 000377 377
4241 001236 000000 000377 377
4242 001237 000000 000377 377
4243 001240 000000 000377 377
4244 001241 000000 000377 377
4245 001242 000000 000377 377
4246 001243 000000 000377 377
4247 001244 000000 000377 377
4248 001245 000000 000377 377
4249 001246 000000 000377 377
4250 .END
4251
4252 END
NO ERRORS DETECTED
MCODE5 DX20 MICRO-DIAGNOSTIC OF THE DATA PATH - PART 2 VERSION 0.1 MACRO %53B(1252) 15:53 6-Mar-89 Page 24-13
MCOD5M MAC 6-Mar-89 15:13 DATA PATH TEST - PART 2
PROGRAM BREAK IS 000000
ABSOLUTE BREAK IS 005243
CPU TIME USED 02:55.539
31P CORE USED
ABTXFR 2588 2614 2637 2664 2696 2712 2772 2862 3055 3214 3410#
AC0 754 867 876 884 932 933 956 957 972 973 1217 1226 1234 1282
1284 1306 1308 1323 1325 1509 1569 1603 1685 1688 2324 2590 2747 2775
2784 2836 2861 2878 2897 2898 2962 2973 3038 3083 3084 3193 3285 3287
3339 3389 3390 3401 3403 3405 3421 3467 3468 3481 3487 3490 3505 3520
3521
AC1 752 855 899 1205 1249 1488 1519 1644 1700 2007 2011 2039 2040 2156
2173 2188 2189 2227 2241 2258 2259 2301 2337 2439 2443 2464 2465 2499
2505 2524 2539 2561 2562 2865 2881
AC2 851 856 871 897 898 1201 1206 1221 1247 1248 2028 2093 2131 2154
2176 2187 2230 2240 2247 2257 2305 2313 2335 2336 2506 2545 2554 2754
2783 2800 2843 2877 2903 3044 3089 3349
AC3 853 878 883 895 896 1203 1228 1233 1245 1246 2095 2133 2158 2185
2219 2229 2234 2263 2264 2303 2323 2334 2508 2523 2556 2557 2867 2885
2886 3512
AC4 682 687 868 874 887 1218 1224 1237 2776 2787 2857 2864 2959 2976
3265 3266 3341 3488 3493 3507 3536
AC5 650 652 654 660 694 695 697 716 718 723 727 732 735 738
743 749 756 779 781 790 792 2777 2779 2790 2854 2866 2954 2956
2979 3343 3489 3497 3498 3509 3543 3546 3549 3561 3564
AC6 663 667 677 801
AC7 635 670 671 704 709 713 717 730 733
AR0S 2027 2130 3851#
AR1716 139# 3496
AR1S 2092 3854#
ARCB 2306# 2333 2339
ARCHK 2029 2096 2134 2177 2248 3487#
ARCHK7 2387 2417 2456 2546 3518#
ARDA0 2153 3835 3857#
ARDA1 3836 3929#
ARDA10 3843 3881#
ARDA11 3844 3884#
ARDA12 3845 3887#
ARDA13 3846 3890#
ARDA14 3847 3893#
ARDA15 3848 3905#
ARDA16 3849 3899#
ARDA17 3850 3902#
ARDA2 3837 3863#
ARDA3 3838 3953#
ARDA4 3839 3869#
ARDA5 3840 3872#
ARDA6 3841 3875#
ARDA7 3842 3954#
ARDATM 2504 4145#
ARDATS 2228 3835#
ARDM0 2437 4145 4171#
ARDM1 4146 4196#
ARDM10 4153 4163#
ARDM11 4154 4162#
ARDM12 4155 4161#
ARDM13 4156 4178#
ARDM14 4157 4177#
ARDM15 4158 4173#
ARDM16 4159 4175#
ARDM17 4160 4174#
ARDM2 4147 4169#
ARDM3 4148 4214#
ARDM4 4149 4167#
ARDM5 4150 4166#
ARDM6 4151 4165#
ARDM7 4152 4232#
ARERR 3492 3495 3500 3503#
ARHI 58# 3488 3519 3530
ARHIBT 135#
ARLO 57# 3487 3518 3529
ARLOBT 131#
ARLP 2008# 2038 2042
ATA 346# 696 722 734 783 794 812
BCERR 1236 1239#
BCFTST 1338 1349 1360 1371 3275#
BCHI 53# 1207 1217 1272 1297 1403 3278
BCHIBT 115#
BCLKEN 78# 1490 1548 1646 1783 2008 2078 2115 2160 2231 2306 2375 2406 2440
2509 2666 2672 2755 2844 2940 3045 3115
BCLO 52# 1208 1218 1273 1298 1402 3279
BCLOBT 111#
BCLP 1206# 1244 1251
BCOF1 1337# 1347 1358 1369 1380
BCOF2 1348#
BCOF3 1359#
BCOF4 1370#
BCOVF 72#
BEGEND 807# 3541
BEGIN 620# 815
BORLO 173# 3469
C 403#
CALL 773 775 777 779#
CALL0 780# 3562
CALLH 3557 3559 3561#
CATAB 769 2103 2141 2184 2255 2333 2396 2426 2463 2553 2608 2631 2656 2690
2711 2798 2876 2894 2988 3023 3069 3080 3136 3162 3191 3223 3235
CBILO 172#
CBLOOP 1483 1544 1639 1781 1948 2004 2080 2225 2299 2374 2502 2749 2838 3446#
CBPAT 2304 3996#
CC0 198# 2670
CC1 199#
CC2 200# 3119 3172
CC4 201# 1492 1550 1648 1787 1914 2117 2162
CC5 202#
CC8 203#
CHANL 179# 1714 1796 3448
CHKLOP 757# 795
CHKLP 758#
CKTRM 790#
CKTRM0 791# 3565
CKTRMH 3564#
CLKDAT 1558 1591 1657 1738 1951 2020 2089 2123 2168 2243 2314 2317 2763 2766
2769 3464#
CLKDRL 174# 3479
CLKDT 1499 2528 2531 2534 3459#
CLKIT 1717 1799 3462 3469#
CLKIT1 3456 3470#
CLKPLS 64# 1820 2383 2542 3356 3357 3358 3359 3360 3361 3362
CLRER 2975 2978 2981#
CLRFLG 185# 1681
CLRGO 339# 653
CLRSEX 1162 1613 1756 3305#
CMDF0 629 645#
CMPERR 340#
CNTCOR 852 1202 3577#
CNTDAT 850 1200 3615#
CORF 890# 892 937# 939 962# 964 978# 980 992# 994 1003# 1005 1014# 1016
1025# 1027 1071# 1073 1089# 1091 1105# 1107 1134# 1136 1151# 1153 1170# 1172
1240# 1242 1288# 1290 1313# 1315 1329# 1331 1343# 1345 1354# 1356 1365# 1367
1376# 1378 1418# 1420 1435# 1437 1450# 1452 1514# 1516 1574# 1576 1608# 1610
1668# 1670 1695# 1697 1728# 1730 1751# 1753 1812# 1814 1828# 1830 1838# 1840
1862# 1864 1878# 1880 1898# 1900 1932# 1934 1964# 1966 2034# 2036 2099# 2101
2137# 2139 2180# 2182 2251# 2253 2329# 2331 2392# 2394 2422# 2424 2459# 2461
2549# 2551 2604# 2606 2627# 2629 2652# 2654 2686# 2688 2707# 2709 2794# 2796
2872# 2874 2890# 2892 2984# 2986 3019# 3021 3065# 3067 3076# 3078 3132# 3134
3158# 3160 3187# 3189 3219# 3221 3231# 3233
CSR0 167# 1682 1685
CSR1 168# 1715 1797 3297 3310 3449
CTR1 986 1337 3569#
CTR2 997 1348 3571#
CTR3 1008 1359 3573#
CTR4 1019 1370 3575#
CUADRS 433 520 2057 2099 2103 2137 2141 2180 2184 2194 2203 2251 2255 2269
2278 2329 2333 2342 2351 2392 2396 2422 2426 2459 2463 2470 2479 2549
2553 2567 2576 2604 2608 2627 2631 2652 2656 2686 2690 2707 2711 2716
2725 2794 2798 2806 2815 2872 2876 2890 2894 2909 2918 2984 2988 2990
2999 3019 3023 3065 3069 3076 3080 3095 3104 3132 3136 3158 3162 3187
3191 3219 3223 3231 3235 3239 3369 3380
DB 372#
DBEVEN 375#
DBPAR 373#
DBPARE 374#
DEVRD 1114 1211 1276 1300 1407 1496 1554 1587 1652 1709 1734 1791 1909 1945
2015 2086 2119 2164 2237 2311 2380 2411 2446 2516 2596 2617 2640 2944
3178 3280 3320#
DEVWR 861 926 950 1059 1505 1565 1599 1677 1921 2319 2384 2413 2448 2543
2946 3012 3047 3122 3169 3206 3260 3327#
DFCPH0 152#
DFCPH1 153#
DFRMAD 54# 1122 1493 1551 1649 1788 1850 1915 2012 2084 2118 2128 2163 2174
2235 2309 2378 2409 2444 2514 2540 2671 2758 2847 2949 3050 3120 3146
3173 3209
DIAGAD 190#
DISACK 181#
DMSK 2114# 2141
DMSKLP 2159# 2184 2191
DMSTRQ 80# 864 929 953 1062 3262
DMXLPI 2231# 2255 2262
DMXLPO 2226# 2266
DMXSHF 192# 2308 2513 2757
DONE 336#
DPDAT 2226 3826#
DPPEFG 71#
DRLO 171# 3481
DSHF0 216# 2010 2083 2233
DSHF1 217#
DSHF10 224#
DSHF11 225#
DSHF12 226#
DSHF13 227#
DSHF14 228#
DSHF15 229#
DSHF16 230#
DSHF17 231#
DSHF2 218#
DSHF3 219#
DSHF4 220#
DSHF5 221#
DSHF6 222#
DSHF7 223#
DSLVRQ 79# 1214 1279 1303 1410 3282
DTD 342# 651 696 3329 3371 3402
DXHISP 77# 1123 1851 1916 2594 2615 2638 2672 2698 2950 3147 3174 3433
EBL 337# 3412
EDIT 2# 2 618
ELOOPC 759 764#
END 3241 3541#
ENSS 1494 1552 1650 1789 2013 2085 2121 2166 2236 2310 2379 2410 2445 2515
2759 2848 3051 3121 3210 3431#
ERLP 738# 890 937 962 978 992 1003 1014 1025 1071 1089 1105 1134 1151
1170 1240 1288 1313 1329 1343 1354 1365 1376 1418 1435 1450 1668 1695
1728 1751 1812 1828 1838 1862 1878 1898 1932 1964 2034 2099 2102 2137
2140 2180 2183 2251 2254 2332 2395 2425 2462 2552 2604 2607 2627 2630
2652 2655 2686 2689 2707 2710 2794 2797 2872 2875 2890 2893 2984 2987
3019 3022 3065 3068 3076 3079 3132 3135 3158 3161 3187 3190 3219 3222
3231 3234
ERLP0 739# 3547
ERLPA 749# 2103 2141 2184 2255 2333 2396 2426 2463 2553 2608 2631 2656 2690
2711 2798 2876 2894 2988 3023 3069 3080 3136 3162 3191 3223 3235
ERLPA0 750#
ERLPH 2102 2140 2183 2254 2607 2630 2655 2689 2710 2797 2875 2893 2987 3022
3068 3079 3135 3161 3190 3222 3234 3546#
ERLPM 743# 1514 1574 1608 2103 2141 2184 2255 2329 2332 2392 2395 2422 2425
2459 2462 2549 2552 2608 2631 2656 2690 2711 2798 2876 2894 2988 3023
3069 3080 3136 3162 3191 3223 3235
ERLPM0 744# 3550
ERLPMH 2332 2395 2425 2462 2552 3549#
ERRCA 747 754#
ERRCHK 709# 739 744 750
ERRCOM 741 756#
ERRSET 703# 889 936 961 977 991 1002 1013 1024 1070 1088 1104 1133 1150
1169 1239 1287 1312 1328 1342 1353 1364 1375 1417 1434 1449 1513 1573
1607 1667 1694 1727 1750 1811 1827 1837 1861 1877 1897 1931 1963 2033
3552
ERSETH 2098 2136 2179 2250 2328 2391 2421 2458 2548 2603 2626 2651 2685 2706
2793 2871 2889 2983 3018 3064 3075 3131 3157 3186 3218 3230 3552#
EVPAR 182# 3448
EXC 338#
EXTRUN 144#
F0 326#
F1 327#
F2 328#
F3 329#
F4 330#
FN 325#
GETAR 2853 2856 2860 2953 2958 2961 3528#
GO 324#
HSDPIN 65# 863 928 952 1061 1118 1213 1278 1302 1409 1498 1556 1564 1589
1654 1711 1736 1793 1947 2017 2026 2087 2120 2165 2238 2312 2381 2412
2447 2517 2597 2618 2641 2675 2701 2761 2850 2945 2947 3013 3048 3123
3207 3261 3281
I 857 872 879 884 1207 1222 1229 1234 1519 1700 2337 2464 2520 2521
2784 2787 2878 2881 3258 3278 3350 3351 3490 3493
ILF 344#
INADR 409#
INIT 412# 636 3244
INITL 2621 2665 2697 2713 3236 3244#
INT0 399#
INT1 400#
INT2 401#
INT3 402#
IOSEL 408# 621 637 639 663 665 668 682 684 688 808 830 870 882
1220 1232 1680 1687 1713 1795 2452 2455 2519 2527 2774 2781 2896 2901
2964 2970 3057 3060 3082 3087 3245 3247 3295 3301 3306 3315 3321 3328
3337 3370 3381 3400 3411 3420 3440 3447 3455 3460 3465 3478 3504 3535
3538
LDCB 142#
LDRMDA 63#
LDSB 143#
LOOPEN 180# 1714 1796 3296 3448
LPADR 890# 893 937# 940 962# 965 978# 981 992# 995 1003# 1006 1014# 1017
1025# 1028 1071# 1074 1089# 1092 1105# 1108 1134# 1137 1151# 1154 1170# 1173
1240# 1243 1288# 1291 1313# 1316 1329# 1332 1343# 1346 1354# 1357 1365# 1368
1376# 1379 1418# 1421 1435# 1438 1450# 1453 1514# 1517 1574# 1577 1608# 1611
1668# 1671 1695# 1698 1728# 1731 1751# 1754 1812# 1815 1828# 1831 1838# 1841
1862# 1865 1878# 1881 1898# 1901 1932# 1935 1964# 1967 2034# 2037 2099# 2102
2103 2137# 2140 2141 2180# 2183 2184 2251# 2254 2255 2329# 2332 2333 2392#
2395 2396 2422# 2425 2426 2459# 2462 2463 2549# 2552 2553 2604# 2607 2608
2627# 2630 2631 2652# 2655 2656 2686# 2689 2690 2707# 2710 2711 2794# 2797
2798 2872# 2875 2876 2890# 2893 2894 2984# 2987 2988 3019# 3022 3023 3065#
3068 3069 3076# 3079 3080 3132# 3135 3136 3158# 3161 3162 3187# 3190 3191
3219# 3222 3223 3231# 3234 3235
MAR 856 871 878 883 1206 1221 1228 1233 2027 2092 2130 2176 2219 2229
2241 2247 2259 2313 2323 2499 2505 2507 2523 2545 2557 2753 2783 2800
2877 2903 3089 3349
MBDLP 2755# 2798 2803
MBERR 2786 2789 2792#
MBPAR 2868 3061 3215 3534#
MCERR 886 889#
MCFTST 987 998 1009 1020 3255#
MCHI 51# 857 867 923 946 1054 3258
MCHIBT 107#
MCLO 50# 858 868 922 947 1053 3259
MCLOBT 103#
MCLP 856# 894 901
MCOF1 986# 996 1007 1018 1029
MCOF2 997#
MCOF3 1008#
MCOF4 1019#
MCOVF 73#
MDPPE1 3142# 3162
MDPPE2 3168# 3191
MDPPE3 3203# 3223 3235
MEMCOV 90# 1079
MEONFE 91# 1116 1160
MEX1 1116# 1138 1155 1174
MMSK 2406#
MMSKLP 2440# 2463 2467
MPARLP 3045# 3069 3080 3092
MPDB0 362# 2775
MPDB1 366# 2776
MPDB2 370# 2777 3536
MPDTR 354#
MPECR 350# 649 728 782 793
MPERR 345# 696 734
MPGP0 379# 666 810
MPGP1 380# 811 832
MPGP10 387# 2453 2897 2899 3083 3085 3422
MPGP11 388# 3425
MPGP12 389# 873 1223 2520 2966 3350
MPGP13 390# 872 1222 2521 2967 3351
MPGP14 391# 880 1230 3340 3506
MPGP15 392# 879 1229 3342 3508
MPGP16 393# 875 1225 2522 2968 3352
MPGP17 394# 877 1227 2525 3344 3510
MPGP2 381# 3424
MPGP3 382# 3427
MPGP4 383# 746 753 3316
MPGP5 384# 755 3513
MPGP6 385# 641 3441
MPGP7 386#
MPHVR 358#
MPSCR0 322# 622 626 3392
MPSCR1 335# 650 655 694 698 813 3323 3330 3372 3383 3401 3406 3413
MPSTAT 398#
MRHDOF 93#
MRQ1 2614# 2631
MRQ2 2637# 2656
MRQ3 2664# 2690
MRQ4 2696# 2711
MSHF0 214 233# 2538
MSHF1 234#
MSHF10 241#
MSHF11 242#
MSHF12 243#
MSHF13 244#
MSHF14 245#
MSHF15 246#
MSHF16 247#
MSHF17 248#
MSHF2 235#
MSHF3 236#
MSHF4 237#
MSHF5 238#
MSHF6 239#
MSHF7 240#
MSK0 199 205# 2127 2408
MSK1 206# 2172 2442
MSK1S 214# 2377
MSK2 207#
MSK3 208#
MSK4 209#
MSK5 210#
MSK6 211#
MSK7 212#
MSK8 213#
MSRDY1 162#
MSRDY2 163#
MSTACK 82#
MSTRDY 161#
MSTRER 2880 2883 2888#
MSTRI 2844# 2876 2894 2906
MSTRPE 149#
MSTRQ 84#
MUXDAT 2507 4090#
MUXDT1 2753 2842 3043 4084#
MUXLPI 2509# 2553 2560
MUXLPO 2504# 2564
MUXSHF 193# 2846 2948 3049 3208
NCLRAR 140#
NCLRN 150#
NENMDM 141#
NFEXFR 99#
NMEXFR 98#
NOFAIL 719 721#
NOTRUN 151#
NRNDAT 154#
NRTN 685# 740 745 751 802
NSEXFR 97#
NXTBNK 2046 2049#
OCC 343# 3371 3382 3402
OFFGO 642 648# 760 764 786
ONES 196#
OUTADR 410#
PNT 463# 890 937 962 978 992 1003 1014 1025 1071 1089 1105 1134 1151
1170 1240 1288 1313 1329 1343 1354 1365 1376 1418 1435 1450 1514 1574
1608 1668 1695 1728 1751 1812 1828 1838 1862 1878 1898 1932 1964 2034
2099 2137 2180 2251 2329 2392 2422 2459 2549 2604 2627 2652 2686 2707
2794 2872 2890 2984 3019 3065 3076 3132 3158 3187 3219 3231
PULSE2 1919 1923 2321 2385 2544 3177 3179 3361#
PULSE3 1501 1560 1593 1659 1719 1742 1801 1803 1953 2022 2090 2091 2129 2175
2244 2245 2852 2859 3360#
PULSE4 1503 1562 1597 1661 1721 1744 1854 1889 1955 2024 2415 2450 3125 3150
3359# 3528
PULSE5 3358#
PULSE6 3357#
PULSE7 2315 2318 2529 2532 2535 2764 2767 2770 2771 3054 3213 3356#
RA71R1 286#
RA71R2 287#
RA71R3 288#
RA71R4 289#
RA71R5 290#
RA72R1 293#
RA72R2 294#
RA72R3 295#
RA72R4 296#
RA72R5 297#
RAS6R1 278#
RAS6R2 279#
RAS6R3 280#
RAS6R4 281#
RAS6R5 282#
RAS6R6 283#
RAS71F 285#
RAS72F 292#
RASC6F 277#
RCBLR1 308#
RCBLR2 309#
RCBLR3 310#
RCBLR4 311#
RCDMPF 259#
RCDMR1 260#
RCDMR2 261#
RCDMR3 262#
RCDMR4 263#
RCDMR5 264#
RCOBLF 307#
RDDATA 1507 1567 1601 2322 3477#
RDLOBT 123# 127#
REG0 46# 920 932 956 970 972 1051 1097 1270 1282 1306 1321 1324 1443
1780 1805 1822 1856 1870 1872 1887 1891 1911 1925 1944 1957 3126 3142
3151 3168 3180 3203 3224 3255 3265 3275 3286
REG1 47# 860 865 925 930 949 954 1058 1063 1120 1124 1210 1215 1275
1280 1299 1304 1405 1411 1491 1549 1647 1784 1848 1852 1913 1917 2009
2079 2116 2126 2161 2171 2232 2307 2376 2407 2441 2510 2537 2593 2595
2600 2616 2622 2639 2645 2647 2667 2673 2677 2678 2679 2680 2681 2682
2699 2703 2756 2845 2941 2943 2951 3011 3046 3116 3144 3148 3171 3175
3205 3257 3263 3277 3283 3432 3434
REG15 59# 3489
REG16 60# 1663 1723 1746 3014 3070
REG17 61#
REG2 48# 1056 1080 1117 1143 1161 1406 1427 1486 1547 1642 1786 2003 2082
2224 2298 2373 2512 2669 2752 2841 2939 3041 3118
REG3 49# 1065 1082 1099 1127 1145 1164 1413 1429 1445
REM1F 299#
REM1R1 300#
REM1R2 301#
REM2F 303#
REM2R1 304#
REM2R2 305#
REPORT 714 726#
REPTU 801# 903 1030 1175 1253 1381 1455 1523 1615 1758 1969 2044 3554
REPTUH 2193 2268 2341 2469 2566 2715 2805 2908 2989 3094 3238 3554#
RESIOS 687# 761 765 787
RHDATA 314# 432 500 2057 2099 2103 2137 2141 2180 2184 2194 2203 2251 2255
2269 2278 2329 2333 2342 2351 2392 2396 2422 2426 2459 2463 2470 2479
2549 2553 2567 2576 2604 2608 2627 2631 2652 2656 2686 2690 2707 2711
2716 2725 2794 2798 2806 2815 2872 2876 2890 2894 2909 2918 2984 2988
2990 2999 3019 3023 3065 3069 3076 3080 3095 3104 3132 3136 3158 3162
3187 3191 3219 3223 3231 3235 3239 3368 3379
RHIDNF 266#
RHIDR1 267#
RHIDR2 268#
RHIDR3 269#
RHIDR4 270#
RHIDR5 271#
RHIDR6 272#
RHIDR7 273#
RHIDR8 274#
RHIDR9 275#
RINCMF 253#
RINCR1 254#
RINCR2 255#
RINCR3 256#
RINCR4 257#
RMADLO 119#
RMADR8 88# 1116 1142 1160 1485 1546 1641 1785 2002 2081 2223 2297 2372 2511
2668 2751 2840 2938 3040 3117
RMDAHI 56#
RMDALO 55#
RPTCNT 41# 676
RTRN 3300# 3311 3317 3324 3331 3345 3374 3385 3407 3414 3428 3442 3450 3474
3482 3514
RUN 323#
RUNBCK 3391 3395#
RUNLP 3390# 3394
RUNWAT 3373 3384 3388#
SAVIOS 682# 721 726 780 791
SDDPE1 1887# 1902
SDDPE2 1909# 1936
SDDPE3 1944# 1968
SDLOOP 1496# 1518 1521
SDPAT 1489 1645 2302 3978#
SEBCOV 89# 1426
SENDAD 772#
SETACT 2971 3339#
SETATA 694# 757 784
SETCNT 2591 2748 2837 3039 3194 3419#
SETCOR 3058 3338 3349# 3511
SETDAT 1655 2242 3314#
SETPNT 848 1198 1636 1999 2076 2221 2371 2501 2745 2834 2937 3036 3439#
SETRD 776#
SETRDB 778#
SETRUN 66# 1853 1888 1918 2124 2169 2320 2382 2414 2449 2541 2952 2957 2960
3124 3149 3176
SETSLV 2855 2858 3454#
SETUP 2782 2863 3336#
SETWRT 774#
SHFTIT 3266# 3539
SLAK25 175# 1683
SLRDY1 159#
SLRDY2 160#
SLVACK 81#
SLVEPE 148#
SLVRDY 158#
SLVRQ 83#
SPAR1 1709# 1732
SPAR2 1734# 1755
SPARLP 1652# 1672 1699 1702
SPRES 411# 636
SRHDOF 92#
SRR1 1587# 1612
SRVINL 184# 3470
STAINL 183# 3298
START 341# 3404
STRDBH 3560#
STRDH 3379 3558#
STRMB 2599 2620 2643 2676 2702 2762 2851 3053 3212 3399#
STWRTH 3368 3556#
STXFRR 2700 2760 3379#
STXFRW 2598 2619 2642 2674 2849 3052 3211 3368#
SWEX 1125 1595 1740 3294#
TEST0I 660# 3544
TESTI 661# 834 912 1039 1184 1262 1390 1464 1532 1624 1767 1978
TESTIH 2056 2202 2277 2350 2478 2575 2724 2814 2917 2998 3103 3543#
TOR0 169# 3299 3308
TOR1 170# 3471 3473
TST 835# 904 913# 941 966 982 1031 1040# 1075 1093 1109 1176 1185# 1254
1263# 1292 1317 1333 1382 1391# 1422 1439 1454 1456 1465# 1524 1533# 1578
1616 1625# 1759 1768# 1816 1832 1842 1866 1882 1970 1979# 2045 2057# 2103
2194 2203# 2269 2278# 2342 2351# 2396 2426 2470 2479# 2567 2576# 2608 2716
2725# 2806 2815# 2909 2918# 2988 2990 2999# 3023 3095 3104# 3136 3239
TST225 835 836#
TST226 913 914#
TST227 1040 1041#
TST228 1185 1186#
TST229 1263 1264#
TST230 1391 1392#
TST231 1465 1466#
TST232 1533 1534#
TST233 1625 1626#
TST234 1768 1769#
TST235 1979 1980#
TST236 2057 2058#
TST237 2203 2204#
TST238 2278 2279#
TST239 2351 2352#
TST240 2479 2480#
TST241 2576 2577#
TST242 2725 2726#
TST243 2815 2816#
TST244 2918 2919#
TST245 2999 3000#
TST246 3104 3105#
TSTART 643 818#
UBPEFG 70#
VERSIO 2# 2 618
WAITGO 622# 625 758 785 814
WAS71 284#
WAS72 291#
WASC6 276#
WCDMP 258#
WCLK 331#
WCOBOL 306#
WEM1 298#
WEM2 302#
WHIDN 265#
WINCM 252#
Z 404#
ZERADR 189#
ZEROS 195# 1121 1849 3145
ZRTN 762# 1835
%ADRH 523# 2057 2057# 2099 2099# 2103 2103# 2137 2137# 2141 2141# 2180 2180# 2184
2184# 2194 2194# 2203 2203# 2251 2251# 2255 2255# 2269 2269# 2278 2278# 2329
2329# 2333 2333# 2342 2342# 2351 2351# 2392 2392# 2396 2396# 2422 2422# 2426
2426# 2459 2459# 2463 2463# 2470 2470# 2479 2479# 2549 2549# 2553 2553# 2567
2567# 2576 2576# 2604 2604# 2608 2608# 2627 2627# 2631 2631# 2652 2652# 2656
2656# 2686 2686# 2690 2690# 2707 2707# 2711 2711# 2716 2716# 2725 2725# 2794
2794# 2798 2798# 2806 2806# 2815 2815# 2872 2872# 2876 2876# 2890 2890# 2894
2894# 2909 2909# 2918 2918# 2984 2984# 2988 2988# 2990 2990# 2999 2999# 3019
3019# 3023 3023# 3065 3065# 3069 3069# 3076 3076# 3080 3080# 3095 3095# 3104
3104# 3132 3132# 3136 3136# 3158 3158# 3162 3162# 3187 3187# 3191 3191# 3219
3219# 3223 3223# 3231 3231# 3235 3235# 3239 3239# 3369 3369# 3380 3380# 3543
3546 3549 3552 3554 3556 3567
%EMES 835# 892 895 895# 913# 939 942 942# 964 967 967# 980 983 983#
994 997 997# 1005 1008 1008# 1016 1019 1019# 1027 1030 1030# 1040# 1073
1076 1076# 1091 1094 1094# 1107 1110 1110# 1136 1139 1139# 1153 1156 1156#
1172 1175 1175# 1185# 1242 1245 1245# 1263# 1290 1293 1293# 1315 1318 1318#
1331 1334 1334# 1345 1348 1348# 1356 1359 1359# 1367 1370 1370# 1378 1381
1381# 1391# 1420 1423 1423# 1437 1440 1440# 1452 1455 1455# 1465# 1516 1519
1519# 1533# 1576 1579 1579# 1610 1613 1613# 1625# 1670 1673 1673# 1697 1700
1700# 1730 1733 1733# 1753 1756 1756# 1768# 1814 1817 1817# 1830 1833 1833#
1840 1843 1843# 1864 1867 1867# 1880 1883 1883# 1900 1903 1903# 1934 1937
1937# 1966 1969 1969# 1979# 2036 2039 2039# 2057# 2101 2104 2104# 2139 2142
2142# 2182 2185 2185# 2203# 2253 2256 2256# 2278# 2331 2334 2334# 2351# 2394
2397 2397# 2424 2427 2427# 2461 2464 2464# 2479# 2551 2554 2554# 2576# 2606
2609 2609# 2629 2632 2632# 2654 2657 2657# 2688 2691 2691# 2709 2712 2712#
2725# 2796 2799 2799# 2815# 2874 2877 2877# 2892 2895 2895# 2918# 2986 2989
2989# 2999# 3021 3024 3024# 3067 3070 3070# 3078 3081 3081# 3104# 3134 3137
3137# 3160 3163 3163# 3189 3192 3192# 3221 3224 3224# 3233 3236 3236#
%REQ 431# 432# 771
%TNUM 429# 829 833 835# 911 913# 1038 1040# 1183 1185# 1261 1263# 1389 1391#
1463 1465# 1531 1533# 1623 1625# 1766 1768# 1977 1979# 2055 2057# 2201 2203#
2276 2278# 2349 2351# 2477 2479# 2574 2576# 2723 2725# 2813 2815# 2916 2918#
2997 2999# 3102 3104#
.ERROR 710 711
ADB 2011 2173 2229 2234 2443 2505 2539
ADBR 2187 2257 2556 2800 2903 3089
CHKERR 514#
CHKRH 505#
CHKTRM 513#
DATI 622 626 650 663 682 694 867 868 932 956 972 1065 1082 1099
1127 1145 1164 1217 1218 1282 1306 1324 1413 1429 1445 1663 1685 1723
1746 1805 1822 1856 1872 1891 1925 1957 2600 2622 2647 2677 2678 2679
2680 2681 2682 2703 2775 2776 2777 2897 3014 3070 3083 3126 3151 3180
3224 3265 3286 3392 3401 3481 3487 3488 3489 3518 3519 3529 3530 3536
DECR 801 899 1249 1519 1700 2337
DEFTST 436# 823
ERLOOP 483# 891 938 963 979 993 1004 1015 1026 1072 1090 1106 1135 1152
1171 1241 1289 1314 1330 1344 1355 1366 1377 1419 1436 1451 1515 1575
1609 1669 1696 1729 1752 1813 1829 1839 1863 1879 1899 1933 1965 2035
2100 2138 2181 2252 2330 2393 2423 2460 2550 2605 2628 2653 2687 2708
2795 2873 2891 2985 3020 3066 3077 3133 3159 3188 3220 3232
ERRLOP 516#
ERRMAC 466# 889 936 961 977 991 1002 1013 1024 1070 1088 1104 1133 1150
1169 1239 1287 1312 1328 1342 1353 1364 1375 1417 1434 1449 1513 1573
1607 1667 1694 1727 1750 1811 1827 1837 1861 1877 1897 1931 1963 2033
2098 2136 2179 2250 2328 2391 2421 2458 2548 2603 2626 2651 2685 2706
2793 2871 2889 2983 3018 3064 3075 3131 3157 3186 3218 3230
ERROR 475# 889 935 959 976 990 1001 1012 1023 1069 1087 1103 1132 1149
1168 1239 1286 1310 1327 1341 1352 1363 1374 1416 1433 1448 1666 1692
1725 1749 1809 1825 1837 1859 1876 1895 1929 1961 2032 2098 2136 2179
2250 2602 2625 2650 2684 2705 2792 2870 2888 2981 3017 3063 3074 3129
3155 3184 3217 3228
ERRORA 479#
ERRORD 481#
ERRORM 477# 1511 1571 1605 2326 2389 2419 2458 2548
GOINK 525# 834 889 893 903 912 936 940 961 965 977 981 991 995
1002 1006 1013 1017 1024 1028 1030 1039 1070 1074 1088 1092 1104 1108
1133 1137 1150 1154 1169 1173 1175 1184 1239 1243 1253 1262 1287 1291
1312 1316 1328 1332 1342 1346 1353 1357 1364 1368 1375 1379 1381 1390
1417 1421 1434 1438 1449 1453 1455 1464 1513 1517 1523 1532 1573 1577
1607 1611 1615 1624 1667 1671 1694 1698 1727 1731 1750 1754 1758 1767
1811 1815 1827 1831 1837 1841 1861 1865 1877 1881 1897 1901 1931 1935
1963 1967 1969 1978 2033 2037 2044 2056 2098 2102 2136 2140 2179 2183
2193 2202 2250 2254 2268 2277 2328 2332 2341 2350 2391 2395 2421 2425
2458 2462 2469 2478 2548 2552 2566 2575 2603 2607 2626 2630 2651 2655
2685 2689 2706 2710 2715 2724 2793 2797 2805 2814 2871 2875 2889 2893
2908 2917 2983 2987 2989 2998 3018 3022 3064 3068 3075 3079 3094 3103
3131 3135 3157 3161 3186 3190 3218 3222 3230 3234 3238 3368 3379
GOSUB 848 861 926 950 987 998 1009 1020 1059 1114 1125 1162 1198 1211
1276 1300 1338 1349 1360 1371 1407 1483 1494 1496 1499 1501 1503 1505
1507 1544 1552 1554 1558 1560 1562 1565 1567 1587 1591 1593 1595 1597
1599 1601 1613 1636 1639 1650 1652 1655 1657 1659 1661 1677 1709 1717
1719 1721 1734 1738 1740 1742 1744 1756 1781 1789 1791 1799 1801 1803
1854 1889 1909 1919 1921 1923 1945 1948 1951 1953 1955 1999 2004 2013
2015 2020 2022 2024 2029
IMAR 2316 2530 2533 2765 2768
INC 2898 3084
INCR 895 896 897 898 1245 1246 1247 1248 2039 2188 2258 2263 2334 2335
2336 2464 2554 2561 3390
JMP 625 633 643 675 741 747 773 775 777 795 815 886 901 975
1086 1131 1236 1251 1432 1521 1665 1691 1702 1748 1808 1875 1894 1928
1960 2042 2047 2191 2262 2266 2339 2467 2560 2564 2624 2649 2786 2789
2803 2880 2883 2906 2975 2978 3073 3092 3154 3183 3227 3241 3311 3317
3324 3331 3345 3374 3385 3394 3407 3414 3428 3442 3450 3456 3462 3474
3482 3492 3495 3500 3514 3539 3542 3545 3548 3551 3553 3555 3557 3559
3563 3566
JMPB0 624 629 631 759 1068 1085 1102 1130 1148 1167 1415 1431 1447 1664
1724 1747 1807 1824 1858 1874 1893 1927 1959 3016 3072 3128 3153 3182
3226 3393
JMPB4 673 934 958 974 1690 2041 2190 2265 2466 2563 3267
JMPB7 710 714 2601 2623 2648 2683 2704
JMPC 3391
JMPI 1835
JMPSUB 642 721 726 739 744 750 757 758 760 761 764 765 780 784
785 786 787 791 814 834 849 862 889 893 903 912 927 936
940 951 961 965 977 981 988 991 995 999 1002 1006 1010 1013
1017 1021 1024 1028 1030 1039 1060 1070 1074 1088 1092 1104 1108 1115
1126 1133 1137 1150 1154 1163 1169 1173 1175 1184 1199 1212 1239 1243
1253 1262 1277 1287 1291 1301 1312 1316 1328 1332 1339 1342 1346 1350
1353 1357 1361 1364 1368 1372 1375 1379 1381 1390 1408 1417 1421 1434
1438 1449 1453 1455 1464 1484 1495 1497 1500 1502 1504 1506 1508 1513
1517 1523 1532 1545 1553 1555 1559 1561 1563 1566 1568 1573 1577 1588
1592 1594 1596 1598 1600 1602 1607 1611 1614 1615 1624 1637 1640 1651
1653 1656 1658 1660 1662 1667 1671 1678 1694 1698 1710 1718 1720 1722
1727 1731 1735 1739 1741 1743 1745 1750 1754 1757 1758 1767 1782 1790
1792 1800 1802 1804 1811 1815 1827 1831 1837 1841 1855 1861 1865 1877
1881 1890 1897 1901 1910 1920 1922 1924 1931 1935 1946 1949 1952 1954
1956 1963 1967 1969 1978 2000 2005 2014 2016 2021 2023 2025 2030 2033
2037 2044 2056 2076 2080 2085 2086 2089 2090 2091 2096 2098 2102 2119
2121 2123 2129 2134 2136 2140 2164 2166 2168 2175 2177 2179 2183 2193
2202 2221 2225 2236 2237 2242 2243 2244 2245 2248 2250 2254 2268 2277
2299 2310 2311 2314 2315 2317 2318 2319 2321 2322 2328 2332 2341 2350
2371 2374 2379 2380 2384 2385 2387 2391 2395 2410 2411 2413 2415 2417
2421 2425 2445 2446 2448 2450 2456 2458 2462 2469 2478 2501 2502 2515
2516 2528 2529 2531 2532 2534 2535 2543 2544 2546 2548 2552 2566 2575
2588 2591 2596 2598 2599 2603 2607 2614 2617 2619 2620 2621 2626 2630
2637 2640 2642 2643 2651 2655 2664 2665 2674 2676 2685 2689 2696 2697
2700 2702 2706 2710 2712 2713 2715 2724 2745 2748 2749 2759 2760 2762
2763 2764 2766 2767 2769 2770 2771 2772 2782 2793 2797 2805 2814 2834
2837 2838 2848 2849 2851 2852 2853 2855 2856 2858 2859 2860 2862 2863
2868 2871 2875 2889 2893 2908 2917 2937 2944 2946 2953 2958 2961 2971
2983 2987 2989 2998 3012 3018 3022 3036 3039 3047 3051 3052 3053 3054
3055 3058 3061 3064 3068 3075 3079 3094 3103 3121 3122 3125 3131 3135
3150 3157 3161 3169 3177 3178 3179 3186 3190 3194 3206 3210 3211 3212
3213 3214 3215 3218 3222 3230 3234 3236 3238 3260 3280 3338 3368 3373
3379 3384 3511 3528
JMPZ 719 740 745 751 802 885 888 894 900 904 941 966 982 989
996 1000 1007 1011 1018 1022 1029 1031 1075 1093 1109 1138 1155 1174
1176 1235 1238 1244 1250 1254 1285 1292 1309 1317 1326 1333 1340 1347
1351 1358 1362 1369 1373 1380 1382 1422 1439 1454 1456 1510 1518 1520
1524 1570 1578 1604 1612 1616 1672 1699 1701 1732 1755 1759 1816 1832
1836 1842 1866 1882 1902 1936 1968 1970 2031 2038 2045 2097 2103 2135
2141 2178 2184 2194 2249 2255 2261 2269 2325 2333 2338 2342 2388 2396
2418 2426 2457 2463 2470 2547 2553 2559 2567 2608 2631 2656 2690 2711
2716 2785 2788 2791 2798 2802 2806 2869 2876 2879 2882 2887 2894 2905
2909 2974 2977 2980 2988 2990 3023 3062 3069 3080 3091 3095 3136 3162
3191 3216 3223 3235 3239 3288 3491 3494 3499 3522
JUMP 2046 3541 3544 3547 3550 3552 3554 3562 3565
LANDB 697 717 732
LANDBR 652 670 716 730 2779 2885 2956 3403 3497
LDBR 620 632 634 636 638 640 648 651 653 669 674 676 683 696
703 715 722 729 731 734 772 774 776 778 783 794 807 809
812 829 831 833 848 850 852 854 859 861 864 869 881 892
911 921 924 926 929 939 945 948 950 953 964 980 987 994
998 1005 1009 1016 1020 1027 1038 1052 1055 1057 1059 1062 1073 1079
1091 1107 1114 1116 1119 1121 1123 1125 1136 1142 1153 1160 1162 1172
1183 1198 1200 1202 1204 1209 1211 1214 1219 1231 1242 1261 1271 1274
1276 1279 1283 1290 1296 1300 1303 1307 1315 1322 1331 1338 1345 1349
1356 1360 1367 1371 1378 1389 1401 1404 1407 1410 1420 1426 1437 1452
1463 1483 1485 1487 1490 1492 1494 1496 1499 1501 1503 1505 1507 1516
1531 1544 1546 1548 1550 1552 1554 1558 1560 1562 1565 1567 1576 1587
1591 1593 1595 1597 1599 1601 1610 1613 1623 1636 1639 1641 1643 1646
1648 1650 1652 1655 1657 1659 1661 1670 1677 1679 1681 1686 1697 1709
1712 1714 1716 1717 1719 1721 1730 1734 1738 1740 1742 1744 1753 1756
1766 1781 1783 1785 1787 1789 1791 1794 1796 1798 1799 1801 1803 1814
1830 1840 1847 1849 1851 1854 1864 1880 1889 1900 1909 1912 1914 1916
1919 1921 1923 1934 1945 1948 1951 1953 1955 1966 1977 1999 2002 2004
2006 2008 2010 2013 2015 2020 2022 2024 2027 2029 2036 2046 2055 2078
2081 2083 2092 2094 2101 2115 2117 2125 2127 2130 2132 2139 2153 2155
2157 2160 2162 2170 2172 2182 2186 2201 2218 2223 2226 2228 2231 2233
2253 2256 2276 2297 2300 2302 2304 2306 2308 2331 2349 2372 2375 2377
2394 2406 2408 2424 2438 2440 2442 2451 2454 2461 2477 2498 2504 2507
2509 2511 2513 2518 2526 2536 2538 2551 2555 2574 2589 2592 2594 2606
2615 2629 2638 2644 2654 2666 2668 2670 2672 2688 2698 2709 2723 2746
2751 2753 2755 2757 2773 2778 2780 2796 2799 2813 2835 2840 2842 2844
2846 2874 2884 2892 2895 2900 2902 2916 2938 2940 2942 2948 2950 2955
2963 2965 2969 2986 2997 3010 3021 3037 3040 3043 3045 3049 3056 3059
3067 3078 3081 3086 3088 3102 3115 3117 3119 3134 3143 3145 3147 3160
3170 3172 3174 3189 3192 3204 3208 3221 3233 3244 3246 3256 3262 3276
3282 3284 3294 3296 3298 3300 3305 3307 3309 3314 3320 3322 3327 3329
3336 3369 3371 3380 3382 3388 3399 3402 3404 3410 3412 3419 3423 3426
3431 3433 3439 3446 3448 3454 3459 3464 3466 3470 3472 3477 3496 3503
3534 3537 3541 3544 3547 3550 3552 3554 3556 3558 3560 3562 3565
LDMAR 661 846 986 997 1008 1019 1196 1337 1348 1359 1370 1489 1645 1733
1997 2018 2074 2114 2159 2239 2246 2369 2437 2743 2832 2935 3034 3248
LDMARX 662 1482 1638 2001 2077 2222 2296 2436 2503 2750 2839 3042
LDMEM 664 847 1197 1557 1590 1635 1737 1950 1998 2019 2075 2088 2122 2167
2220 2370 2386 2416 2500 2744 2833 2936 2972 3035 3249
LORB 654 1284 1308 3405
LORBR 695 704 733
LORCB 1325 3287
LORCM 3468
MOV 660 667 671 687 709 727 752 754 756 781 792 856 871 874
876 878 883 1206 1221 1224 1226 1228 1233 1688 2040 2176 2240 2241
2259 2264 2313 2323 2523 2524 2545 2557 2562 2783 2864 2866 2877 3339
3341 3343 3349 3421 3505 3507 3509 3512
MOVB 621 635 637 639 641 649 655 666 668 677 684 688 698 723
728 735 738 743 749 753 755 779 782 790 793 808 810 811
813 830 832 851 853 855 860 863 865 870 875 877 882 920
922 923 925 928 930 946 947 949 952 954 970 1051 1053 1054
1056 1058 1061 1063 1080 1097 1117 1118 1120 1122 1124 1143 1161 1201
1203 1205 1210 1213 1215 1220 1225 1227 1232 1270 1272 1273 1275 1278
1280 1297 1298 1299 1302 1304 1321 1323 1402 1403 1405 1406 1409 1411
1427 1443 1486 1488 1491 1493 1498 1547 1549 1551 1556 1564 1589 1642
1644 1647 1649 1654 1680 1682 1683 1687 1711 1713 1715 1736 1780 1784
1786 1788 1793 1795 1797 1820 1848 1850 1852 1853 1870 1887 1888 1911
1913 1915 1917 1918 1944 1947 2003 2007 2009 2012 2017 2026 2028 2079
2082 2084 2087 2093 2095 2116 2118 2120 2124 2126 2128 2131 2133 2154
2156 2158 2161 2163 2165 2169 2171 2174 2219 2224 2227 2232 2235 2238
2298 2301 2303 2305 2307 2309 2312 2320 2373 2376 2378 2381 2382 2383
2407 2409 2412 2414 2439 2441 2444 2447 2449 2452 2455 2499 2508 2510
2512 2514 2517 2519 2525 2527 2537 2540 2541 2542 2590 2593 2595 2597
2616 2618 2639 2641 2645 2667 2669 2671 2673 2675 2699 2701 2747 2752
2754 2756 2758 2761 2774 2781 2836 2841 2843 2845 2847 2850 2854 2857
2861 2865 2867 2896 2899 2901 2939 2941 2943 2945 2947 2949 2951 2952
2954 2957 2959 2960 2962 2964 2966 2967 2968 2970 3011 3013 3038 3041
3044 3046 3048 3050 3057 3060 3082 3085 3087 3116 3118 3120 3123 3124
3142 3144 3146 3148 3149 3168 3171 3173 3175 3176 3193 3203 3205 3207
3209 3245 3247 3255 3257 3261 3263 3275 3277 3281 3283 3285 3295 3297
3299 3301 3306 3308 3310 3315 3321 3323 3328 3330 3337 3340 3342 3344
3356 3357 3358 3359 3360 3361 3362 3370 3372 3381 3383 3389 3400 3406
3411 3413 3420 3422 3424 3425 3427 3432 3434 3440 3447 3449 3455 3460
3465 3467 3469 3471 3473 3478 3479 3504 3506 3508 3510 3513 3520 3535
3538 3543 3546 3549 3561 3564
MOVMEM 665 746 857 858 872 873 879 880 1207 1208 1222 1223 1229 1230
2230 2247 2260 2453 2506 2520 2521 2522 2558 2801 2904 3090 3258 3259
3278 3279 3316 3350 3351 3352 3441 3461
NAME 2# 2
NOP 866 931 955 971 1064 1081 1098 1144 1216 1281 1305 1412 1428 1444
1684 1821 1871 2646 3264 3480
OSB 718
OSM 884 887 1234 1237 1509 1569 1603 2324 2784 2787 2790 2878 2881 2886
2973 2976 2979 3490 3493 3498 3521
READ 502# 3379
READB 503#
REPEAT 496# 903 1030 1175 1253 1381 1455 1523 1615 1758 1969 2044 2193 2268
2341 2469 2566 2715 2805 2908 2989 3094 3238
RETURN 646 656 678 685 689 699 705 712 720 724 736 762 766 788
803 3250 3268 3269 3289 3290 3302 3353 3363 3395 3435 3501 3523 3524
3531
SHL 713 933 957 973 2189 2465 3266
SHLR 2185
SHR 623 627 628 630 645 672 1066 1067 1083 1084 1100 1101 1128 1129
1146 1147 1165 1166 1414 1430 1446 1689 1806 1823 1857 1873 1892 1926
1958 3015 3071 3127 3152 3181 3225
TEST 823# 824 906 1033 1178 1256 1384 1458 1526 1618 1761 1972 2050 2196
2271 2344 2472 2569 2718 2808 2911 2992 3097
WRITE 501# 3368
.ECRAM 585# 3541
.END 4250
.INIT 615
.LOC 2048
.MEM 3567