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;MF20.FMT.61
*** MF20 MEMORY CONTROLLER SBUS DIAGNOSTIC FUNCTIONS ***
FUNCTION 00 00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E) 1* < CONTROLLER NUMBER > !CLEAR* *
TO MEM 2* 0 ! 1 ! ? * ? ! ? ! 0-5 * ! ! * ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E) 3* ! < FUNCTION NUMBER > *
TO MEM 4* ! ! * ! ! * ! ! * ! ! * ! 0 ! 0 * 0 ! 0 ! 0 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E+1) 5*CONTR!CORR !INCMP* <PARITY ERRORS> *INTERLEAVE ! <LAST WORD REQUESTS > *<LAST TYPE>! < ERROR ADDRESS *
FROM MEM 6* ERR ! ERR !CYCLE*READ !WRITE! ADR * 1 ! 1 ! RQ0 * RQ1 ! RQ2 ! RQ3 * RD ! WR ! 14 * 15 ! 16 ! 17 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E+1) 7* ERROR ADDRESS (CONTINUED) > *
FROM MEM 8* 18 ! 19 ! 20 * 21 ! 22 ! 23 * 24 ! 25 ! 26 * 27 ! 28 ! 29 * 30 ! 31 ! 32 * 33 ! 34 ! 35 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
FUNCTION 01 00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E) 1* < CONTROLLER NUMBER > ! *<GROUP LOOPBACK >* *
TO MEM 2* 0 ! 1 ! ? * ? ! ? ! * ! ! * ! ! *ENABL! GN2 ! GN1 * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E) 3* ! < STATUS > !LD EN! ! < FUNCTION NUMBER > *
TO MEM 4* ! ! * ! ! * !DSABL! SF2 * SF1 !25-27! * ! 0 ! 0 * 0 ! 0 ! 1 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E+1) 5* ! <MEM CONTROLLER TYPE> * <LPBK GRP SEL> * *
FROM MEM 6* ! ! * ! ! * ! ! 0 * 1 ! 0 ! 1 * 0 ! 1 ! 2 * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E+1) 7* ! < STATUS > ! *
FROM MEM 8* ! ! * ! ! * !DSABL! SF2 * SF1 ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
SF2 & SF1 ARE SOFTWARE FLAGS DO NOT EFFECT THE HARDWARE, NOR DOES THE HARDWARE AFFECT THEM EXCEPT TO CLEAR THEM ON POWER-UP. THEIR
COMBINED MEANINGS ARE: 0/CONTROLLER WAS JUST POWERED UP; 1/ALL RAMS BUT ADRESP ARE LOADED, CRUDE PATCHING IS DONE AND BITSUB RAM
SAYS WHICH BLOCKS MAY BE USED; 2/SAME AS 1 BUT CONTROLLER IS CONFIGURED; 3/SAME AS 2 EXCEPT THAT TGHA HAS FINISHED ITS WORK.
FUNCTION 02 00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E) 1* < CONTROLLER NUMBER > ! * < SM PROM SELECT > !<PROM BYTE>* *
TO MEM 2* 0 ! 1 ! ? * ? ! ? ! * ! ! * GN2 ! GN1 ! FN2 * FN1 ! 2 ! 1 * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E) 3* ! < DIAG MIXER INPUT SELECT > ! ! < FUNCTION NUMBER > *
TO MEM 4* ! ! * ! ! 2 * 3 ! 4 ! 5 * 6 ! ! * ! 0 ! 0 * 0 ! 1 ! 0 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E+1) 5* !<ERROR WD#>! < SELECTED DIAG DATA OR PROM DATA > * *
FROM MEM 6* ! ! * ! ! 2 * 1 ! 0 ! 1 * 2 ! 3 ! 4 * 5 ! 6 ! 7 * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E+1) 7* ! < MOS ADDRESS (SINGLE STEP ONLY) > !<CTL RAM PAR ERR>! *
FROM MEM 8* ! ! 0 * 1 ! 2 ! 3 * 4 ! 5 ! 6 * 7 ! TIM ! SUB * ADR ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
NOTE: BITS 23-27 ARE ONLY USED DURING SINGLE STEP DIAGNOSTIC TESTS. THE LEFTMOST 1 BIT SELECTS THE CORRESPONDING MIXER INPUT
FOR READING DIAGNOSTIC SIGNALS. IF 23-27 ARE 0 THEN THE DATA RETURNED IS THE SELECTED SM PROM WORD. NOTE ALSO THAT
BITS 26-27 ARE USED TO SELECT THE ADDRESS WHICH IS SENT BACK IN THE MOS ADDRESS FIELD.
*** MF20 MEMORY CONTROLLER SBUS DIAGNOSTIC FUNCTIONS ***
FUNCTION 03 00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E) 1* < CONTROLLER NUMBER > ! !FAST * !<FIXED VAL LOGIC RAMS >!LD EN*LD EN! *
TO MEM 2* 0 ! 1 ! ? * ? ! ? ! * ! ! BUS * !ACKN !D VLD*RDA34!RDA35! 10 *11-13! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E) 3* ! < FIXED VALUE LOGIC RAM LOAD ADDRESS > ! ! < FUNCTION NUMBER > *
TO MEM 4* ! ! 0 * 1 ! 2 ! 3 * 4 ! 5 ! 6 * 7 ! ! * ! 0 ! 0 * 0 ! 1 ! 1 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E+1) 5* !FAST * !<FIXED VAL LOGIC RAMS >! *
FROM MEM 6* ! ! * ! ! * ! ! BUS * !ACKN !D VLD*RDA34!RDA35! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E+1) 7* *
FROM MEM 8* ! ! * ! ! * ! ! * ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
NOTES: THE ACKN RAM (BIT 10) USES ADR BITS 1-7 ONLY.
THE FAST-BUS BIT IS DISCONNECTED INTERNALLY AND IS LEFT IN ONLY FOR DIAGNOSTIC COMPATABILITY.
FUNCTION 04 00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E) 1* < CONTROLLER NUMBER > !PORT * * < SINGLE STEP CLOCK CONTROL *
TO MEM 2* 0 ! 1 ! ? * ? ! ? !LPBK * ! ! *A COM!B COM!D VLD* ! !SSCLK*SSMOD! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E) 3* SS CLK CTL > *REFR !LD EN! * < REFRESH INTERVAL (GATED CLOCK/16) > ! < FUNCTION NUMBER > *
TO MEM 4* ! !RNOW *ALLOW!24-30! * 1 ! 2 ! 3 * 4 ! 5 ! 6 * 7 ! 0 ! 0 * 1 ! 0 ! 0 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E+1) 5* * < SS CLOCK CONTROL ECHO > ! *
FROM MEM 6* ! ! * ! ! * ! ! *A COM!B COM! * ! ! *SSMOD! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E+1) 7* *REFR ! ! < REFRESH INTERVAL COUNTER > ! *
FROM MEM 8* ! ! *ALLOW! ! 0 * 1 ! 2 ! 3 * 4 ! 5 ! 6 * 7 ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
NOTE: IF PORT LOOPBACK IS SET (BIT 5) THE CONTROLLER WILL JUST ECHO ANYTHING SENT OUT BY AN SBUS DIAG AS LONG AS THE PROPER
CONTROLLER NUMBER IS GIVEN. ONLY AN SBUS RESET CAN CLEAR THIS CONDITION.
FUNCTION 05 00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E) 1* < CONTROLLER NUMBER > ! * < SINGLE STEP SIMULATED REQUEST BITS > ! *LD EN! *
TO MEM 2* 0 ! 1 ! ? * ? ! ? ! *ST A !ST B ! RQ0 * RQ1 ! RQ2 ! RQ3 * RD ! WR ! * SS ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E) 3* ! < SINGLE STEP REQUEST SIMULATED ADDRESS BITS > ! < FUNCTION NUMBER > *
TO MEM 4* ! ! 14 * 15 ! 16 ! 17 * 18 ! 19 ! 20 * 21 ! ! 34 * 35 ! 0 ! 0 * 1 ! 0 ! 1 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E+1) 5* *
FROM MEM 6* ! ! * ! ! * ! ! * ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E+1) 7* * < SS MOS RAS > ! *
FROM MEM 8* ! ! * ! ! * 0 ! 1 ! 2 * 3 ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
*** MF20 MEMORY CONTROLLER SBUS DIAGNOSTIC FUNCTIONS ***
FUNCTION 06 00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E) 1* < CONTROLLER NUMBER > ! ! < DIAGNOSTIC DATA TO SY OR WP BOARD > *LD EN! *
TO MEM 2* 0 ! 1 ! ? * ? ! ? ! * ! 32 ! 16 * 8 ! 4 ! 2 * 1 !MISC !MISC *07-14! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E) 3* !<ECC DIAG SUBFCN>! ! < FUNCTION NUMBER > *
TO MEM 4* ! ! * ! ! * ! 4 ! 2 * 1 ! ! * ! 0 ! 0 * 1 ! 1 ! 0 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E+1) 5* ! < DIAGNOSTIC DATA FROM SY OR WP BOARD > * *
FROM MEM 6* ! ! * ! ! * ! 32 ! 16 * 8 ! 4 ! 2 * 1 !MISC !MISC * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E+1) 7* * < SS MOS CAS > ! *
FROM MEM 8* ! ! * ! ! * 0 ! 1 ! 2 * 3 ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
NOTE: SBDIAG FCN 6 DOES DIFFERENT THINGS DEPENDING ON THE SUBFUNCTION CODE IN BITS 25-27:
6.0 READ THE ECC REGISTER ON THE SYN BOARD.
6.1 READ THE SYNDROME BUFFER ON THE SYN BOARD. THIS FUNCTION IS ALSO NORMALLY USED BY MONITOR.
6.2 SEL DIAG BITS 07-13 IN PLACE OF MOS BITS 36-42, FORCE ZEROS ON 00-35, RUN THRU A CORRECTION PASS, AND RETURN 00-35.
*** PLEASE NOTE THAT FCN 6.2 RETURNS THE ENTIRE WORD, NOT JUST BITS 7-14. ***
6.3 UNUSED
6.4 WR ECC COMPLEMENT REG IF BIT 15 SET, THEN READ IT BACK.
6.5 WR ECC COMPLEMENT REG IF BIT 15 SET, THEN ENABLE IT TO BE SENT TO MEM IN PLACE OF D36-42 ON NEXT WR TO MEM.
6.6 READ D36-43 MIXER.
6.7 ENABLE LATCHING OF D36-43 MIXER AFTER NEXT WRITE.
7 8 9 10 11 12 13 14 7 8 9 10 11 12 13 14
+-----+-----*-----+-----+-----*-----+-----+-----* +-----+-----*-----+-----+-----*-----+-----+-----*
SUBFUNCTION ! < MEM BITS 36-43 LATCHED ON LAST RD ERROR > * SUBFUNCTION ! < ECC BITS TO BE COMPLEMENTED ON WR > ! PAR *
6.0 !ECC32!ECC16*ECC8 !ECC4 !ECC2 *ECC1 !E PAR!SPARE* 6.4 ! 32 ! 16 * 8 ! 4 ! 2 * 1 !E PAR! CTL *
+-----+-----*-----+-----+-----*-----+-----+-----* +-----+-----*-----+-----+-----*-----+-----+-----*
+-----+-----*-----+-----+-----*-----+-----+-----* +-----+-----*-----+-----+-----*-----+-----+-----*
SUBFUNCTION ! <SYNDROME LATCHED ON LAST RD ERR> !<ERR TYPE >* SUBFUNCTION ! <BITS 36-43 AS WRITTEN TO MEM AFTER FCN 6.7 > *
6.1 ! 32 ! 16 * 8 ! 4 ! 2 * 1 ! CORR! DBL * 6.6 !ECC32!ECC16*ECC8 !ECC4 !ECC2 *ECC1 !E PAR!SPARE*
+-----+-----*-----+-----+-----*-----+-----+-----* +-----+-----*-----+-----+-----*-----+-----+-----*
FUNCTION 07 00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E) 1* < CONTROLLER NUMBER > ! ! < BIT SUBSTITUTION RAM DATA (BIT NUMBERS) > *LD EN! *
TO MEM 2* 0 ! 1 ! ? * ? ! ? ! * ! 32 ! 16 * 8 ! 4 ! 2 * 1 ! ICE ! PAR *07-14! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E) 3* * < BIT SUBSTITUTION RAM LOAD ADDRESS > ! ! < FUNCTION NUMBER > *
TO MEM 4* ! ! * GN2 ! GN1 ! BN2 * BN1 ! 33 ! 34 * 35 ! ! * ! 0 ! 0 * 1 ! 1 ! 1 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E+1) 5* ! < BIT SUBSTITUTION RAM DATA ECHO > * *
FROM MEM 6* ! ! * ! ! * ! 32 ! 16 * 8 ! 4 ! 2 * 1 ! ICE ! PAR * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E+1) 7* * < SS MOS WR EN > ! *
FROM MEM 8* ! ! * ! ! * 0 ! 1 ! 2 * 3 ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
"ICE" MEANS IGNORE CORRECTABLE ERROR (IE DON'T SET CORR ERR FLAG)
*** MF20 MEMORY CONTROLLER SBUS DIAGNOSTIC FUNCTIONS ***
FUNCTION 10 00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E) 1* < CONTROLLER NUMBER > ! ! < VOLTAGE MARGINS > ! < V MARGIN ENABLES > *LD EN! *
TO MEM 2* 0 ! 1 ! ? * ? ! ? ! * !12.60!5.25 *-2.10!-5.46! 12 * 5 ! -2 !-5.2 *07-14! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E) 3* !CORR * CLR ! ! < FUNCTION NUMBER > *
TO MEM 4* ! ! * ! ! * ! ! DIS *DCBAD! ! * ! 0 ! 1 * 0 ! 0 ! 0 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E+1) 5* ! < VOLTAGE MARGINS > ! < V MARGINS ENABLED > * *
FROM MEM 6* ! ! * ! ! * !12.60!5.25 *-2.10!-5.46! 12 * 5 ! -2 !-5.2 * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E+1) 7* !CORR * DC ! *
FROM MEM 8* ! ! * ! ! * ! ! DIS * BAD ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
NOTE: THE VOLTAGES GIVEN ABOVE APPLY FOR ONES IN BITS 7-10 WHERE ENABLED BY BITS 11-14. THE VOLTAGES CORRESPONDING TO ZEROS
IN BITS 7-10 ARE 11.40, 4.75, -1.90, AND -4.94. MORE THAN ONE MARGIN MAY BE SET CONCURRENTLY.
FUNCTION 11 00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E) 1* < CONTROLLER NUMBER > ! ! < TIMING RAM LOAD ADR... *
TO MEM 2* 0 ! 1 ! ? * ? ! ? ! * ! ! * ! ! * ! 0 ! 1 * 2 ! 3 ! 4 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E) 3* ...ADR > !LD EN* < TIMING RAM DATA > ! ! < FUNCTION NUMBER > *
TO MEM 4* 5 ! 6 !21-30* RAS ! CAS ! PAR *WR EN!2ND A!D RDY*B CLR! ! * ! 0 ! 1 * 0 ! 0 ! 1 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E+1) 5* *
FROM MEM 6* ! ! * ! ! * ! ! * ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E+1) 7* * < TIMING RAM DATA ECHO > ! ! 4K *-DSEL! *
FROM MEM 8* ! ! * RAS ! CAS ! PAR *WR EN!2ND A!D RDY*B CLR! ! EN *CYCEN! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
FUNCTION 12 00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E) 1* < CONTROLLER NUMBER > ! ! < ADDRESS RESPONSE RAM DATA > *LD EN! *
TO MEM 2* 0 ! 1 ! ? * ? ! ? ! * ! ! PAR *TYPE ! GN2 ! GN1 * BN2 ! BN1 !DESEL*08-14! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E) 3* ! < ADDRESS RESPONSE RAM LOAD ADDRESS > ! ! < FUNCTION NUMBER > *
TO MEM 4* ! ! 14 * 15 ! 16 ! 17 * 18 ! 19 ! 20 * 21 ! ! * ! 0 ! 1 * 0 ! 1 ! 0 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E+1) 5* ! < ADDRESS RESPONSE RAM ECHO > * *
FROM MEM 6* ! ! * ! ! * ! ! PAR *TYPE ! GN2 ! GN1 * BN2 ! BN1 !DESEL* ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E+1) 7* *
FROM MEM 8* ! ! * ! ! * ! ! * ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
NOTE: "DESEL" (BIT 14) IS "BOX DESELECTED ON 1".
*** MF20 STORAGE ORGANIZATION ***
--------------------------------------------------------------------------------------------------------------------------------
MF20 STORAGE IS COMPOSED OF GROUPS, FIELDS, BLOCKS, & SUBBLOCKS. KL10 BIT NUMBER VS. "FIELD" LOCATION
A GROUP IS A SET OF FOUR STORAGE BOARDS. A FIELD IS ONE BOARD (11 BITS) ----------------------------------------
WIDE. 4 FIELDS USED IN PARALLEL GIVE A 44-BIT WORD: 36 DATA BITS, 6 ECC
(ERROR CHECK & CORRECT) BITS, ONE 43-BIT PARITY BIT, AND ONE SPARE BIT. KL10 BIT BIT IN SYNDROME
A BIT'S GROUP AND FIELD NUMBERS UNIQUELY PICK THE BIT'S STORAGE BOARD. BIT USE FIELD FIELD (NOTE 1)
A GROUP HAS 1 TO 4 BLOCKS (USUALLY 4) NUMBERED FROM 0. A BLOCK'S SIZE ---- ------ ----- ------ --------
IS 4 TIMES RAM SIZE. ITS START ADDRESS IS PROGRAMMABLE (SBDIAG FCN 12). 00 DATA 0 02 014
EACH BLOCK HAS 4 SUBBLOCKS. SUBBLOCKS ARE THE BASIC MF20 STORAGE UNIT, 01 DATA 1 02 024
ARE 1 WORD (44 BITS) WIDE, AND ARE SELECTED BY ADDRESS 34-35. EVERY 4TH 02 DATA 0 03 030
WORD OF A BLOCK'S MEMORY BELONGS TO A GIVEN SUBBLOCK. THERE IS 1 SPARE 03 DATA 1 03 034
BIT RAM PER SUBBLOCK. DURING A MEMORY CYCLE ALL OF THE BLOCK'S FIELDS 04 DATA 0 04 044
AND SUBBLOCKS ARE ALWAYS CYCLED, WITH THE 4 XBUS REQUEST BITS SPECIFYING 05 DATA 1 04 050
WHICH SUBBLOCK'S WORDS ARE ACTUALLY TO BE USED. 06 DATA 0 05 054
07 DATA 1 05 060
TABLE OF SLOT NUMBERS VS. GROUP, FIELD, AND BIT. 08 DATA 0 06 064
-------------------------------------------------------- 09 DATA 1 06 070
10 DATA 0 07 074
SLOT GROUP FIELD BITS 11 DATA 1 07 104
---- ----- ----- -------------------------------- 12 DATA 0 08 110
8 2 0 36,38,00,02,04,06,08,10,12,14,16 13 DATA 1 08 114
9 1 0 SAME 14 DATA 0 09 120
10 0 0 SAME 15 DATA 1 09 124
11 2 1 37,39,01,03,05,07,09,11,13,15,17 16 DATA 0 10 130
12 1 1 SAME 17 DATA 1 10 134
13 0 1 SAME 18 DATA 2 02 140
14 2 2 40,42,18,20,22,24,26,28,30,32,34 19 DATA 3 02 144
15 1 2 SAME 20 DATA 2 03 150
16 0 2 SAME 21 DATA 3 03 154
17 2 3 41,43,19,21,23,25,27,29,31,33,35 22 DATA 2 04 160
18 1 3 SAME 23 DATA 3 04 164
19 0 3 SAME 24 DATA 2 05 170
25 DATA 3 05 174
------------------------------------------------------------------------ 26 DATA 2 06 204
27 DATA 3 06 210
CALCULATING A FAILED RAM "E" NUMBER 28 DATA 2 07 214
----------------------------------- 29 DATA 3 07 220
30 DATA 2 08 224
TO CALCULATE THE "E" NUMBER OF A RAM ON AN M8579 BOARD YOU NEED 31 DATA 3 08 230
THE BLOCK NUMBER (BN), WORD NUMBER (WN), AND BIT-IN-FIELD NUMBER (BIFN). 32 DATA 2 09 234
USE ERROR ADDRESS BITS 14-21 IN AN SBDIAG FUNCTION 12 TO READ THE 33 DATA 3 09 240
ADDRESS RESPONSE RAM. BITS 12-13 OF THE SBDIAG ECHO ARE BN. ERROR 34 DATA 2 10 244
ADDRESS BITS 34-35 ARE WN. BIFN CAN BE DERIVED FROM THE TABLE ON THE 35 DATA 3 10 250
RIGHT USING EITHER THE SYNDROME (FROM FUNCTION 6.1) OR KNOWN ERROR DATA 36 ECC32 0 00 200
PATTERN. USE BIFN TO SELECT A NUMBER FROM THE TABLE BELOW AND PLUG THAT 37 ECC16 1 00 100
NUMBER INTO THE FORMULA TO GET THE ACTUAL "E" NUMBER. 38 ECC8 0 01 040
39 ECC4 1 01 020
BIFN: 0 1 2 3 4 5 6 7 8 9 10 40 ECC2 2 00 010
TABLE: 19. 38. 57. 76. 96. 116. 149. 167. 188. 204. 224. 41 ECC1 3 00 004
42 ECCPAR 2 01 000
FORMULA: E# = TABLE(BIFN) - (4 * WN) - BN 43 SPARE 3 01 (NOTE 2)
NOTE 1: THE SYNDROME IS A SIX BIT NUMBER AND IS SHOWN HERE OCTALLY GROUPED AS IT WOULD APPEAR IN AN SBDIAG FUNCTION 6.1 ECHO
IN BITS 07-12. NOTE THAT THE 43-BIT PARITY BIT IS NOT INCLUDED IN THIS LIST.
NOTE 2: THE SPARE BIT HAS NO ASSOCIATED SYNDROME. IF THE SPARE BIT HAPPENS TO BE REPLACING THE BIT WHICH YOUR SYNDROME
POINTS TO, THEN THE ERROR IS IN THE SPARE BIT AND NOT THE BIT WHICH THE SYNDROME POINTS TO.
MF20 ARRAY BOARD PROM DATA. M8579 MF20 STORAGE ARRAY BOARD E NUMBER LAYOUT
------------------------------------------------------------------------ ----------------------------------------------------
EVERY MF20 STORAGE ARRAY BOARD HAS ASSOCIATED WITH IT A SERIAL THE M8579 STORAGE BOARDS DO NOT HAVE ANY E NUMBERS
NUMBER AND OTHER RELATED DATA. THERE IS ONE 32-BIT PROM "WORD" PER ETCHED ON THEM, MAKING IT DIFFICULT TO LOCATE A
BOARD WHICH IS READ USING FUNCTION 2. WHICH WORD YOU GET DEPENDS UPON SPECIFIC DIP. USE THE MAP BELOW TO LOCATE MOS RAM
Bits 9-12. FOUR SBDIAGS ARE NECESSARY TO READ THE ENTIRE WORD BY DIPS OR DC008 MUX DIPS. EXAMPLE: THE E NUMBER FOR
VARYING THE BYTE NUMBER IN BITS 13 & 14. THE LAYOUT OF A PROM WORD IS BLOCK (BLK) 2, SUBBLOCK (SBLK) 1, BIT 18 WOULD BE
AS FOLLOWS: 51. USE BLK & SBLK TO FIND THE ROW. USING THE BIT
NUMBER, LOOK IN THE LOWER TABLE TO FIND THE COLUMN.
PROM BYTE: 0 1 2 3 THE MAP IS ORIENTED AS IF YOU HELD THE BOARD WITH
PROM BIT: 01234567012345670123456701234567 THE COMPONENT SIDE UP AND THE CONNECTOR EDGE TOWARDS
CONTENT: YYYYWWWWWW###########PPABNNSSMMM YOU. NOTE THAT THE ROW OF MUX CHIPS IS STAGGERED.
YYYY IS THE 4 BIT YEAR NUMBER WHICH IS THE BCD EQUIVALENT OF THE BLK SBLK MOS RAM AND MUX CHIP E NUMBERS
LAST DIGIT OF THE CALENDAR YEAR. --- ---- -------------------------------------------
WWWWWW IS THE 6 BIT WEEK NUMBER. 0 0 224 204 188 167 149 116 96 76 57 38 19
1 0 223 203 187 166 148 115 95 75 56 37 18
##...## IS AN 11 BIT SERIAL NUMBER WHICH IS RESTARTED FROM 1 EACH WEEK. 2 0 222 202 186 165 147 114 94 74 55 36 17
3 0 221 201 185 164 146 113 93 73 54 35 16
PP IS A MOS RAM POPULATION CODE: 00 - MOS RAM BLOCK 0 EXISTS 0 1 220 200 184 163 145 112 92 72 53 34 15
01 - BLOCKS 0 & 1 EXIST 1 1 219 199 183 162 144 111 91 71 52 33 14
10 - BLOCKS 0, 1, & 2 EXIST 2 1 218 198 182 161 143 110 90 70 51 32 13
11 - BOARD IS FULLY POPULATED 3 1 217 197 181 160 142 109 89 69 50 31 12
0 2 216 196 180 159 141 108 88 68 49 30 11
A PARITY BIT SUCH THAT BYTES 0-2 OF THE WORD HAVE EVEN PARITY. 1 2 215 195 179 158 140 107 87 67 48 29 10
2 2 214 194 178 157 139 106 86 66 47 28 9
B ANOTHER PARITY BIT SUCH THAT BYTE 3 HAS ODD PARITY. 3 2 213 193 177 156 138 105 85 65 46 27 8
0 3 212 192 176 155 137 104 84 64 45 26 7
NN IS THE 2 BIT "TIMING NUMBER". THIS NUMBER DETERMINES WHICH 1 3 211 191 175 154 136 103 83 63 44 25 6
DISTINCT TIMING IS TO BE USED WITH THE RAMS ON THIS BOARD. 2 3 210 190 174 153 135 102 82 62 43 24 5
3 3 209 189 173 152 134 101 81 61 42 23 4
SS IS THE MOS RAM SIZE CODE: 11 - INDICATES 4K RAMS MUX ==> 207 205 171 169 131 98 79 59 40 20 2
10 - 16K RAMS
01 - 32K RAMS FIELD KL10 BIT NUMBERS AS POSITIONED IN FIELD
00 - 64K RAMS ----- -------------------------------------------
0 16 14 12 10 08 06 04 02 00 38 36
MMM IS THE 3 BIT MOS RAM MANUFACTURER CODE: 1 17 15 13 11 09 07 05 03 01 39 37
2 34 32 30 28 26 24 22 20 18 42 40
000 - MOSTEK 100 - MOTOROLA 3 35 33 31 29 27 25 23 21 19 43 41
001 - INTEL 101 - T.I.
010 - FUJITSU 110 - OTHER (DEC, DEC PART NUMBER, ETC.)
011 - HITACHI 111 - UNASSIGNED ====================================================
THERE ARE ACTUALLY 8 PROM WORDS PER ARRAY BOARD, OF WHICH ONLY
ONE IS ALLOWED OUT BY THE STATE OF THE 3 JUMPERS. IF NO JUMPER IS CUT CONTROL BOARD SLOT NUMBERS & BASIC FUNCTIONS
THEN WORD 0 IS SELECTED, IF ALL ARE CUT THEN WORD 7 IS SELECTED. THESE ----------------------------------------------------
JUMPERS ARE CUT IN RELATION TO THE MANUFACTURER OF THE MOS RAMS ON THE
BOARD. NOTE ALSO THAT THE SERIAL NUMBER IS ALSO PRINTED ON THE BOARD IN NUMBER NAME SLOT FUNCTION
THE FORM:
YWW#### M8574 WRP 04 XBUS DATA/WR PATH/ECC GEN/SPARE OUT
M8576 CTL 05 XBUS & CYC CTL/WD & GRP SEL/PROM RD
**** PLEASE MAKE SURE WHEN AN ARRAY BOARD IS SENT IN FOR REPAIR THAT THE M8575 SYN 06 SPARE IN/CHK/CORR/ADR 14-21/V MARG
**** ERROR TYPEOUT SHOWING THE SERIAL NUMBER IS ATTACHED TO THE BOARD. M8577 ADT 07 MOS ADR/TIMING/REFRESH/BLK SEL/ERR
MG20 ARRAY BOARD (M8570)
CALCULATING A FAILED RAM "E" NUMBER
-----------------------------------
TO CALCULATE THE "E" NUMBER OF A RAM ON AN M8570 BOARD YOU NEED
THE BLOCK NUMBER (BN), WORD NUMBER (WN), AND BIT-IN-FIELD NUMBER (BIFN).
USE ERROR ADDRESS BITS 14-21 IN AN SBDIAG FUNCTION 12 TO READ THE
ADDRESS RESPONSE RAM. BITS 12-13 OF THE SBDIAG ECHO ARE BN. ERROR
ADDRESS BITS 34-35 ARE WN. BIFN CAN BE DERIVED FROM THE TABLE ON THE
RIGHT USING EITHER THE SYNDROME (FROM FUNCTION 6.1) OR KNOWN ERROR DATA
PATTERN. USE BIFN TO SELECT A NUMBER FROM THE TABLE BELOW AND PLUG THAT
NUMBER INTO THE FORMULA TO GET THE ACTUAL "E" NUMBER.
BIFN: 0 1 2 3 4 5 6 7 8 9 10
TABLE: 19. 38. 57. 75. 92. 112. 146. 165. 183. 202. 221.
FORMULA: E# = TABLE(BIFN) - (4 * WN) - BN
M8570 MG20 STORAGE ARRAY BOARD E NUMBER LAYOUT
M8570 STORAGE BOARDS DO NOT HAVE ANY E NUMBERS ETCHED ON THEM, MAKING IT DIFFICULT TO LOCATE A SPECIFIC DIP. USE THE MAP BELOW
TO LOCATE MOS RAM DIPS OR DC008 MUX DIPS. EXAMPLE: THE E NUMBER FOR BLOCK (BLK) 2, SUBBLOCK (SBLK) 1, BIT 18 WOULD BE 51. USE
BLK & SBLK TO FIND THE ROW. USING THE BIT NUMBER, LOOK IN THE LOWER TABLE TO FIND THE COLUMN. THE MAP IS ORIENTED AS IF YOU
HELD THE BOARD WITH THE COMPONENT SIDE UP AND THE CONNECTOR EDGE TOWARDS YOU. NOTE THAT THE ROW OF MUX CHIPS IS STAGGERED.
BLK SBLK MOS RAM AND MUX CHIP E NUMBERS
-----------------------------------------------------
0 0 221 202 183 165 146 112 92 75 57 38 19
1 0 220 201 182 164 145 111 91 74 56 37 18
2 0 219 200 181 163 144 110 90 73 55 36 17
3 0 218 199 180 162 143 109 89 72 54 35 16
0 1 217 198 179 161 142 108 88 71 53 34 15
1 1 216 197 178 160 141 107 87 70 52 33 14
2 1 215 196 177 159 140 106 86 69 51 32 13
3 1 214 195 176 158 139 105 85 68 50 31 12
0 2 213 194 175 157 138 104 84 67 49 30 11
1 2 212 193 174 156 137 103 83 66 48 29 10
2 2 211 192 173 155 136 102 82 65 47 28 9
3 2 210 191 172 154 135 101 81 64 46 27 8
0 3 209 190 171 153 134 100 80 63 45 26 7
1 3 208 189 170 152 133 99 79 62 44 25 6
2 3 207 188 169 151 132 98 78 61 43 24 5
3 3 206 187 168 150 131 97 77 60 42 23 4
MUX ==> 204 203 185 148 128 114 95 58 40 20 2
FIELD KL10 BIT NUMBERS AS POSITIONED IN FIELD
----- -------------------------------------------
0 16 14 12 10 08 06 04 02 00 38 36
1 17 15 13 11 09 07 05 03 01 39 37
2 34 32 30 28 26 24 22 20 18 42 40
3 35 33 31 29 27 25 23 21 19 43 41
====================================================
*** MF20 ERROR CORRECTION CODE (ECC) CALCULATION ***
CALCULATION OF THE ECC IS BASED UPON BIT CHANGES FROM A DATA WORD OF ALL ZEROS. THE ECC FOR ALL ZEROS IS DEFINED TO BE
11 111 11 (OR 376 AS IT WOULD APPEAR IN BITS 07-13 OF AN SBDIAG FUNC 6.0). TO CALCULATE WHAT THE ECC SHOULD BE FOR ANY GIVEN WORD:
TAKE EACH "1" BIT FROM THE DATA WORD, GET THE SYNDROME FOR THAT BIT FROM THE TABLE BELOW, AND XOR IT INTO THE PREVIOUS ECC.
INITIALLY THE ECC IS THE ECC FOR A DATA WORD OF ZERO.
IF THERE ARE MORE ONES THAN ZEROS IN THE WORD THEN DO THE SAME AS ABOVE ONLY APPLY THE SYNDROMES FOR EACH "0" BIT AND USE
THE INITIAL ECC VALUE OF 10 101 11 (256 OCTAL). NOTE THAT THE FOLLOWING RELATION ALWAYS HOLDS:
ECC(X)=120.XOR.ECC(.NOT.X)
WHICH MEANS THAT THE ECC FOR THE COMPLEMENT OF A WORD DIFFERS FROM THE ECC OF THE WORD BY 120 OCTAL.
*** SYNDROME & 43-BIT PARITY TABLE ***
BIT FCN 6 SYN SYN SYN SYN SYN SYN 43B
# OCTAL 32 16 8 4 2 1 PAR
--- ----- --- --- --- --- --- --- ---
00 016 0 0 0 0 1 1 1 EXAMPLE: CALCULATE THE ECC & 43-BIT PARITY FOR A DATA WORD OF 3
01 026 0 0 0 1 0 1 1
02 032 0 0 0 1 1 0 1 376 IS ECC FOR ZERO
03 034 0 0 0 1 1 1 0 250 IS SYNDROME & 43B PAR FOR BIT 35
04 046 0 0 1 0 0 1 1 244 IS SYNDROME & 43B PAR FOR BIT 34
05 052 0 0 1 0 1 0 1 --- .XOR. ALL OF THE ABOVE
06 054 0 0 1 0 1 1 0 362 IS THE ECC FOR 3
07 062 0 0 1 1 0 0 1
08 064 0 0 1 1 0 1 0
09 070 0 0 1 1 1 0 0
10 076 0 0 1 1 1 1 1
11 106 0 1 0 0 0 1 1 ANOTHER METHOD FOR COMPUTING THE ECC IS AS FOLLOWS: FOR EACH OF THE 7
12 112 0 1 0 0 1 0 1 ECC BITS TAKE THE DATA WORD, .AND. IT WITH THE APPROPRIATE MASK BELOW,
13 114 0 1 0 0 1 1 0 AND COMPUTE THE RESULT'S ODD PARITY. THAT BIT IS ONE OF THE ECC BITS.
14 122 0 1 0 1 0 0 1
15 124 0 1 0 1 0 1 0 000000 001777 ECC 32
16 130 0 1 0 1 1 0 0 000177 776000 ECC 16
17 136 0 1 0 1 1 1 1 037600 776007 ECC 8
18 142 0 1 1 0 0 0 1 343617 036170 ECC 4
19 144 0 1 1 0 0 1 0 554663 146631 ECC 2
20 150 0 1 1 0 1 0 0 665325 253252 ECC 1
21 156 0 1 1 0 1 1 1 732351 455514 43B PAR
22 160 0 1 1 1 0 0 0
23 166 0 1 1 1 0 1 1
24 172 0 1 1 1 1 0 1
25 174 0 1 1 1 1 1 0
26 206 1 0 0 0 0 1 1
27 212 1 0 0 0 1 0 1 BITS 03, 09, 10, 13, 15, 25, AND 32 (040624 002010) FORM A SET WHICH IS
28 214 1 0 0 0 1 1 0 ONE OF MANY POSSIBLE "INDEPENDENT" BIT SETS. BY VARYING THE VALUES OF
29 222 1 0 0 1 0 0 1 THESE 7 BITS ONE CAN GENERATE ALL 128 ECC CODES, THOUGH NOT IN ANY
30 224 1 0 0 1 0 1 0 SPECIAL ORDER. ADDING BIT 35 ALLOWS PLAYING WITH THE SPARE BIT BUT DOES
31 230 1 0 0 1 1 0 0 NOT ALTER THE INDEPENDENCE OF THIS BIT SET.
32 236 1 0 0 1 1 1 1
33 242 1 0 1 0 0 0 1
34 244 1 0 1 0 0 1 0 NOTE THAT THE OCTAL NUMBER 200,,2217 (33555599 DECIMAL) IS A SMALL,
35 250 1 0 1 0 1 0 0 RELATIVELY EASY TO REMEMBER NUMBER WHICH PRODUCES AN ALL ZEROS ECC.
-- -- -- -- -- -- --
10 15 18 19 20 20 20 <== SUM OF SYNDROME ONE BITS
*** MF20 ERROR DETECTION AND CORRECTION ***
---------------------------------------------
HOW MF20 ERROR CORRECTION WORKS. AN EXAMPLE OF ERROR CORRECTION.
-------------------------------- -------------------------------
WHEN A WRITE IS DONE THE MF20 CALCULATES AN ECC BASED UPON THE WRITE A 3 TO MEMORY, ASSUME THAT BIT 27 IS STUCK
DATA IT GOT FROM THE CPU. THE DATA AND THE ECC ARE THEN PUT IN MEMORY. HIGH IN MEMORY. AS SHOWN ON THE PREVIOUS PAGE
WHEN A READ IS DONE THE MF20 GETS THE DATA AND THE OLD ECC FROM MEMORY. THE ECC FOR 3 IS 362, THEREFORE:
IT THEN COMPUTES A NEW ECC ON THE DATA AND XOR'S THE OLD AND NEW ECC'S 3<362> GOES TO MEMORY.
WHICH RESULTS IN A SYNDROME. OBVIOUSLY IF THERE WAS NO ERROR IN MEMORY ON THE READ BIT 27 IS STUCK HIGH SO THAT WE SEE:
THE OLD AND NEW ECC'S WILL BE THE SAME, AND THE SYNDROME WILL BE ZERO 403<362> FROM MEMORY.
SINCE XOR'ING EQUAL VALUES PRODUCES 0. WE CALCULATE THE NEW ECC:
374 IS ECC FOR 0 (LESS 43B PAR BIT)
NOW, WHEN THERE IS AN ERROR IN ONE BIT THE NEW SYNDROME WILL 250 IS SYNDROME FOR BIT 35
DIFFER FROM WHAT IT WOULD HAVE BEEN BY A VALUE EQUAL TO THE SYNDROME OF 244 IS SYNDROME FOR BIT 34
THE BAD BIT. THUS XOR'ING THE NEW SYNDROME WITH THE OLD ONE FROM MEMORY 210 IS SYNDROME FOR BIT 27
WILL RESULT IN A SYNDROME EQUAL TO THAT OF THE BAD BIT. THE SYNDROME --- XOR THE WHOLE MESS TOGETHER
MAPPED TO A BIT WHICH, IN TURN, IS USED TO COMPLEMENT (IE CORRECT) THE 170 IS THE NEW ECC.
BAD BIT. SEE EXAMPLE ON RIGHT AT TOP. WE NOW CALCULATE THE SYNDROME:
360 IS THE OLD ECC (LESS 43B PAR BIT)
WHEN ONE BIT IS BAD ON A READ THEN, OBVIOUSLY, THE PARITY OF THE 170 IS THE NEW ECC
43-BIT WORD FROM MEMORY WILL BE BAD. BAD PARITY IS WHAT CAUSES THE MF20 --- XOR
TO RECOGNIZE A CORRECTABLE ERROR. THE MF20 THEN GOES OFF AND COMPUTES 210 IS THE SYNDROME
THE SYNDROME. IF THE SYNDROME IS THAT OF ONE OF THE ECC BITS THEN THE THE HARDWARE MAPS THE SYNDROME TO THE PROPER BIT
MAPPED CORRECTION BIT GOES NOWHERE SINCE WE DON'T SEND THE ECC BACK TO AND CHANGES THE BIT:
THE CPU. 403 IS DATA FROM MEMORY
400 IS THE MAPPED BIT
IF THERE IS NO PARITY ERROR AND THE SYNDROME IS ZERO THEN THERE --- XOR
IS NO CORRECTION NECESSARY. HOWEVER A DOUBLE BIT (UNCORRECTABLE) ERROR 3 IS WHAT GOES BACK TO THE CPU.
GIVES GOOD PARITY (SINCE 2 BITS ARE BAD) AND A NONZERO SYNDROME. THIS HOCUS-POCUS-PRESTO-CHANGO, THE ERROR IS GONE!
IS HOW AN MF20 RECOGNIZES AN DOUBLE BIT ERROR. WHEN A DOUBLE BIT ERROR
IS DETECTED THE MF20 SHIPS THE DATA, AS IS, TO THE CPU WHILE FORCING BAD ----------------------------------------------------
XBUS PARITY. SEE THE TABLE ON THE RIGHT AT THE BOTTOM FOR A CONCISE
LIST OF ERROR CONDITIONS. SYNDROME PARITY MEANING & ACTION TAKEN BY MF20
-------- ------ ------------------------------
SOFTWARE DOUBLE BIT ERROR CORRECTION.
------------------------------------- ZERO OK EVERY THING IS OK. TAKE DATA
AS IT IS.
WHEN A DOUBLE BIT ERROR OCCURS ALL IS NOT LOST. WE MAY BE ABLE
TO RECOVER THE DATA USING A SOFTWARE ALGORITHM PROVIDED THAT AT LEAST ZERO BAD 43-BIT PARITY BIT IS BAD.
ONE OF THE BAD BITS IS A HARD FAILURE. (1) GET THE WORD AND ITS USE THE DATA AS IT IS.
SYNDROME. (2) WRITE THE WORD'S COMPLEMENT TO THE FAILED LOCATION. (3)
EQUIVALENCE THE MEMORY WORD WITH THE ORIGINAL WORD. (4) IF THE RESULT IS 1,2,4,8, BAD AN ECC BIT IS BAD. USE THE
ZERO OR HAS MORE THAN 2 BITS SET, PUNT. (5) IF EXACTLY TWO BITS ARE SET 16,32 DATA AS IT IS.
IN THE EQUIVALENCE THEN XOR IT INTO THE ORIGINAL WORD AND YOU'RE DONE.
(6) IF THERE IS ONE BIT SET IN THE EQUIVALENCE THEN GET ITS BIT NUMBER. NOT 0 OR BAD A DATA BIT IS BAD. CORRECT IT
(7) USE THE ORIGINAL SYNDROME TO FIND THE LINE IN THE TABLE ON THE NEXT 1,2, ETC AND SEND BACK CORRECTED WORD.
PAGE WHERE YOU WILL LOOK. (8) FIND THE BIT PAIR CONTAINING THE BIT. (9)
IF NOT FOUND, PUNT. (10) CORRECT THE BITS IN THE ORIGINAL WORD INDICATED NOT 0 OK THIS IS A NON-CORRECTABLE
BY THE BIT PAIR AND YOU'RE DONE. ERROR. PUT DATA ON XBUS AS
IT IS PLUS BAD PARITY.
THIS ALGORITHM BECOMES MORE COMPLICATED WHEN THE ECC & SPARE ARE
TAKEN INTO CONSIDERATION TOO. HOWEVER THE ESSENTIAL IDEA REMAINS THE
SAME. WHILE SOFTWARE CORRECTION OF DOUBLE BIT ERRORS IS NOT IMPLEMENTED
THE BASIC ALGORITHM IS INCLUDED HERE SHOULD THE NEED FOR IT ARISE.
THIS IS THE TABLE OF SYNDROMES VS. ALL POSSIBLE BIT PAIRS WHICH COULD CAUSE A DOUBLE
BIT ERROR WITH THAT SYNDROME. THE SYNDROME IS THE OCTAL NUMBER ON THE LEFT. REMEMBER THAT
IT IS ONLY 6 BITS BUT IS SHOWN ALIGNED AS IT IS IN AN SBUS DIAG FUNCTION 6.1. ALL THE BIT
PAIRS WHICH WOULD RESULT IN A GIVEN SYNDROME ARE ON THE LINE TO THE RIGHT OF THE SYNDROME.
THESE PAIRS ARE DECIMAL KL10 BIT NUMBERS WITH THE LOWER NUMBER OF THE PAIR TO THE LEFT OF THE
COMMA. THE PAIRS ARE IN ORDER BY THE LOWER NUMBER. THE TABLE CONTINUES ON THE NEXT PAGE.
SYN BIT PAIRS WHICH COULD CAUSE A DBE WITH THE GIVEN SYNDROME
--- ---------------------------------------------------------
374 15,35 16,34 17,33 18,32 19,31 20,30 21,29 22,28 23,27 24,26 25,36
370 14,35 16,33 17,34 18,31 19,32 20,29 21,30 22,27 23,28 24,36 25,26
364 14,34 15,33 17,35 18,30 19,29 20,32 21,31 22,26 23,36 24,28 25,27
360 14,33 15,34 16,35 18,29 19,30 20,31 21,32 22,36 23,26 24,27 25,28
354 11,35 12,34 13,33 18,28 19,27 20,26 21,36 22,32 23,31 24,30 25,29
350 12,33 13,34 18,27 19,28 20,36 21,26 22,31 23,32 24,29 25,30 35,37
344 11,33 13,35 18,26 19,36 20,28 21,27 22,30 23,29 24,32 25,31 34,37
340 11,34 12,35 18,36 19,26 20,27 21,28 22,29 23,30 24,31 25,32 33,37
334 11,31 12,30 13,29 14,28 15,27 16,26 17,36 23,35 24,34 25,33 32,37
330 11,32 12,29 13,30 14,27 15,28 16,36 17,26 22,35 24,33 25,34 31,37
324 11,29 12,32 13,31 14,26 15,36 16,28 17,27 22,34 23,33 25,35 30,37
320 11,30 12,31 13,32 14,36 15,26 16,27 17,28 22,33 23,34 24,35 29,37
314 11,27 12,26 13,36 14,32 15,31 16,30 17,29 19,35 20,34 21,33 28,37
310 11,28 12,36 13,26 14,31 15,32 16,29 17,30 18,35 20,33 21,34 27,37
304 11,36 12,28 13,27 14,30 15,29 16,32 17,31 18,34 19,33 21,35 26,37
300 11,26 12,27 13,28 14,29 15,30 16,31 17,32 18,33 19,34 20,35 36,37
274 01,35 02,34 03,33 04,31 05,30 06,29 07,28 08,27 09,26 10,36 32,38
270 02,33 03,34 04,32 05,29 06,30 07,27 08,28 09,36 10,26 31,38 35,39
264 01,33 03,35 04,29 05,32 06,31 07,26 08,36 09,28 10,27 30,38 34,39
260 01,34 02,35 04,30 05,31 06,32 07,36 08,26 09,27 10,28 29,38 33,39
254 00,33 04,27 05,26 06,36 07,32 08,31 09,30 10,29 28,38 34,40 35,41
250 00,34 04,28 05,36 06,26 07,31 08,32 09,29 10,30 27,38 33,40 35,42
244 00,35 04,36 05,28 06,27 07,30 08,29 09,32 10,31 26,38 33,41 34,42
240 04,26 05,27 06,28 07,29 08,30 09,31 10,32 33,42 34,41 35,40 36,38
234 00,29 01,27 02,26 03,36 08,35 09,34 10,33 28,39 30,40 31,41 32,42
230 00,30 01,28 02,36 03,26 07,35 09,33 10,34 27,39 29,40 31,42 32,41
224 00,31 01,36 02,28 03,27 07,34 08,33 10,35 26,39 29,41 30,42 32,40
220 00,32 01,26 02,27 03,28 07,33 08,34 09,35 29,42 30,41 31,40 36,39
214 00,36 01,31 02,30 03,29 04,35 05,34 06,33 26,40 27,41 28,42 32,39
210 00,26 01,32 02,29 03,30 05,33 06,34 27,42 28,41 31,39 35,38 36,40
204 00,27 01,29 02,32 03,31 04,33 06,35 26,42 28,40 30,39 34,38 36,41
200 00,28 01,30 02,31 03,32 04,34 05,35 26,41 27,40 29,39 33,38 36,42
SYN BIT PAIRS WHICH COULD CAUSE A DBE WITH THE GIVEN SYNDROME (CONTINUED FROM PREVIOUS PAGE)
--- -----------------------------------------------------------------------------------------
174 00,22 01,20 02,19 03,18 04,16 05,15 06,14 07,13 08,12 09,11 10,37 17,38 21,39 23,40 24,41 25,42
170 00,23 01,21 02,18 03,19 04,17 05,14 06,15 07,12 08,13 09,37 10,11 16,38 20,39 22,40 24,42 25,41
164 00,24 01,18 02,21 03,20 04,14 05,17 06,16 07,11 08,37 09,13 10,12 15,38 19,39 22,41 23,42 25,40
160 00,25 01,19 02,20 03,21 04,15 05,16 06,17 07,37 08,11 09,12 10,13 14,38 18,39 22,42 23,41 24,40
154 00,18 01,24 02,23 03,22 04,12 05,11 06,37 07,17 08,16 09,15 10,14 13,38 19,40 20,41 21,42 25,39
150 00,19 01,25 02,22 03,23 04,13 05,37 06,11 07,16 08,17 09,14 10,15 12,38 18,40 20,42 21,41 24,39
144 00,20 01,22 02,25 03,24 04,37 05,13 06,12 07,15 08,14 09,17 10,16 11,38 18,41 19,42 21,40 23,39
140 00,21 01,23 02,24 03,25 04,11 05,12 06,13 07,14 08,15 09,16 10,17 18,42 19,41 20,40 22,39 37,38
134 00,14 01,12 02,11 03,37 04,24 05,23 06,22 07,21 08,20 09,19 10,18 13,39 15,40 16,41 17,42 25,38
130 00,15 01,13 02,37 03,11 04,25 05,22 06,23 07,20 08,21 09,18 10,19 12,39 14,40 16,42 17,41 24,38
124 00,16 01,37 02,13 03,12 04,22 05,25 06,24 07,19 08,18 09,21 10,20 11,39 14,41 15,42 17,40 23,38
120 00,17 01,11 02,12 03,13 04,23 05,24 06,25 07,18 08,19 09,20 10,21 14,42 15,41 16,40 22,38 37,39
114 00,37 01,16 02,15 03,14 04,20 05,19 06,18 07,25 08,24 09,23 10,22 11,40 12,41 13,42 17,39 21,38
110 00,11 01,17 02,14 03,15 04,21 05,18 06,19 07,24 08,25 09,22 10,23 12,42 13,41 16,39 20,38 37,40
104 00,12 01,14 02,17 03,16 04,18 05,21 06,20 07,23 08,22 09,25 10,24 11,42 13,40 15,39 19,38 37,41
100 00,13 01,15 02,16 03,17 04,19 05,20 06,21 07,22 08,23 09,24 10,25 11,41 12,40 14,39 18,38 37,42
074 00,07 01,05 02,04 03,38 06,39 08,40 09,41 10,42 11,24 12,23 13,22 14,21 15,20 16,19 17,18 25,37 30,35 31,34 32,33
070 00,08 01,06 02,38 03,04 05,39 07,40 09,42 10,41 11,25 12,22 13,23 14,20 15,21 16,18 17,19 24,37 29,35 31,33 32,34
064 00,09 01,38 02,06 03,05 04,39 07,41 08,42 10,40 11,22 12,25 13,24 14,19 15,18 16,21 17,20 23,37 29,34 30,33 32,35
060 00,10 01,04 02,05 03,06 07,42 08,41 09,40 11,23 12,24 13,25 14,18 15,19 16,20 17,21 22,37 29,33 30,34 31,35 38,39
054 00,38 01,09 02,08 03,07 04,40 05,41 06,42 10,39 11,20 12,19 13,18 14,25 15,24 16,23 17,22 21,37 26,35 27,34 28,33
050 00,04 01,10 02,07 03,08 05,42 06,41 09,39 11,21 12,18 13,19 14,24 15,25 16,22 17,23 20,37 27,33 28,34 35,36 38,40
044 00,05 01,07 02,10 03,09 04,42 06,40 08,39 11,18 12,21 13,20 14,23 15,22 16,25 17,24 19,37 26,33 28,35 34,36 38,41
040 00,06 01,08 02,09 03,10 04,41 05,40 07,39 11,19 12,20 13,21 14,22 15,23 16,24 17,25 18,37 26,34 27,35 33,36 38,42
034 00,39 01,40 02,41 03,42 04,09 05,08 06,07 10,38 11,16 12,15 13,14 17,37 18,25 19,24 20,23 21,22 26,31 27,30 28,29 32,36
030 00,01 02,42 03,41 04,10 05,07 06,08 09,38 11,17 12,14 13,15 16,37 18,24 19,25 20,22 21,23 26,32 27,29 28,30 31,36 39,40
024 00,02 01,42 03,40 04,07 05,10 06,09 08,38 11,14 12,17 13,16 15,37 18,23 19,22 20,25 21,24 26,29 27,32 28,31 30,36 39,41
020 00,03 01,41 02,40 04,08 05,09 06,10 07,38 11,15 12,16 13,17 14,37 18,22 19,23 20,24 21,25 26,30 27,31 28,32 29,36 39,42
014 00,42 01,02 03,39 04,05 06,38 07,10 08,09 11,12 13,37 14,17 15,16 18,21 19,20 22,25 23,24 26,27 28,36 29,32 30,31 34,35 40,41
010 00,41 01,03 02,39 04,06 05,38 07,09 08,10 11,13 12,37 14,16 15,17 18,20 19,21 22,24 23,25 26,28 27,36 29,31 30,32 33,35 40,42
004 00,40 01,39 02,03 04,38 05,06 07,08 09,10 11,37 12,13 14,15 16,17 18,19 20,21 22,23 24,25 26,36 27,28 29,30 31,32 33,34 41,42
000 A ZERO SYNDROME NEVER CAUSES A DOUBLE BIT ERROR.
MISCELLANEOUS KL10 I/O INSTRUCTIONS RELATING TO THE MEMORY SYSTEM.
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APRID *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
700000 * < MICROCODE OPTIONS > * < MICROCODE VERSION NUMBER > *
LH(E) *KLPAG!XADDR!UNSTD* ! ! * ! !TRCKS* ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
* < HARDWARE OPTIONS > * < PROCESSOR SERIAL NUMBER > *
RH(E) *50 HZ!CACHE!CHANL* XADR!MSTR ! * ! ! * ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
CONO APR, *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
700200 * ! I/O ! SELECTED FLAGS * < SELECT FLAG > ! * PI LEVEL *
E * !RESET! EN * DIS ! CLR ! SET * SBUS! NXM ! IOPF*MBPAR!C DIR!ADR P*POWER!SWEEP! * 4 ! 2 ! 1 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
CONI APR, *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
700240 * * < ENABLED FLAGS > ! *
LH(E) * ! ! * ! ! * SBUS! NXM ! IOPF*MBPAR!C DIR!ADR P*POWER!SWEEP! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
* !SWEEP! * SBUS! ! I/O * MB !CACHE! ADDR*POWER!SWEEP! INT * PI LEVEL *
RH(E) * ! BUSY! * ! ! * ERR ! NXM ! PGF * PAR ! DIR ! PAR * FAIL! DONE! REQ * 4 ! 2 ! 1 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
RDERA *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
700400 * WORD NO !SWEEP* CHAN! DATA SRC *WRITE! ! PHYSICAL ADDRESS *
LH(E) * ! ! REF * REF ! ! * REF ! JUNK! JUNK* ! ! * ! ! 14 * 15 ! 16 ! 17 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
* < PHYSICAL ADDRESS OF FIRST WORD OF TRANSFER > *
RH(E) * 18 ! 19 ! 20 * 21 ! 22 ! 23 * 24 ! 25 ! 26 * 27 ! 28 ! 29 * 30 ! 31 ! 32 * 33 ! 34 ! 35 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
DATA SRC WRITE = 0 WRITE = 1
00 MEMORY (READ, RPW) CHANNEL (STORE STATUS)
01 CHANNEL (DATA STORE)
10 EBOX STORE FROM AR
11 READ FROM CACHE WRITEBACK FROM CACHE
(PG REFILL OR CHAN READ)
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
CONO PI, *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
700600 * WRITE EVEN PAR * ! DROP!CLEAR* REQ ! TURN CHAN * TURN SYS ! < SELECT CHANNEL > *
E * ADDR! DATA! DIR * ! INT ! SYS * INT ! ON ! OFF * OFF ! ON ! 1 * 2 ! 3 ! 4 * 5 ! 6 ! 7 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*