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klad.sources/mscrad.xrf
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1 %TITLE 'STIRS FAULT ISOLATION DATA FOR M8622 (CRA) BOARD'
2
3 MODULE MSCRAD (
4 LANGUAGE(BLISS36)
5 ) =
6
7 BEGIN
8
9 !
10 ! COPYRIGHT (C) 1979 BY
11 ! DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASS.
12 !
13 ! THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COPIED
14 ! ONLY IN ACCORDANCE WITH THE TERMS OF SUCH LICENSE AND WITH THE
15 ! INCLUSION OF THE ABOVE COPYRIGHT NOTICE. THIS SOFTWARE OR ANY OTHER
16 ! COPIES THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY
17 ! OTHER PERSON. NO TITLE TO AND OWNERSHIP OF THE SOFTWARE IS HEREBY
18 ! TRANSFERRED.
19 !
20 ! THE INFORMATION IN THIS SOFTWARE IS SUBJECT TO CHANGE WITHOUT NOTICE
21 ! AND SHOULD NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL EQUIPMENT
22 ! CORPORATION.
23 !
24 ! DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE OR RELIABILITY OF ITS
25 ! SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL.
26 !
27
28 !++
29 ! FACILITY: DECSYSTEM 2020 DIAGNOSTIC RELEASE TAPE 'DSTIR'
30 !
31 ! ABSTRACT:
32 !
33 ! THIS MODULE CONTAINS THE FAULT ISOLATION DATA FOR THE KS10
34 ! STIMULUS/RESPONSE (STIRS) DIAGNOSTIC FOR THE M8622 (CRA) BOARD.
35 ! IT IS LINKED TO THE 'MSSTRC' AND 'MSCRAT' MODULES TO PRODUCE
36 ! THE 'MSCRA.EXE' FILE.
37 !
38 ! ENVIRONMENT: RUNS UNDER 'CSL' ON A TOPS-20 SYSTEM.
39 !
40 ! AUTHOR: RICH MURATORI , CREATION DATE: 23-MAY-79
41 !
42 ! MODIFIED BY:
43 !
44 ! RICH MURATORI, 23-MAY-79; VERSION 0.1
45 !--
46 !
47 ! EQUATED SYMBOLS:
48 !
49
50 GLOBAL LITERAL
51 DATA_VERSION = 1, !VERSION NUMBER FOR THIS MODULE
52 DATA_EDIT = 0, !EDIT NUMBER FOR THIS MODULE
53 MAXNETS = 180;
54
55 !
56 ! MACROS:
57 !
58
59 MACRO
60 UPAZ(TEXT) = UPLIT(%ASCIZ TEXT)%,
61 AMX_00 = AMX11_00 AMX10_00 AMX9_00 AMX8_00 AMX7_00 AMX6_00 AMX5_00 AMX4_00 AMX3_00 AMX2_00 AMX1_00 AMX0_00%,
62
63
64 !DEFINING NETWORKS TO CORRESPOND TO BITS FOR WORD W_0
65
66 AMX = %ASSIGN (W_0,W_0 OR 1^0)%,
67 AMX0_1 = %ASSIGN (W_0,W_0 OR 1^1)%,
68 AMX2_3 = %ASSIGN (W_0,W_0 OR 1^2)%,
69 AMX4_5 = %ASSIGN (W_0,W_0 OR 1^3)%,
70 AMX6_7 = %ASSIGN (W_0,W_0 OR 1^4)%,
71 AMX8 = %ASSIGN (W_0,W_0 OR 1^5)%,
72 AMX9 = %ASSIGN (W_0,W_0 OR 1^6)%,
73 AMX10 = %ASSIGN (W_0,W_0 OR 1^7)%,
74 AMX11 = %ASSIGN (W_0,W_0 OR 1^8)%,
75 STKWRT = %ASSIGN (W_0,W_0 OR 1^9)%,
76 TCLKB = %ASSIGN (W_0,W_0 OR 1^10)%,
77 TCLKC = %ASSIGN (W_0,W_0 OR 1^11)%,
78 CLKD = %ASSIGN (W_0,W_0 OR 1^12)%,
79 CLKE = %ASSIGN (W_0,W_0 OR 1^13)%,
80 CLKF = %ASSIGN (W_0,W_0 OR 1^14)%,
81 CLKH = %ASSIGN (W_0,W_0 OR 1^15)%,
82 CLKJ = %ASSIGN (W_0,W_0 OR 1^16)%,
83 CLKEN = %ASSIGN (W_0,W_0 OR 1^17)%,
84 SYNCH = %ASSIGN (W_0,W_0 OR 1^18)%,
85 PFBUF = %ASSIGN (W_0,W_0 OR 1^19)%,
86 DSP_SKP_EN = %ASSIGN (W_0,W_0 OR 1^20)%,
87 FRSTCYC = %ASSIGN (W_0,W_0 OR 1^21)%,
88 IOLTCH = %ASSIGN (W_0,W_0 OR 1^22)%,
89 SYNCL = %ASSIGN (W_0,W_0 OR 1^23)%,
90 RTN = %ASSIGN (W_0,W_0 OR 1^24)%,
91 CALLRTN = %ASSIGN (W_0,W_0 OR 1^25)%,
92 RESET = %ASSIGN (W_0,W_0 OR 1^26)%,
93 STKRST = %ASSIGN (W_0,W_0 OR 1^27)%,
94 SKIP10 = %ASSIGN (W_0,W_0 OR 1^28)%,
95 SPEC10 = %ASSIGN (W_0,W_0 OR 1^29)%,
96 AREAD = %ASSIGN (W_0,W_0 OR 1^30)%,
97 NIC_ENC = %ASSIGN (W_0,W_0 OR 1^31)%,
98 TRPCYC = %ASSIGN(W_0,W_0 OR 1^32)%,
99 AMX0_00 = %ASSIGN (W_0,W_0 OR 1^33)%,
100 ADR11 = %ASSIGN(W_0,W_0 OR 1^34)%,
101 CRAM = %ASSIGN(W_0,W_0 OR 1^35)%,
102
103 !DEFINING NETWORKS TO CORRESPOND TO BITS FOR WORD W_1
104
105 STACK = %ASSIGN (W_1,W_1 OR 1^0)%,
106 STKADR = %ASSIGN (W_1,W_1 OR 1^1)%,
107 SBRET1 = %ASSIGN (W_1,W_1 OR 1^2)%,
108 SBRET2 = %ASSIGN (W_1,W_1 OR 1^3)%,
109 SBRET3 = %ASSIGN (W_1,W_1 OR 1^4)%,
110 STACK1 = %ASSIGN (W_1,W_1 OR 1^5)%,
111 STACK2 = %ASSIGN (W_1,W_1 OR 1^6)%,
112 STACK3 = %ASSIGN (W_1,W_1 OR 1^7)%,
113 CLOC1 = %ASSIGN (W_1,W_1 OR 1^8)%,
114 CLOC2 = %ASSIGN (W_1,W_1 OR 1^9)%,
115 CLOC3 = %ASSIGN (W_1,W_1 OR 1^10)%,
116 DMX0 = %ASSIGN (W_1,W_1 OR 1^11)%,
117 DMX1 = %ASSIGN (W_1,W_1 OR 1^12)%,
118 DMX2 = %ASSIGN (W_1,W_1 OR 1^13)%,
119 DMX3 = %ASSIGN (W_1,W_1 OR 1^14)%,
120 DMX4 = %ASSIGN (W_1,W_1 OR 1^15)%,
121 DMX5 = %ASSIGN (W_1,W_1 OR 1^16)%,
122 DMX6 = %ASSIGN (W_1,W_1 OR 1^17)%,
123 DMX7 = %ASSIGN (W_1,W_1 OR 1^18)%,
124 DMX11 = %ASSIGN (W_1,W_1 OR 1^19)%,
125 DFN0 = %ASSIGN (W_1,W_1 OR 1^20)%,
126 DFN1 = %ASSIGN (W_1,W_1 OR 1^21)%,
127 DFN2 = %ASSIGN (W_1,W_1 OR 1^22)%,
128 DFN3 = %ASSIGN (W_1,W_1 OR 1^23)%,
129 DFN4 = %ASSIGN (W_1,W_1 OR 1^24)%,
130 DFN5 = %ASSIGN (W_1,W_1 OR 1^25)%,
131 DFN6 = %ASSIGN (W_1,W_1 OR 1^26)%,
132 DFN7 = %ASSIGN (W_1,W_1 OR 1^27)%,
133 DFN11 = %ASSIGN (W_1,W_1 OR 1^28)%,
134 CWRT0_5 = %ASSIGN (W_1,W_1 OR 1^29)%,
135 CWRT6_11 = %ASSIGN (W_1,W_1 OR 1^30)%,
136 CWRT12_17 = %ASSIGN (W_1,W_1 OR 1^31)%,
137 CWRT18_23 = %ASSIGN (W_1,W_1 OR 1^32)%,
138 CWRT24_29 = %ASSIGN (W_1,W_1 OR 1^33)%,
139 CWRT30_35 = %ASSIGN (W_1,W_1 OR 1^34)%,
140 DADR = %ASSIGN (W_1,W_1 OR 1^35)%,
141
142 !DEFINING NETWORKS TO CORRESPOND TO BITS FOR WORD W_2
143
144 DADR1 = %ASSIGN (W_2,W_2 OR 1^0)%,
145 DADR2 = %ASSIGN (W_2,W_2 OR 1^1)%,
146 DADR3 = %ASSIGN (W_2,W_2 OR 1^2)%,
147 BUSBUF = %ASSIGN (W_2,W_2 OR 1^3)%,
148 XCVRS = %ASSIGN (W_2,W_2 OR 1^4)%,
149 PARNET = %ASSIGN (W_2,W_2 OR 1^5)%,
150 CREG1 = %ASSIGN (W_2,W_2 OR 1^6)%,
151 CREG2 = %ASSIGN (W_2,W_2 OR 1^7)%,
152 CREG3 = %ASSIGN (W_2,W_2 OR 1^8)%,
153 CREG4 = %ASSIGN (W_2,W_2 OR 1^9)%,
154 CREG5 = %ASSIGN (W_2,W_2 OR 1^10)%,
155 CREG6 = %ASSIGN (W_2,W_2 OR 1^11)%,
156 CREG7 = %ASSIGN (W_2,W_2 OR 1^12)%,
157 CREG8 = %ASSIGN (W_2,W_2 OR 1^13)%,
158 CADR1 = %ASSIGN (W_2,W_2 OR 1^14)%,
159 CADR2 = %ASSIGN (W_2,W_2 OR 1^15)%,
160 CADR3 = %ASSIGN (W_2,W_2 OR 1^16)%,
161 CADR4 = %ASSIGN (W_2,W_2 OR 1^17)%,
162 CADR5 = %ASSIGN (W_2,W_2 OR 1^18)%,
163 CADR6 = %ASSIGN (W_2,W_2 OR 1^19)%,
164 CADR7 = %ASSIGN (W_2,W_2 OR 1^20)%,
165 CADR8 = %ASSIGN (W_2,W_2 OR 1^21)%,
166 CADR9 = %ASSIGN (W_2,W_2 OR 1^22)%,
167 CADR10 = %ASSIGN (W_2,W_2 OR 1^23)%,
168 CADR11 = %ASSIGN (W_2,W_2 OR 1^24)%,
169 CRAM0 = %ASSIGN (W_2,W_2 OR 1^25)%,
170 CRAM1 = %ASSIGN (W_2,W_2 OR 1^26)%,
171 CRAM2 = %ASSIGN (W_2,W_2 OR 1^27)%,
172 CRAM3 = %ASSIGN (W_2,W_2 OR 1^28)%,
173 CRAM4 = %ASSIGN (W_2,W_2 OR 1^29)%,
174 CRAM5 = %ASSIGN (W_2,W_2 OR 1^30)%,
175 CRAM6 = %ASSIGN (W_2,W_2 OR 1^31)%,
176 CRAM7 = %ASSIGN (W_2,W_2 OR 1^32)%,
177 CRAM8 = %ASSIGN (W_2,W_2 OR 1^33)%,
178 CRAM9 = %ASSIGN (W_2,W_2 OR 1^34)%,
179 CRAM10 = %ASSIGN (W_2,W_2 OR 1^35)%,
180
181 !DEFINING NETWORKS TO CORRESPOND TO BITS FOR WORD W_3
182
183 CRAM11 = %ASSIGN (W_3,W_3 OR 1^0)%,
184 CRAM12 = %ASSIGN (W_3,W_3 OR 1^1)%,
185 CRAM13 = %ASSIGN (W_3,W_3 OR 1^2)%,
186 CRAM14 = %ASSIGN (W_3,W_3 OR 1^3)%,
187 CRAM15 = %ASSIGN (W_3,W_3 OR 1^4)%,
188 CRAM16 = %ASSIGN (W_3,W_3 OR 1^5)%,
189 CRAM17 = %ASSIGN (W_3,W_3 OR 1^6)%,
190 CRAM18 = %ASSIGN (W_3,W_3 OR 1^7)%,
191 CRAM19 = %ASSIGN (W_3,W_3 OR 1^8)%,
192 CRAM20 = %ASSIGN (W_3,W_3 OR 1^9)%,
193 CRAM21 = %ASSIGN (W_3,W_3 OR 1^10)%,
194 CRAM22 = %ASSIGN (W_3,W_3 OR 1^11)%,
195 CRAM23 = %ASSIGN (W_3,W_3 OR 1^12)%,
196 CRAM24 = %ASSIGN (W_3,W_3 OR 1^13)%,
197 CRAM25 = %ASSIGN (W_3,W_3 OR 1^14)%,
198 CRAM26 = %ASSIGN (W_3,W_3 OR 1^15)%,
199 CRAM27 = %ASSIGN (W_3,W_3 OR 1^16)%,
200 CRAM28 = %ASSIGN (W_3,W_3 OR 1^17)%,
201 CRAM29 = %ASSIGN (W_3,W_3 OR 1^18)%,
202 CRAM30 = %ASSIGN (W_3,W_3 OR 1^19)%,
203 CRAM31 = %ASSIGN (W_3,W_3 OR 1^20)%,
204 CRAM32 = %ASSIGN (W_3,W_3 OR 1^21)%,
205 CRAM33 = %ASSIGN (W_3,W_3 OR 1^22)%,
206 CRAM34 = %ASSIGN (W_3,W_3 OR 1^23)%,
207 CRAM35 = %ASSIGN (W_3,W_3 OR 1^24)%,
208 AMX1_00 = %ASSIGN (W_3,W_3 OR 1^25)%,
209 AMX2_00 = %ASSIGN (W_3,W_3 OR 1^26)%,
210 AMX3_00 = %ASSIGN (W_3,W_3 OR 1^27)%,
211 AMX4_00 = %ASSIGN (W_3,W_3 OR 1^28)%,
212 AMX5_00 = %ASSIGN (W_3,W_3 OR 1^29)%,
213 AMX6_00 = %ASSIGN (W_3,W_3 OR 1^30)%,
214 AMX7_00 = %ASSIGN (W_3,W_3 OR 1^31)%,
215 AMX8_00 = %ASSIGN (W_3,W_3 OR 1^32)%,
216 AMX9_00 = %ASSIGN (W_3,W_3 OR 1^33)%,
217 AMX10_00 = %ASSIGN (W_3,W_3 OR 1^34)%,
218 AMX11_00 = %ASSIGN (W_3,W_3 OR 1^35)%,
219
220 !DEFINING NETWORKS TO CORRESPOND TO BITS FOR WORD W_4
221
222 CRM0_0 = %ASSIGN (W_4,W_4 OR 1^0)%,
223 CRM0_1 = %ASSIGN (W_4,W_4 OR 1^1)%,
224 CRM0_2 = %ASSIGN (W_4,W_4 OR 1^2)%,
225 CRM0_3 = %ASSIGN (W_4,W_4 OR 1^3)%,
226 CRM0_4 = %ASSIGN (W_4,W_4 OR 1^4)%,
227 CRM0_5 = %ASSIGN (W_4,W_4 OR 1^5)%,
228 CRM0_6 = %ASSIGN (W_4,W_4 OR 1^6)%,
229 CRM0_7 = %ASSIGN (W_4,W_4 OR 1^7)%,
230 CRM0_8 = %ASSIGN (W_4,W_4 OR 1^8)%,
231 CRM0_9 = %ASSIGN (W_4,W_4 OR 1^9)%,
232 CRM0_10 = %ASSIGN (W_4,W_4 OR 1^10)%,
233 CRM0_11 = %ASSIGN (W_4,W_4 OR 1^11)%,
234 CRM0_12 = %ASSIGN (W_4,W_4 OR 1^12)%,
235 CRM0_13 = %ASSIGN (W_4,W_4 OR 1^13)%,
236 CRM0_14 = %ASSIGN (W_4,W_4 OR 1^14)%,
237 CRM0_15 = %ASSIGN (W_4,W_4 OR 1^15)%,
238 CRM0_16 = %ASSIGN (W_4,W_4 OR 1^16)%,
239 CRM0_17 = %ASSIGN (W_4,W_4 OR 1^17)%,
240 CRM0_18 = %ASSIGN (W_4,W_4 OR 1^18)%,
241 CRM0_19 = %ASSIGN (W_4,W_4 OR 1^19)%,
242 CRM0_20 = %ASSIGN (W_4,W_4 OR 1^20)%,
243 CRM0_21 = %ASSIGN (W_4,W_4 OR 1^21)%,
244 CRM0_22 = %ASSIGN (W_4,W_4 OR 1^22)%,
245 CRM0_23 = %ASSIGN (W_4,W_4 OR 1^23)%,
246 CRM0_24 = %ASSIGN (W_4,W_4 OR 1^24)%,
247 CRM0_25 = %ASSIGN (W_4,W_4 OR 1^25)%,
248 CRM0_26 = %ASSIGN (W_4,W_4 OR 1^26)%,
249 CRM0_27 = %ASSIGN (W_4,W_4 OR 1^27)%,
250 CRM0_28 = %ASSIGN (W_4,W_4 OR 1^28)%,
251 CRM0_29 = %ASSIGN (W_4,W_4 OR 1^29)%,
252 CRM0_30 = %ASSIGN (W_4,W_4 OR 1^30)%,
253 CRM0_31 = %ASSIGN (W_4,W_4 OR 1^31)%,
254 CRM0_32 = %ASSIGN(W_4,W_4 OR 1^32)%,
255 CRM0_33 = %ASSIGN (W_4,W_4 OR 1^33)%,
256 CRM0_34 = %ASSIGN(W_4,W_4 OR 1^34)%,
257 CRM0_35 = %ASSIGN(W_4,W_4 OR 1^35)%,
258 !WORD BEING GENERATED
259 NTWK = W_0,W_1,W_2,W_3,W_4
260 %ASSIGN (W_0,0)
261 %ASSIGN (W_1,0)
262 %ASSIGN (W_2,0)
263 %ASSIGN (W_3,0)
264 %ASSIGN (W_4,0)%;
265
266 COMPILETIME
267 W_0 = 0,
268 W_1 = 0,
269 W_2 = 0,
270 W_3 = 0,
271 W_4 = 0;
272
273
274 BIND
275 DIAG_MUX = UPAZ('CRA4: DIAGNOSTIC READ MUXS'),
276 DIAG_FN = UPAZ('CRA4: DIAGNOSTIC FUNCTION DECODER'),
277 CWRT_DEC = UPAZ('CRA4: CRAM WRITE DECODER'),
278 CRM0_NAME = UPAZ('CRA8: RAMS FOR CRAM BIT 0'),
279 CRM1_NAME = UPAZ('CRA8: RAMS FOR CRAM BIT 1'),
280 CRM2_NAME = UPAZ('CRA8: RAMS FOR CRAM BIT 2'),
281 CRM3_NAME = UPAZ('CRA8: RAMS FOR CRAM BIT 3'),
282 CRM4_NAME = UPAZ('CRA8: RAMS FOR CRAM BIT 4'),
283 CRM5_NAME = UPAZ('CRA8: RAMS FOR CRAM BIT 5'),
284 CRM6_NAME = UPAZ('CRA8: RAMS FOR CRAM BIT 6'),
285 CRM7_NAME = UPAZ('CRA8: RAMS FOR CRAM BIT 7'),
286 CRM8_NAME = UPAZ('CRA8: RAMS FOR CRAM BIT 8'),
287 CRM9_NAME = UPAZ('CRA8: RAMS FOR CRAM BIT 9'),
288 CRM10_NAME = UPAZ('CRA8: RAMS FOR CRAM BIT 10'),
289 CRM11_NAME = UPAZ('CRA8: RAMS FOR CRAM BIT 11'),
290 CRM12_NAME = UPAZ('CRA8: RAMS FOR CRAM BIT 12'),
291 CRM13_NAME = UPAZ('CRA8: RAMS FOR CRAM BIT 13'),
292 CRM14_NAME = UPAZ('CRA8: RAMS FOR CRAM BIT 14'),
293 CRM15_NAME = UPAZ('CRA8: RAMS FOR CRAM BIT 15'),
294 CRM16_NAME = UPAZ('CRA8: RAMS FOR CRAM BIT 16'),
295 CRM17_NAME = UPAZ('CRA8: RAMS FOR CRAM BIT 17'),
296 CRM18_NAME = UPAZ('CRA9: RAMS FOR CRAM BIT 18'),
297 CRM19_NAME = UPAZ('CRA9: RAMS FOR CRAM BIT 19'),
298 CRM20_NAME = UPAZ('CRA9: RAMS FOR CRAM BIT 20'),
299 CRM21_NAME = UPAZ('CRA9: RAMS FOR CRAM BIT 21'),
300 CRM22_NAME = UPAZ('CRA9: RAMS FOR CRAM BIT 22'),
301 CRM23_NAME = UPAZ('CRA9: RAMS FOR CRAM BIT 23'),
302 CRM24_NAME = UPAZ('CRA9: RAMS FOR CRAM BIT 24'),
303 CRM25_NAME = UPAZ('CRA9: RAMS FOR CRAM BIT 25'),
304 CRM26_NAME = UPAZ('CRA9: RAMS FOR CRAM BIT 26'),
305 CRM27_NAME = UPAZ('CRA9: RAMS FOR CRAM BIT 27'),
306 CRM28_NAME = UPAZ('CRA9: RAMS FOR CRAM BIT 28'),
307 CRM29_NAME = UPAZ('CRA9: RAMS FOR CRAM BIT 29'),
308 CRM30_NAME = UPAZ('CRA9: RAMS FOR CRAM BIT 30'),
309 CRM31_NAME = UPAZ('CRA9: RAMS FOR CRAM BIT 31'),
310 CRM32_NAME = UPAZ('CRA9: RAMS FOR CRAM BIT 32'),
311 CRM33_NAME = UPAZ('CRA9: RAMS FOR CRAM BIT 33'),
312 CRM34_NAME = UPAZ('CRA9: RAMS FOR CRAM BIT 34'),
313 CRM35_NAME = UPAZ('CRA9: RAMS FOR CRAM BIT 35');
314
315 GLOBAL BIND
316 NET_NAMES = UPLIT(UPAZ('CRA1: NEXT CRAM ADDRESS MUXS'),
317 UPAZ('CRA1: NEXT CRAM ADDRESS MUX FOR BITS 0 AND 1'),
318 UPAZ('CRA1: NEXT CRAM ADDRESS MUX FOR BITS 2 AND 3'),
319 UPAZ('CRA1: NEXT CRAM ADDRESS MUX FOR BITS 4 AND 5'),
320 UPAZ('CRA1: NEXT CRAM ADDRESS MUX FOR BITS 6 AND 7'),
321 UPAZ('CRA1: NEXT CRAM ADDRESS MUX FOR BIT 8'),
322 UPAZ('CRA1: NEXT CRAM ADDRESS MUX FOR BIT 9'),
323 UPAZ('CRA1: NEXT CRAM ADDRESS MUX FOR BIT 10'),
324 UPAZ('CRA1: NEXT CRAM ADDRESS MUX FOR BIT 11'),
325 UPAZ('CRA2: "STACK WRITE" SIGNAL'),
326 UPAZ('CRA2: "T CLK B" SIGNAL'),
327 UPAZ('CRA2: "T CLK C" SIGNAL'),
328 UPAZ('CRA2: "CLK D" SIGNAL'),
329 UPAZ('CRA2: "CLK E" SIGNAL'),
330 UPAZ('CRA2: "CLK F" SIGNAL'),
331 UPAZ('CRA2: "CLK H" SIGNAL'),
332 UPAZ('CRA2: "CLK J" SIGNAL'),
333 UPAZ('CRA2: CLOCK ENABLE SIGNAL'),
334 UPAZ('CRA2: "SYNC H" SIGNAL'),
335 UPAZ('CRA2: "PAGE FAIL" SIGNAL BUFFERS'),
336 UPAZ('CRA2: "DISP & SKIP EN" SIGNAL'),
337 UPAZ('CRA2: "FIRST CYCLE" SIGNAL'),
338 UPAZ('CRA2: "I/O LATCH" SIGNAL'),
339 UPAZ('CRA2: "SYNC L" SIGNAL'),
340 UPAZ('CRA2: "RETURN" SIGNAL'),
341 UPAZ('CRA2: "CALL OR RETURN" SIGNAL'),
342 UPAZ('CRA2: "RESET" SIGNAL'),
343 UPAZ('CRA2: "STACK RESET" SIGNAL'),
344 UPAZ('CRA2: SKIP 10 LATCH AND DECODER'),
345 UPAZ('CRA2: SPEC 10 DECODER'),
346 UPAZ('CRA2: AREAD MUX'),
347 UPAZ('CRA2: NICOND DISPATCH PRIORITY ENCODER'),
348 UPAZ('CRA2: "TRAP CYCLE" SIGNAL LATCH'),
349 UPAZ('CRA1: NEXT CRAM ADDRESS MUX FOR BITS 0 AND 1'),
350 UPAZ('CRA2: "ADR 11" SIGNAL BUFFERS'),
351 UPAZ('CRA8,9: CRAMS'),
352
353
354 !NETWORKS NAMES FOR NETWORKS 36-71 (WHICH ARE IN W_1)
355
356 UPAZ('CRA3: THE SUBROUTINE STACK RAMS'),
357 UPAZ('CRA3: THE STACK ADDRESS CONTROL NETWORK'),
358 UPAZ('CRA3: THE LATCH FOR BITS 0-3 OF "SBR RET"'),
359 UPAZ('CRA3: THE LATCH FOR BITS 4-7 OF "SBR RET"'),
360 UPAZ('CRA3: THE LATCH FOR BITS 8-11 OF "SBR RET"'),
361 UPAZ('CRA3: RAM FOR BITS 0-3 OF SUBROUTINE STACK'),
362 UPAZ('CRA3: RAM FOR BITS 4-7 OF SUBROUTINE STACK'),
363 UPAZ('CRA3: RAM FOR BITS 8-11 OF SUBROUTINE STACK'),
364 UPAZ('CRA3: THE LATCH FOR BITS 0-3 OF "CURR LOC"'),
365 UPAZ('CRA3: THE LATCH FOR BITS 4-7 OF "CURR LOC"'),
366 UPAZ('CRA3: THE LATCH FOR BITS 8-11 OF "CURR LOC"'),
367 DIAG_MUX,
368 DIAG_MUX,
369 DIAG_MUX,
370 DIAG_MUX,
371 DIAG_MUX,
372 DIAG_MUX,
373 DIAG_MUX,
374 DIAG_MUX,
375 DIAG_MUX,
376 DIAG_FN,
377 DIAG_FN,
378 DIAG_FN,
379 DIAG_FN,
380 DIAG_FN,
381 DIAG_FN,
382 DIAG_FN,
383 DIAG_FN,
384 DIAG_FN,
385 CWRT_DEC,
386 CWRT_DEC,
387 CWRT_DEC,
388 CWRT_DEC,
389 CWRT_DEC,
390 CWRT_DEC,
391 UPAZ('CRA5: "DIAG ADR" LATCHES'),
392
393 !NETWORK NAMES FOR NETWORKS 72-107 (WHICH ARE IN W_2)
394
395 UPAZ('CRA5: LATCH FOR BITS 0-3 OF "DIAG ADR"'),
396 UPAZ('CRA5: LATCH FOR BITS 4-7 OF "DIAG ADR"'),
397 UPAZ('CRA5: LATCH FOR BITS 8-11 OF "DIAG ADR"'),
398 UPAZ('CRA5: "BUS DATA" BUFFERS'),
399 UPAZ('CRA5: KS10 BUS TRANSCEIVERS'),
400 UPAZ('CRA6: CRAM PARITY DETECTION NETWORK'),
401 UPAZ('CRA6: LATCH FOR CRAM CONTROL BITS 0-5'),
402 UPAZ('CRA6: LATCH FOR CRAM CONTROL BITS 6-11'),
403 UPAZ('CRA6: LATCH FOR CRAM CONTROL BITS 12,18,24,30'),
404 UPAZ('CRA6: LATCH FOR CRAM CONTROL BITS 13,19,25,31'),
405 UPAZ('CRA6: LATCH FOR CRAM CONTROL BITS 14,20,26,32'),
406 UPAZ('CRA6: LATCH FOR CRAM CONTROL BITS 15,21,27,33'),
407 UPAZ('CRA6: LATCH FOR CRAM CONTROL BITS 16,22,28,34'),
408 UPAZ('CRA6: LATCH FOR CRAM CONTROL BITS 17,23,29,35'),
409 UPAZ('CRA7: DRIVERS FOR CRAM ADDRESS BIT 1'),
410 UPAZ('CRA7: DRIVERS FOR CRAM ADDRESS BIT 2'),
411 UPAZ('CRA7: DRIVERS FOR CRAM ADDRESS BIT 3'),
412 UPAZ('CRA7: DRIVERS FOR CRAM ADDRESS BIT 4'),
413 UPAZ('CRA7: DRIVERS FOR CRAM ADDRESS BIT 5'),
414 UPAZ('CRA7: DRIVERS FOR CRAM ADDRESS BIT 6'),
415 UPAZ('CRA7: DRIVERS FOR CRAM ADDRESS BIT 7'),
416 UPAZ('CRA7: DRIVERS FOR CRAM ADDRESS BIT 8'),
417 UPAZ('CRA7: DRIVERS FOR CRAM ADDRESS BIT 9'),
418 UPAZ('CRA7: DRIVERS FOR CRAM ADDRESS BIT 10'),
419 UPAZ('CRA7: DRIVERS FOR CRAM ADDRESS BIT 11'),
420 CRM0_NAME,
421 CRM1_NAME,
422 CRM2_NAME,
423 CRM3_NAME,
424 CRM4_NAME,
425 CRM5_NAME,
426 CRM6_NAME,
427 CRM7_NAME,
428 CRM8_NAME,
429 CRM9_NAME,
430 CRM10_NAME,
431
432 !NETWORK NAMES FOR NETWORKS 108-143 (WHICH ARE IN W_3)
433
434 CRM11_NAME,
435 CRM12_NAME,
436 CRM13_NAME,
437 CRM14_NAME,
438 CRM15_NAME,
439 CRM16_NAME,
440 CRM17_NAME,
441 CRM18_NAME,
442 CRM19_NAME,
443 CRM20_NAME,
444 CRM21_NAME,
445 CRM22_NAME,
446 CRM23_NAME,
447 CRM24_NAME,
448 CRM25_NAME,
449 CRM26_NAME,
450 CRM27_NAME,
451 CRM28_NAME,
452 CRM29_NAME,
453 CRM30_NAME,
454 CRM31_NAME,
455 CRM32_NAME,
456 CRM33_NAME,
457 CRM34_NAME,
458 CRM35_NAME,
459 UPAZ('CRA1: NEXT CRAM ADDRESS MUX FOR BITS 0 AND 1'),
460 UPAZ('CRA1: NEXT CRAM ADDRESS MUX FOR BITS 2 AND 3'),
461 UPAZ('CRA1: NEXT CRAM ADDRESS MUX FOR BITS 2 AND 3'),
462 UPAZ('CRA1: NEXT CRAM ADDRESS MUX FOR BITS 4 AND 5'),
463 UPAZ('CRA1: NEXT CRAM ADDRESS MUX FOR BITS 4 AND 5'),
464 UPAZ('CRA1: NEXT CRAM ADDRESS MUX FOR BITS 6 AND 7'),
465 UPAZ('CRA1: NEXT CRAM ADDRESS MUX FOR BITS 6 AND 7'),
466 UPAZ('CRA1: NEXT CRAM ADDRESS MUX FOR BIT 8'),
467 UPAZ('CRA1: NEXT CRAM ADDRESS MUX FOR BIT 9'),
468 UPAZ('CRA1: NEXT CRAM ADDRESS MUX FOR BIT 10'),
469 UPAZ('CRA1: NEXT CRAM ADDRESS MUX FOR BIT 11'),
470
471 !NETWORK NAMES FOR NETWORKS 144-179 (WHICH ARE IN W_4)
472
473 CRM0_NAME,
474 CRM1_NAME,
475 CRM2_NAME,
476 CRM3_NAME,
477 CRM4_NAME,
478 CRM5_NAME,
479 CRM6_NAME,
480 CRM7_NAME,
481 CRM8_NAME,
482 CRM9_NAME,
483 CRM10_NAME,
484 CRM11_NAME,
485 CRM12_NAME,
486 CRM13_NAME,
487 CRM14_NAME,
488 CRM15_NAME,
489 CRM16_NAME,
490 CRM17_NAME,
491 CRM18_NAME,
492 CRM19_NAME,
493 CRM20_NAME,
494 CRM21_NAME,
495 CRM22_NAME,
496 CRM23_NAME,
497 CRM24_NAME,
498 CRM25_NAME,
499 CRM26_NAME,
500 CRM27_NAME,
501 CRM28_NAME,
502 CRM29_NAME,
503 CRM30_NAME,
504 CRM31_NAME,
505 CRM32_NAME,
506 CRM33_NAME,
507 CRM34_NAME,
508 CRM35_NAME);
509
510 !
511 ! OWN STORAGE:
512 !
513
514 !
515 ! EXTERNAL REFERENCES:
516 !
517
518
519 BIND T1_E1 = UPLIT(DMX7 BUSBUF XCVRS NTWK);
520 BIND T1_E2 = UPLIT(DFN7 NTWK);
521
522 BIND T1_ES = PLIT( T1_E1,
523 T1_E2);
524
525
526 BIND T2_E1 = UPLIT(XCVRS BUSBUF DMX11 NTWK);
527 BIND T2_E2 = UPLIT(XCVRS BUSBUF NTWK);
528 BIND T2_E3 = UPLIT(TCLKC DFN11 NTWK);
529 BIND T2_NE1 = UPLIT(XCVRS BUSBUF DMX11 TCLKC DFN11 NTWK);
530
531 BIND T2_ES = PLIT( T2_E1,
532 T2_E2,
533 T2_E3);
534 BIND T2_NES = PLIT( T2_NE1);
535
536
537 BIND T3_E1 = UPLIT(DMX0 CRM0_11 CREG2 NTWK);
538 BIND T3_E2 = UPLIT(DMX0 CRM0_10 CREG2 NTWK);
539 BIND T3_E3 = UPLIT(DMX0 CRM0_9 CREG2 NTWK);
540 BIND T3_E4 = UPLIT(DMX0 CRM0_8 CREG2 NTWK);
541 BIND T3_E5 = UPLIT(DMX0 CRM0_7 CREG2 NTWK);
542 BIND T3_E6 = UPLIT(DMX0 CRM0_6 CREG2 NTWK);
543 BIND T3_E7 = UPLIT(DMX0 CRM0_5 CREG1 NTWK);
544 BIND T3_E8 = UPLIT(DMX0 CRM0_4 CREG1 NTWK);
545 BIND T3_E9 = UPLIT(DMX0 CRM0_3 CREG1 NTWK);
546 BIND T3_E10 = UPLIT(DMX0 CRM0_2 CREG1 NTWK);
547 BIND T3_E11 = UPLIT(DMX0 CRM0_1 CREG1 NTWK);
548 BIND T3_E12 = UPLIT(DMX0 CRM0_0 CREG1 NTWK);
549 BIND T3_E13 = UPLIT(CREG1 CWRT0_5 NTWK);
550 BIND T3_E14 = UPLIT(CREG2 CWRT6_11 NTWK);
551 BIND T3_E15 = UPLIT(DFN0 CLKE CLKEN RESET NTWK);
552 BIND T3_E16 = UPLIT(DFN0 NTWK);
553 BIND T3_NE1 = UPLIT(DMX0 CWRT0_5 CWRT6_11 CLKE CLKEN DFN0 NTWK);
554
555 BIND T3_ES = PLIT( T3_E1,
556 T3_E2,
557 T3_E3,
558 T3_E4,
559 T3_E5,
560 T3_E6,
561 T3_E7,
562 T3_E8,
563 T3_E9,
564 T3_E10,
565 T3_E11,
566 T3_E12,
567 T3_E13,
568 T3_E14,
569 T3_E15,
570 T3_E16);
571 BIND T3_NES = PLIT( T3_NE1);
572
573
574 BIND T4_E1 = UPLIT(DMX4 CRM0_23 CREG8 NTWK);
575 BIND T4_E2 = UPLIT(DMX4 CRM0_22 CREG7 NTWK);
576 BIND T4_E3 = UPLIT(DMX4 CRM0_21 CREG6 NTWK);
577 BIND T4_E4 = UPLIT(DMX4 CRM0_20 CREG5 NTWK);
578 BIND T4_E5 = UPLIT(DMX4 CRM0_19 CREG4 NTWK);
579 BIND T4_E6 = UPLIT(DMX4 CRM0_18 CREG3 NTWK);
580 BIND T4_E7 = UPLIT(DMX4 CRM0_17 CREG8 NTWK);
581 BIND T4_E8 = UPLIT(DMX4 CRM0_16 CREG7 NTWK);
582 BIND T4_E9 = UPLIT(DMX4 CRM0_15 CREG6 NTWK);
583 BIND T4_E10 = UPLIT(DMX4 CRM0_14 CREG5 NTWK);
584 BIND T4_E11 = UPLIT(DMX4 CRM0_13 CREG4 NTWK);
585 BIND T4_E12 = UPLIT(DMX4 CRM0_12 CREG3 NTWK);
586 BIND T4_E13 = UPLIT(CREG8 NTWK);
587 BIND T4_E14 = UPLIT(CREG7 NTWK);
588 BIND T4_E15 = UPLIT(CREG6 NTWK);
589 BIND T4_E16 = UPLIT(CREG5 NTWK);
590 BIND T4_E17 = UPLIT(CREG4 NTWK);
591 BIND T4_E18 = UPLIT(CREG3 NTWK);
592 BIND T4_E19 = UPLIT(CWRT12_17 NTWK);
593 BIND T4_E20 = UPLIT(CWRT18_23 NTWK);
594 BIND T4_E21 = UPLIT(CLKJ SYNCH NTWK);
595 BIND T4_E22 = UPLIT(CLKH SYNCH NTWK);
596 BIND T4_E23 = UPLIT(SYNCH DFN1 DFN4 RESET NTWK);
597 BIND T4_E24 = UPLIT(DFN1 DFN4 NTWK);
598 BIND T4_NE1 = UPLIT(DFN1 DMX4 DFN4 CLKJ SYNCH CLKH SYNCH CWRT18_23 CWRT12_17 NTWK);
599
600 BIND T4_ES = PLIT( T4_E1,
601 T4_E2,
602 T4_E3,
603 T4_E4,
604 T4_E5,
605 T4_E6,
606 T4_E7,
607 T4_E8,
608 T4_E9,
609 T4_E10,
610 T4_E11,
611 T4_E12,
612 T4_E13,
613 T4_E14,
614 T4_E15,
615 T4_E16,
616 T4_E17,
617 T4_E18,
618 T4_E19,
619 T4_E20,
620 T4_E21,
621 T4_E22,
622 T4_E23,
623 T4_E24);
624 BIND T4_NES = PLIT( T4_NE1);
625
626
627 BIND T5_E1 = UPLIT(DMX5 CRM0_35 CREG8 NTWK);
628 BIND T5_E2 = UPLIT(DMX5 CRM0_34 CREG7 NTWK);
629 BIND T5_E3 = UPLIT(DMX5 CRM0_33 CREG6 NTWK);
630 BIND T5_E4 = UPLIT(DMX5 CRM0_32 CREG5 NTWK);
631 BIND T5_E5 = UPLIT(DMX5 CRM0_31 CREG4 NTWK);
632 BIND T5_E6 = UPLIT(DMX5 CRM0_30 CREG3 NTWK);
633 BIND T5_E7 = UPLIT(DMX5 CRM0_29 CREG8 NTWK);
634 BIND T5_E8 = UPLIT(DMX5 CRM0_28 CREG7 NTWK);
635 BIND T5_E9 = UPLIT(DMX5 CRM0_27 CREG6 NTWK);
636 BIND T5_E10 = UPLIT(DMX5 CRM0_26 CREG5 NTWK);
637 BIND T5_E11 = UPLIT(DMX5 CRM0_25 CREG4 NTWK);
638 BIND T5_E12 = UPLIT(DMX5 CRM0_24 CREG3 NTWK);
639 BIND T5_E13 = UPLIT(CWRT24_29 NTWK);
640 BIND T5_E14 = UPLIT(CWRT30_35 NTWK);
641 BIND T5_E15 = UPLIT(SYNCH RESET DFN2 DFN5 NTWK);
642 BIND T5_E16 = UPLIT(DFN2 DFN5 NTWK);
643 BIND T5_NE1 = UPLIT(DFN2 DFN5 DMX5 CWRT24_29 CWRT30_35 NTWK);
644
645 BIND T5_ES = PLIT( T5_E1,
646 T5_E2,
647 T5_E3,
648 T5_E4,
649 T5_E5,
650 T5_E6,
651 T5_E7,
652 T5_E8,
653 T5_E9,
654 T5_E10,
655 T5_E11,
656 T5_E12,
657 T5_E13,
658 T5_E14,
659 T5_E15,
660 T5_E16);
661 BIND T5_NES = PLIT( T5_NE1);
662
663
664 BIND T6_E1 = UPLIT(DMX6 CRM0_35 CREG8 NTWK);
665 BIND T6_E2 = UPLIT(DMX6 CRM0_34 CREG7 NTWK);
666 BIND T6_E3 = UPLIT(DMX6 CRM0_33 CREG6 NTWK);
667 BIND T6_E4 = UPLIT(DMX6 CRM0_32 CREG5 NTWK);
668 BIND T6_E5 = UPLIT(DMX6 CRM0_31 CREG4 NTWK);
669 BIND T6_E6 = UPLIT(DMX6 CRM0_30 CREG3 NTWK);
670 BIND T6_E7 = UPLIT(DMX6 CRM0_29 CREG8 NTWK);
671 BIND T6_E8 = UPLIT(DMX6 CRM0_28 CREG7 NTWK);
672 BIND T6_E9 = UPLIT(DMX6 CRM0_27 CREG6 NTWK);
673 BIND T6_E10 = UPLIT(DMX6 CRM0_26 CREG5 NTWK);
674 BIND T6_E11 = UPLIT(DMX6 CRM0_25 CREG4 NTWK);
675 BIND T6_E12 = UPLIT(DMX6 CRM0_24 CREG3 NTWK);
676 BIND T6_E13 = UPLIT(DFN2 DFN6 NTWK);
677 BIND T6_NE1 = UPLIT(DFN2 DFN6 DMX6 NTWK);
678
679 BIND T6_ES = PLIT( T6_E1,
680 T6_E2,
681 T6_E3,
682 T6_E4,
683 T6_E5,
684 T6_E6,
685 T6_E7,
686 T6_E8,
687 T6_E9,
688 T6_E10,
689 T6_E11,
690 T6_E12,
691 T6_E13);
692 BIND T6_NES = PLIT( T6_NE1);
693
694
695 BIND T7_E1 = UPLIT(DMX0 CREG1 NTWK);
696 BIND T7_E2 = UPLIT(DMX0 CREG2 NTWK);
697 BIND T7_E3 = UPLIT(DMX0 RESET NTWK);
698
699 BIND T7_ES = PLIT( T7_E1,
700 T7_E2,
701 T7_E3);
702
703
704 BIND T8_E1 = UPLIT(DMX4 CREG8 NTWK);
705 BIND T8_E2 = UPLIT(DMX4 CREG7 NTWK);
706 BIND T8_E3 = UPLIT(DMX4 CREG6 NTWK);
707 BIND T8_E4 = UPLIT(DMX4 CREG5 NTWK);
708 BIND T8_E5 = UPLIT(DMX4 CREG4 NTWK);
709 BIND T8_E6 = UPLIT(DMX4 CREG3 NTWK);
710 BIND T8_E7 = UPLIT(RESET NTWK);
711
712 BIND T8_ES = PLIT( T8_E1,
713 T8_E2,
714 T8_E3,
715 T8_E4,
716 T8_E5,
717 T8_E6,
718 T8_E7);
719
720
721 BIND T9_E1 = UPLIT(DMX5 CREG8 NTWK);
722 BIND T9_E2 = UPLIT(DMX5 CREG7 NTWK);
723 BIND T9_E3 = UPLIT(DMX5 CREG6 NTWK);
724 BIND T9_E4 = UPLIT(DMX5 CREG5 NTWK);
725 BIND T9_E5 = UPLIT(DMX5 CREG4 NTWK);
726 BIND T9_E6 = UPLIT(DMX5 CREG3 NTWK);
727 BIND T9_E7 = UPLIT(RESET NTWK);
728 BIND T9_E8 = UPLIT(DMX6 CREG8 NTWK);
729 BIND T9_E9 = UPLIT(DMX6 CREG7 NTWK);
730 BIND T9_E10 = UPLIT(DMX6 CREG6 NTWK);
731 BIND T9_E11 = UPLIT(DMX6 CREG5 NTWK);
732 BIND T9_E12 = UPLIT(DMX6 CREG4 NTWK);
733 BIND T9_E13 = UPLIT(DMX6 CREG3 NTWK);
734 BIND T9_E14 = UPLIT(RESET NTWK);
735
736 BIND T9_ES = PLIT( T9_E1,
737 T9_E2,
738 T9_E3,
739 T9_E4,
740 T9_E5,
741 T9_E6,
742 T9_E7,
743 T9_E8,
744 T9_E9,
745 T9_E10,
746 T9_E11,
747 T9_E12,
748 T9_E13,
749 T9_E14);
750
751
752 BIND T10_E1 = UPLIT(DADR3 AMX11_00 DMX1 SKIP10 NTWK);
753 BIND T10_E2 = UPLIT(DADR3 AMX10_00 DMX1 NTWK);
754 BIND T10_E3 = UPLIT(DADR3 AMX9_00 DMX1 NTWK);
755 BIND T10_E4 = UPLIT(DADR3 AMX8_00 DMX1 NTWK);
756 BIND T10_E5 = UPLIT(DADR2 AMX7_00 DMX1 NTWK);
757 BIND T10_E6 = UPLIT(DADR2 AMX6_00 DMX1 NTWK);
758 BIND T10_E7 = UPLIT(DADR2 AMX5_00 DMX1 NTWK);
759 BIND T10_E8 = UPLIT(DADR2 AMX4_00 DMX1 NTWK);
760 BIND T10_E9 = UPLIT(DADR1 AMX3_00 DMX1 NTWK);
761 BIND T10_E10 = UPLIT(DADR1 AMX2_00 DMX1 NTWK);
762 BIND T10_E11 = UPLIT(DADR1 AMX1_00 DMX1 NTWK);
763 BIND T10_E12 = UPLIT(DADR1 AMX0_00 DMX1 NTWK);
764 BIND T10_E13 = UPLIT(DADR3 NTWK);
765 BIND T10_E14 = UPLIT(DADR2 NTWK);
766 BIND T10_E15 = UPLIT(DADR1 NTWK);
767 BIND T10_E16 = UPLIT(PFBUF NTWK);
768 BIND T10_E17 = UPLIT(DADR AMX DFN1 NTWK);
769 BIND T10_NE1 = UPLIT(DADR DADR1 DADR2 DADR3 AMX_00 DMX1 DFN1 NTWK);
770
771 BIND T10_ES = PLIT( T10_E1,
772 T10_E2,
773 T10_E3,
774 T10_E4,
775 T10_E5,
776 T10_E6,
777 T10_E7,
778 T10_E8,
779 T10_E9,
780 T10_E10,
781 T10_E11,
782 T10_E12,
783 T10_E13,
784 T10_E14,
785 T10_E15,
786 T10_E16,
787 T10_E17);
788 BIND T10_NES = PLIT( T10_NE1);
789
790
791 BIND T11_E1 = UPLIT(DADR3 CLOC3 AMX11_00 DMX3 SKIP10 NTWK);
792 BIND T11_E2 = UPLIT(DADR3 CLOC3 AMX10_00 DMX3 NTWK);
793 BIND T11_E3 = UPLIT(DADR3 CLOC3 AMX9_00 DMX3 NTWK);
794 BIND T11_E4 = UPLIT(DADR3 CLOC3 AMX8_00 DMX3 NTWK);
795 BIND T11_E5 = UPLIT(DADR2 CLOC2 AMX7_00 DMX3 NTWK);
796 BIND T11_E6 = UPLIT(DADR2 CLOC2 AMX6_00 DMX3 NTWK);
797 BIND T11_E7 = UPLIT(DADR2 CLOC2 AMX5_00 DMX3 NTWK);
798 BIND T11_E8 = UPLIT(DADR2 CLOC2 AMX4_00 DMX3 NTWK);
799 BIND T11_E9 = UPLIT(DADR1 CLOC1 AMX3_00 DMX3 NTWK);
800 BIND T11_E10 = UPLIT(DADR1 CLOC1 AMX2_00 DMX3 NTWK);
801 BIND T11_E11 = UPLIT(DADR1 CLOC1 AMX1_00 DMX3 NTWK);
802 BIND T11_E12 = UPLIT(DADR1 CLOC1 AMX0_00 DMX3 NTWK);
803 BIND T11_E13 = UPLIT(CLKF CLKEN DADR3 CLOC3 NTWK);
804 BIND T11_E14 = UPLIT(CLKD CLKEN DADR2 CLOC2 NTWK);
805 BIND T11_E15 = UPLIT(CLKE CLKEN DADR1 CLOC1 NTWK);
806 BIND T11_E16 = UPLIT(DFN3 NTWK);
807 BIND T11_NE1 = UPLIT(DADR1 DADR2 DADR3 AMX_00 DMX3 CLOC1 CLOC2 CLOC3 DFN3 NTWK);
808
809 BIND T11_ES = PLIT( T11_E1,
810 T11_E2,
811 T11_E3,
812 T11_E4,
813 T11_E5,
814 T11_E6,
815 T11_E7,
816 T11_E8,
817 T11_E9,
818 T11_E10,
819 T11_E11,
820 T11_E12,
821 T11_E13,
822 T11_E14,
823 T11_E15,
824 T11_E16);
825 BIND T11_NES = PLIT( T11_NE1);
826
827
828 BIND T12_E1 = UPLIT(AMX11 SKIP10 NTWK);
829 BIND T12_E2 = UPLIT(AMX10 NTWK);
830 BIND T12_E3 = UPLIT(AMX9 NTWK);
831 BIND T12_E4 = UPLIT(AMX8 NTWK);
832 BIND T12_E5 = UPLIT(AMX6_7 NTWK);
833 BIND T12_E6 = UPLIT(AMX6_7 NTWK);
834 BIND T12_E7 = UPLIT(AMX4_5 NTWK);
835 BIND T12_E8 = UPLIT(AMX4_5 NTWK);
836 BIND T12_E9 = UPLIT(AMX2_3 NTWK);
837 BIND T12_E10 = UPLIT(AMX2_3 NTWK);
838 BIND T12_E11 = UPLIT(AMX0_1 NTWK);
839 BIND T12_E12 = UPLIT(AMX0_1 NTWK);
840 BIND T12_E13 = UPLIT(AMX11 SKIP10 NTWK);
841 BIND T12_E14 = UPLIT(AMX10 NTWK);
842 BIND T12_E15 = UPLIT(AMX9 NTWK);
843 BIND T12_E16 = UPLIT(AMX8 NTWK);
844 BIND T12_E17 = UPLIT(AMX6_7 NTWK);
845 BIND T12_E18 = UPLIT(AMX6_7 NTWK);
846 BIND T12_E19 = UPLIT(AMX4_5 NTWK);
847 BIND T12_E20 = UPLIT(AMX4_5 NTWK);
848 BIND T12_E21 = UPLIT(AMX2_3 NTWK);
849 BIND T12_E22 = UPLIT(AMX2_3 NTWK);
850 BIND T12_E23 = UPLIT(AMX0_1 NTWK);
851 BIND T12_E24 = UPLIT(AMX0_1 NTWK);
852
853 BIND T12_ES = PLIT( T12_E1,
854 T12_E2,
855 T12_E3,
856 T12_E4,
857 T12_E5,
858 T12_E6,
859 T12_E7,
860 T12_E8,
861 T12_E9,
862 T12_E10,
863 T12_E11,
864 T12_E12,
865 T12_E13,
866 T12_E14,
867 T12_E15,
868 T12_E16,
869 T12_E17,
870 T12_E18,
871 T12_E19,
872 T12_E20,
873 T12_E21,
874 T12_E22,
875 T12_E23,
876 T12_E24);
877
878
879 BIND T13_E1 = UPLIT(CRAM35 NTWK);
880 BIND T13_E2 = UPLIT(CRAM34 NTWK);
881 BIND T13_E3 = UPLIT(CRAM33 NTWK);
882 BIND T13_E4 = UPLIT(CRAM32 NTWK);
883 BIND T13_E5 = UPLIT(CRAM31 NTWK);
884 BIND T13_E6 = UPLIT(CRAM30 NTWK);
885 BIND T13_E7 = UPLIT(CRAM29 NTWK);
886 BIND T13_E8 = UPLIT(CRAM28 NTWK);
887 BIND T13_E9 = UPLIT(CRAM27 NTWK);
888 BIND T13_E10 = UPLIT(CRAM26 NTWK);
889 BIND T13_E11 = UPLIT(CRAM25 NTWK);
890 BIND T13_E12 = UPLIT(CRAM24 NTWK);
891 BIND T13_E13 = UPLIT(CRAM23 NTWK);
892 BIND T13_E14 = UPLIT(CRAM22 NTWK);
893 BIND T13_E15 = UPLIT(CRAM21 NTWK);
894 BIND T13_E16 = UPLIT(CRAM20 NTWK);
895 BIND T13_E17 = UPLIT(CRAM19 NTWK);
896 BIND T13_E18 = UPLIT(CRAM18 NTWK);
897 BIND T13_E19 = UPLIT(CRAM17 NTWK);
898 BIND T13_E20 = UPLIT(CRAM16 NTWK);
899 BIND T13_E21 = UPLIT(CRAM15 NTWK);
900 BIND T13_E22 = UPLIT(CRAM14 NTWK);
901 BIND T13_E23 = UPLIT(CRAM13 NTWK);
902 BIND T13_E24 = UPLIT(CRAM12 NTWK);
903 BIND T13_E25 = UPLIT(CRAM11 NTWK);
904 BIND T13_E26 = UPLIT(CRAM10 NTWK);
905 BIND T13_E27 = UPLIT(CRAM9 NTWK);
906 BIND T13_E28 = UPLIT(CRAM8 NTWK);
907 BIND T13_E29 = UPLIT(CRAM7 NTWK);
908 BIND T13_E30 = UPLIT(CRAM6 NTWK);
909 BIND T13_E31 = UPLIT(CRAM5 NTWK);
910 BIND T13_E32 = UPLIT(CRAM4 NTWK);
911 BIND T13_E33 = UPLIT(CRAM3 NTWK);
912 BIND T13_E34 = UPLIT(CRAM2 NTWK);
913 BIND T13_E35 = UPLIT(CRAM1 NTWK);
914 BIND T13_E36 = UPLIT(CRAM0 NTWK);
915 BIND T13_E37 = UPLIT(CRAM NTWK);
916
917 BIND T13_ES = PLIT( T13_E1,
918 T13_E2,
919 T13_E3,
920 T13_E4,
921 T13_E5,
922 T13_E6,
923 T13_E7,
924 T13_E8,
925 T13_E9,
926 T13_E10,
927 T13_E11,
928 T13_E12,
929 T13_E13,
930 T13_E14,
931 T13_E15,
932 T13_E16,
933 T13_E17,
934 T13_E18,
935 T13_E19,
936 T13_E20,
937 T13_E21,
938 T13_E22,
939 T13_E23,
940 T13_E24,
941 T13_E25,
942 T13_E26,
943 T13_E27,
944 T13_E28,
945 T13_E29,
946 T13_E30,
947 T13_E31,
948 T13_E32,
949 T13_E33,
950 T13_E34,
951 T13_E35,
952 T13_E36,
953 T13_E37);
954
955
956 BIND T14_E1 = UPLIT(CADR11 NTWK);
957 BIND T14_E2 = UPLIT(CADR10 NTWK);
958 BIND T14_E3 = UPLIT(CADR9 NTWK);
959 BIND T14_E4 = UPLIT(CADR8 NTWK);
960 BIND T14_E5 = UPLIT(CADR7 NTWK);
961 BIND T14_E6 = UPLIT(CADR6 NTWK);
962 BIND T14_E7 = UPLIT(CADR5 NTWK);
963 BIND T14_E8 = UPLIT(CADR4 NTWK);
964 BIND T14_E9 = UPLIT(CADR3 NTWK);
965 BIND T14_E10 = UPLIT(CADR2 NTWK);
966 BIND T14_E11 = UPLIT(CADR1 NTWK);
967 BIND T14_E12 = UPLIT(AMX11 SKIP10 NTWK);
968 BIND T14_E13 = UPLIT(AMX10 NTWK);
969 BIND T14_E14 = UPLIT(AMX9 NTWK);
970 BIND T14_E15 = UPLIT(AMX8 NTWK);
971 BIND T14_E16 = UPLIT(AMX6_7 NTWK);
972 BIND T14_E17 = UPLIT(AMX6_7 NTWK);
973 BIND T14_E18 = UPLIT(AMX4_5 NTWK);
974 BIND T14_E19 = UPLIT(AMX4_5 NTWK);
975 BIND T14_E20 = UPLIT(AMX2_3 NTWK);
976 BIND T14_E21 = UPLIT(AMX2_3 NTWK);
977 BIND T14_E22 = UPLIT(AMX0_1 NTWK);
978 BIND T14_E23 = UPLIT(AMX0_1 NTWK);
979
980 BIND T14_ES = PLIT( T14_E1,
981 T14_E2,
982 T14_E3,
983 T14_E4,
984 T14_E5,
985 T14_E6,
986 T14_E7,
987 T14_E8,
988 T14_E9,
989 T14_E10,
990 T14_E11,
991 T14_E12,
992 T14_E13,
993 T14_E14,
994 T14_E15,
995 T14_E16,
996 T14_E17,
997 T14_E18,
998 T14_E19,
999 T14_E20,
1000 T14_E21,
1001 T14_E22,
1002 T14_E23);
1003
1004
1005 BIND T15_E1 = UPLIT(PFBUF RTN CALLRTN NTWK);
1006
1007 BIND T15_ES = PLIT( T15_E1);
1008
1009
1010 BIND T16_E1 = UPLIT(CLOC3 STACK3 DMX2 SBRET3 NTWK);
1011 BIND T16_E2 = UPLIT(CLOC2 STACK2 DMX2 SBRET2 NTWK);
1012 BIND T16_E3 = UPLIT(CLOC1 STACK1 DMX2 SBRET1 NTWK);
1013 BIND T16_E4 = UPLIT(STKWRT FRSTCYC SYNCH TCLKB DFN2 CLKD CLKEN CALLRTN NTWK);
1014 BIND T16_NE1 = UPLIT(SBRET1 SBRET2 SBRET3 STKWRT CLKD CLKEN FRSTCYC SYNCH TCLKB NTWK);
1015
1016 BIND T16_ES = PLIT( T16_E1,
1017 T16_E2,
1018 T16_E3,
1019 T16_E4);
1020 BIND T16_NES = PLIT( T16_NE1);
1021
1022
1023 BIND T17_E1 = UPLIT(AMX11 SKIP10 SBRET1 STACK1 NTWK);
1024 BIND T17_E2 = UPLIT(AMX10 SBRET1 STACK1 NTWK);
1025 BIND T17_E3 = UPLIT(AMX9 SBRET1 STACK1 NTWK);
1026 BIND T17_E4 = UPLIT(AMX8 SBRET1 STACK1 NTWK);
1027 BIND T17_E5 = UPLIT(AMX6_7 SBRET2 STACK2 NTWK);
1028 BIND T17_E6 = UPLIT(AMX6_7 SBRET2 STACK2 NTWK);
1029 BIND T17_E7 = UPLIT(AMX4_5 SBRET2 STACK2 NTWK);
1030 BIND T17_E8 = UPLIT(AMX4_5 SBRET2 STACK2 NTWK);
1031 BIND T17_E9 = UPLIT(AMX2_3 SBRET1 STACK3 NTWK);
1032 BIND T17_E10 = UPLIT(AMX2_3 SBRET1 STACK3 NTWK);
1033 BIND T17_E11 = UPLIT(AMX0_1 SBRET1 STACK3 NTWK);
1034 BIND T17_E12 = UPLIT(AMX0_1 SBRET1 STACK3 NTWK);
1035 BIND T17_E13 = UPLIT(CLKD CLKEN CALLRTN STKWRT FRSTCYC SYNCH TCLKB NTWK);
1036 BIND T17_NE1 = UPLIT(CLKD CLKEN STKWRT FRSTCYC SYNCH TCLKB SBRET1 SBRET2 SBRET3 NTWK);
1037
1038 BIND T17_ES = PLIT( T17_E1,
1039 T17_E2,
1040 T17_E3,
1041 T17_E4,
1042 T17_E5,
1043 T17_E6,
1044 T17_E7,
1045 T17_E8,
1046 T17_E9,
1047 T17_E10,
1048 T17_E11,
1049 T17_E12,
1050 T17_E13);
1051 BIND T17_NES = PLIT( T17_NE1);
1052
1053
1054 BIND T18_E1 = UPLIT(RTN CALLRTN STKADR STACK3 TCLKB STKRST PFBUF NTWK);
1055 BIND T18_E2 = UPLIT(RTN CALLRTN STKADR STACK2 TCLKB STKRST PFBUF NTWK);
1056 BIND T18_E3 = UPLIT(RTN CALLRTN STKADR STACK1 TCLKB STKRST PFBUF NTWK);
1057 BIND T18_E4 = UPLIT(STKADR RTN CALLRTN TCLKB STKRST PFBUF NTWK);
1058
1059 BIND T18_ES = PLIT( T18_E1,
1060 T18_E2,
1061 T18_E3,
1062 T18_E4);
1063
1064
1065 BIND T19_E1 = UPLIT(STKRST PFBUF CALLRTN RTN STKADR STACK NTWK);
1066
1067 BIND T19_ES = PLIT( T19_E1);
1068
1069
1070 BIND T20_E1 = UPLIT(NIC_ENC AMX11 NTWK);
1071 BIND T20_E2 = UPLIT(NIC_ENC AMX10 NTWK);
1072 BIND T20_E3 = UPLIT(NIC_ENC AMX9 NTWK);
1073 BIND T20_E4 = UPLIT(NIC_ENC NTWK);
1074 BIND T20_E5 = UPLIT(SKIP10 NIC_ENC AMX11 NTWK);
1075 BIND T20_E6 = UPLIT(NIC_ENC AMX10 NTWK);
1076 BIND T20_E7 = UPLIT(NIC_ENC AMX9 NTWK);
1077 BIND T20_NE1 = UPLIT(NIC_ENC NTWK);
1078
1079 BIND T20_ES = PLIT( T20_E1,
1080 T20_E2,
1081 T20_E3,
1082 T20_E4,
1083 T20_E5,
1084 T20_E6,
1085 T20_E7);
1086 BIND T20_NES = PLIT( T20_NE1);
1087
1088
1089 BIND T21_E1 = UPLIT(NIC_ENC TRPCYC SKIP10 AMX11 NTWK);
1090 BIND T21_E2 = UPLIT(NIC_ENC TRPCYC SKIP10 AMX11 NTWK);
1091
1092 BIND T21_ES = PLIT( T21_E1,
1093 T21_E2);
1094
1095
1096 BIND T22_E1 = UPLIT(SKIP10 AMX11 TCLKB DSP_SKP_EN SYNCH NTWK);
1097 BIND T22_E2 = UPLIT(DSP_SKP_EN SYNCH FRSTCYC NTWK);
1098 BIND T22_E3 = UPLIT(SKIP10 AMX11 TCLKB DSP_SKP_EN SYNCH NTWK);
1099 BIND T22_NE1 = UPLIT(DSP_SKP_EN SYNCH TCLKB NTWK);
1100
1101 BIND T22_ES = PLIT( T22_E1,
1102 T22_E2,
1103 T22_E3);
1104 BIND T22_NES = PLIT( T22_NE1);
1105
1106
1107 BIND T23_E1 = UPLIT(SKIP10 AMX11 TCLKB DSP_SKP_EN SYNCH NTWK);
1108 BIND T23_E2 = UPLIT(SKIP10 AMX11 TCLKB DSP_SKP_EN SYNCH NTWK);
1109 BIND T23_NE1 = UPLIT(DSP_SKP_EN TCLKB SYNCH NTWK);
1110
1111 BIND T23_ES = PLIT( T23_E1,
1112 T23_E2);
1113 BIND T23_NES = PLIT( T23_NE1);
1114
1115
1116 BIND T24_E1 = UPLIT(SKIP10 AMX11 TCLKB DSP_SKP_EN SYNCH NTWK);
1117 BIND T24_E2 = UPLIT(SKIP10 AMX11 TCLKB DSP_SKP_EN SYNCH NTWK);
1118
1119 BIND T24_ES = PLIT( T24_E1,
1120 T24_E2);
1121
1122
1123 BIND T25_E1 = UPLIT(IOLTCH SKIP10 AMX11 TCLKB DSP_SKP_EN SYNCH NTWK);
1124 BIND T25_E2 = UPLIT(SPEC10 IOLTCH SKIP10 AMX11 TCLKB DSP_SKP_EN SYNCH NTWK);
1125
1126 BIND T25_ES = PLIT( T25_E1,
1127 T25_E2);
1128
1129
1130 BIND T26_E1 = UPLIT(SKIP10 AMX11 NTWK);
1131 BIND T26_E2 = UPLIT(SKIP10 AMX11 NTWK);
1132
1133 BIND T26_ES = PLIT( T26_E1,
1134 T26_E2);
1135
1136
1137 BIND T27_E1 = UPLIT(SKIP10 AMX11 NTWK);
1138 BIND T27_E2 = UPLIT(SKIP10 AMX11 NTWK);
1139
1140 BIND T27_ES = PLIT( T27_E1,
1141 T27_E2);
1142
1143
1144 BIND T28_E1 = UPLIT(AMX10 NTWK);
1145 BIND T28_E2 = UPLIT(AMX10 NTWK);
1146
1147 BIND T28_ES = PLIT( T28_E1,
1148 T28_E2);
1149
1150
1151 BIND T29_E1 = UPLIT(AMX9 NTWK);
1152 BIND T29_E2 = UPLIT(AMX9 NTWK);
1153
1154 BIND T29_ES = PLIT( T29_E1,
1155 T29_E2);
1156
1157
1158 BIND T30_E1 = UPLIT(AMX8 NTWK);
1159 BIND T30_E2 = UPLIT(AMX8 NTWK);
1160
1161 BIND T30_ES = PLIT( T30_E1,
1162 T30_E2);
1163
1164
1165 BIND T31_E1 = UPLIT(AMX11 NTWK);
1166 BIND T31_E2 = UPLIT(AMX10 NTWK);
1167 BIND T31_E3 = UPLIT(AMX9 NTWK);
1168 BIND T31_E4 = UPLIT(AMX9 AMX10 AMX11 NTWK);
1169 BIND T31_E5 = UPLIT(SKIP10 AMX11 NTWK);
1170 BIND T31_E6 = UPLIT(AMX10 NTWK);
1171 BIND T31_E7 = UPLIT(AMX9 NTWK);
1172 BIND T31_E8 = UPLIT(AMX9 AMX10 AMX11 NTWK);
1173
1174 BIND T31_ES = PLIT( T31_E1,
1175 T31_E2,
1176 T31_E3,
1177 T31_E4,
1178 T31_E5,
1179 T31_E6,
1180 T31_E7,
1181 T31_E8);
1182
1183
1184 BIND T32_E1 = UPLIT(SKIP10 AMX11 NTWK);
1185 BIND T32_E2 = UPLIT(AMX10 NTWK);
1186 BIND T32_E3 = UPLIT(AMX9 NTWK);
1187 BIND T32_E4 = UPLIT(AMX8 NTWK);
1188 BIND T32_E5 = UPLIT(AMX8 AMX9 AMX10 AMX11 NTWK);
1189
1190 BIND T32_ES = PLIT( T32_E1,
1191 T32_E2,
1192 T32_E3,
1193 T32_E4,
1194 T32_E5);
1195
1196
1197 BIND T33_E1 = UPLIT(AMX11 NTWK);
1198 BIND T33_E2 = UPLIT(AMX10 NTWK);
1199 BIND T33_E3 = UPLIT(AMX9 NTWK);
1200 BIND T33_E4 = UPLIT(AMX8 NTWK);
1201 BIND T33_E5 = UPLIT(AMX6_7 NTWK);
1202 BIND T33_E6 = UPLIT(AMX6_7 NTWK);
1203 BIND T33_E7 = UPLIT(AMX4_5 NTWK);
1204 BIND T33_E8 = UPLIT(AMX4_5 NTWK);
1205 BIND T33_E9 = UPLIT(AMX2_3 NTWK);
1206 BIND T33_E10 = UPLIT(AMX2_3 NTWK);
1207 BIND T33_E11 = UPLIT(AMX0_1 NTWK);
1208 BIND T33_E12 = UPLIT(AMX0_1 NTWK);
1209 BIND T33_E13 = UPLIT(AMX NTWK);
1210
1211 BIND T33_ES = PLIT( T33_E1,
1212 T33_E2,
1213 T33_E3,
1214 T33_E4,
1215 T33_E5,
1216 T33_E6,
1217 T33_E7,
1218 T33_E8,
1219 T33_E9,
1220 T33_E10,
1221 T33_E11,
1222 T33_E12,
1223 T33_E13);
1224
1225
1226 BIND T34_E1 = UPLIT(AMX6_7 AREAD NTWK);
1227 BIND T34_E2 = UPLIT(AMX6_7 AREAD NTWK);
1228 BIND T34_E3 = UPLIT(AMX4_5 AREAD NTWK);
1229 BIND T34_E4 = UPLIT(AMX4_5 AREAD NTWK);
1230 BIND T34_E5 = UPLIT(AMX2_3 AREAD NTWK);
1231 BIND T34_E6 = UPLIT(AMX2_3 AREAD NTWK);
1232 BIND T34_E7 = UPLIT(AMX0_1 AREAD NTWK);
1233 BIND T34_E8 = UPLIT(AMX0_1 AREAD NTWK);
1234 BIND T34_E9 = UPLIT(AREAD NTWK);
1235
1236 BIND T34_ES = PLIT( T34_E1,
1237 T34_E2,
1238 T34_E3,
1239 T34_E4,
1240 T34_E5,
1241 T34_E6,
1242 T34_E7,
1243 T34_E8,
1244 T34_E9);
1245
1246
1247 BIND T35_E1 = UPLIT(AMX11 NTWK);
1248 BIND T35_E2 = UPLIT(AMX10 NTWK);
1249 BIND T35_E3 = UPLIT(AMX9 NTWK);
1250 BIND T35_E4 = UPLIT(AMX8 NTWK);
1251 BIND T35_E5 = UPLIT(AMX6_7 NTWK);
1252 BIND T35_E6 = UPLIT(AMX6_7 NTWK);
1253 BIND T35_E7 = UPLIT(AMX4_5 NTWK);
1254 BIND T35_E8 = UPLIT(AMX4_5 NTWK);
1255 BIND T35_E9 = UPLIT(AMX2_3 NTWK);
1256 BIND T35_E10 = UPLIT(AMX2_3 NTWK);
1257 BIND T35_E11 = UPLIT(AMX0_1 NTWK);
1258 BIND T35_E12 = UPLIT(AMX0_1 NTWK);
1259 BIND T35_E13 = UPLIT(PFBUF NTWK);
1260 BIND T35_E14 = UPLIT(PFBUF STKADR CALLRTN NTWK);
1261
1262 BIND T35_ES = PLIT( T35_E1,
1263 T35_E2,
1264 T35_E3,
1265 T35_E4,
1266 T35_E5,
1267 T35_E6,
1268 T35_E7,
1269 T35_E8,
1270 T35_E9,
1271 T35_E10,
1272 T35_E11,
1273 T35_E12,
1274 T35_E13,
1275 T35_E14);
1276
1277
1278 BIND T36_E1 = UPLIT(AMX11 NTWK);
1279
1280 BIND T36_ES = PLIT( T36_E1);
1281
1282
1283 BIND T37_E1 = UPLIT(AMX11 NTWK);
1284
1285 BIND T37_ES = PLIT( T37_E1);
1286
1287
1288 BIND T38_E1 = UPLIT(RTN NTWK);
1289
1290 BIND T38_ES = PLIT( T38_E1);
1291
1292
1293 BIND T39_E1 = UPLIT(SPEC10 NTWK);
1294 BIND T39_E2 = UPLIT(SPEC10 NTWK);
1295
1296 BIND T39_ES = PLIT( T39_E1,
1297 T39_E2);
1298
1299
1300 BIND T40_E1 = UPLIT(PARNET NTWK);
1301 BIND T40_E2 = UPLIT(PARNET NTWK);
1302
1303 BIND T40_ES = PLIT( T40_E1,
1304 T40_E2);
1305 GLOBAL BIND ES_TBL = UPLIT( T1_ES,
1306 T2_ES,
1307 T3_ES,
1308 T4_ES,
1309 T5_ES,
1310 T6_ES,
1311 T7_ES,
1312 T8_ES,
1313 T9_ES,
1314 T10_ES,
1315 T11_ES,
1316 T12_ES,
1317 T13_ES,
1318 T14_ES,
1319 T15_ES,
1320 T16_ES,
1321 T17_ES,
1322 T18_ES,
1323 T19_ES,
1324 T20_ES,
1325 T21_ES,
1326 T22_ES,
1327 T23_ES,
1328 T24_ES,
1329 T25_ES,
1330 T26_ES,
1331 T27_ES,
1332 T28_ES,
1333 T29_ES,
1334 T30_ES,
1335 T31_ES,
1336 T32_ES,
1337 T33_ES,
1338 T34_ES,
1339 T35_ES,
1340 T36_ES,
1341 T37_ES,
1342 T38_ES,
1343 T39_ES,
1344 T40_ES);
1345
1346 GLOBAL BIND NES_TBL = UPLIT( 0,
1347 T2_NES,
1348 T3_NES,
1349 T4_NES,
1350 T5_NES,
1351 T6_NES,
1352 0,
1353 0,
1354 0,
1355 T10_NES,
1356 T11_NES,
1357 0,
1358 0,
1359 0,
1360 0,
1361 T16_NES,
1362 T17_NES,
1363 0,
1364 0,
1365 T20_NES,
1366 0,
1367 T22_NES,
1368 T23_NES,
1369 0,
1370 0,
1371 0,
1372 0,
1373 0,
1374 0,
1375 0,
1376 0,
1377 0,
1378 0,
1379 0,
1380 0,
1381 0,
1382 0,
1383 0,
1384 0,
1385 0);
1386
1387 EXTERNAL ROUTINE
1388 TST1,
1389 TST2,
1390 TST3,
1391 TST4,
1392 TST5,
1393 TST6,
1394 TST7,
1395 TST8,
1396 TST9,
1397 TST10,
1398 TST11,
1399 TST12,
1400 TST13,
1401 TST14,
1402 TST15,
1403 TST16,
1404 TST17,
1405 TST18,
1406 TST19,
1407 TST20,
1408 TST21,
1409 TST22,
1410 TST23,
1411 TST24,
1412 TST25,
1413 TST26,
1414 TST27,
1415 TST28,
1416 TST29,
1417 TST30,
1418 TST31,
1419 TST32,
1420 TST33,
1421 TST34,
1422 TST35,
1423 TST36,
1424 TST37,
1425 TST38,
1426 TST39,
1427 TST40;
1428
1429
1430 GLOBAL BIND TEST_DISP = PLIT( TST1,
1431 TST2,
1432 TST3,
1433 TST4,
1434 TST5,
1435 TST6,
1436 TST7,
1437 TST8,
1438 TST9,
1439 TST10,
1440 TST11,
1441 TST12,
1442 TST13,
1443 TST14,
1444 TST15,
1445 TST16,
1446 TST17,
1447 TST18,
1448 TST19,
1449 TST20,
1450 TST21,
1451 TST22,
1452 TST23,
1453 TST24,
1454 TST25,
1455 TST26,
1456 TST27,
1457 TST28,
1458 TST29,
1459 TST30,
1460 TST31,
1461 TST32,
1462 TST33,
1463 TST34,
1464 TST35,
1465 TST36,
1466 TST37,
1467 TST38,
1468 TST39,
1469 TST40);
1470 GLOBAL LITERAL MAXTEST = 40;
1471
1472 GLOBAL
1473 TESTS_FAILED: BITVECTOR[MAXTEST];
1474
1475 GLOBAL
1476 NET_FAULTS: BITVECTOR[MAXNETS];
1477
1478 END
1479 ELUDOM
ADR11 100#
AMX 66# 768 1209
AMX0_00 61 99# 763 802
AMX0_1 67# 838 839 850 851 977 978 1033 1034 1207 1208 1232
1233 1257 1258
AMX10_00 61 217# 753 792
AMX10 73# 829 841 968 1024 1071 1075 1144 1145 1166 1168 1170
1172 1185 1188 1198 1248
AMX11_00 61 218# 752 791
AMX11 74# 828 840 967 1023 1070 1074 1089 1090 1096 1098 1107
1108 1116 1117 1123 1124 1130 1131 1137 1138 1165 1168 1169
1172 1184 1188 1197 1247 1278 1283
AMX1_00 61 208# 762 801
AMX2_00 61 209# 761 800
AMX2_3 68# 836 837 848 849 975 976 1031 1032 1205 1206 1230
1231 1255 1256
AMX3_00 61 210# 760 799
AMX4_00 61 211# 759 798
AMX4_5 69# 834 835 846 847 973 974 1029 1030 1203 1204 1228
1229 1253 1254
AMX5_00 61 212# 758 797
AMX6_00 61 213# 757 796
AMX6_7 70# 832 833 844 845 971 972 1027 1028 1201 1202 1226
1227 1251 1252
AMX7_00 61 214# 756 795
AMX8 71# 831 843 970 1026 1158 1159 1187 1188 1200 1250
AMX8_00 61 215# 755 794
AMX9 72# 830 842 969 1025 1072 1076 1151 1152 1167 1168 1171
1172 1186 1188 1199 1249
AMX9_00 61 216# 754 793
AMX_00 61# 769 807
AREAD 96# 1226 1227 1228 1229 1230 1231 1232 1233 1234
BLISS36 4
BUSBUF 147# 519 526 527 529
CADR1 158# 966
CADR10 167# 957
CADR11 168# 956
CADR2 159# 965
CADR3 160# 964
CADR4 161# 963
CADR5 162# 962
CADR6 163# 961
CADR7 164# 960
CADR8 165# 959
CADR9 166# 958
CALLRTN 91# 1005 1013 1035 1054 1055 1056 1057 1065 1260
CLKD 78# 804 1013 1014 1035 1036
CLKE 79# 551 553 805
CLKEN 83# 551 553 803 804 805 1013 1014 1035 1036
CLKF 80# 803
CLKH 81# 595 598
CLKJ 82# 594 598
CLOC1 113# 799 800 801 802 805 807 1012
CLOC2 114# 795 796 797 798 804 807 1011
CLOC3 115# 791 792 793 794 803 807 1010
CRAM 101# 915
CRAM0 169# 914
CRAM1 170# 913
CRAM10 179# 904
CRAM11 183# 903
CRAM12 184# 902
CRAM13 185# 901
CRAM14 186# 900
CRAM15 187# 899
CRAM16 188# 898
CRAM17 189# 897
CRAM18 190# 896
CRAM19 191# 895
CRAM2 171# 912
CRAM20 192# 894
CRAM21 193# 893
CRAM22 194# 892
CRAM23 195# 891
CRAM24 196# 890
CRAM25 197# 889
CRAM26 198# 888
CRAM27 199# 887
CRAM28 200# 886
CRAM29 201# 885
CRAM3 172# 911
CRAM30 202# 884
CRAM31 203# 883
CRAM32 204# 882
CRAM33 205# 881
CRAM34 206# 880
CRAM35 207# 879
CRAM4 173# 910
CRAM5 174# 909
CRAM6 175# 908
CRAM7 176# 907
CRAM8 177# 906
CRAM9 178# 905
CREG1 150# 543 544 545 546 547 548 549 695
CREG2 151# 537 538 539 540 541 542 550 696
CREG3 152# 579 585 591 632 638 669 675 709 726 733
CREG4 153# 578 584 590 631 637 668 674 708 725 732
CREG5 154# 577 583 589 630 636 667 673 707 724 731
CREG6 155# 576 582 588 629 635 666 672 706 723 730
CREG7 156# 575 581 587 628 634 665 671 705 722 729
CREG8 157# 574 580 586 627 633 664 670 704 721 728
CRM0_NAME 278# 420 473
CRM0_0 222# 548
CRM0_1 223# 547
CRM0_10 232# 538
CRM0_11 233# 537
CRM0_12 234# 585
CRM0_13 235# 584
CRM0_14 236# 583
CRM0_15 237# 582
CRM0_16 238# 581
CRM0_17 239# 580
CRM0_18 240# 579
CRM0_19 241# 578
CRM0_2 224# 546
CRM0_20 242# 577
CRM0_21 243# 576
CRM0_22 244# 575
CRM0_23 245# 574
CRM0_24 246# 638 675
CRM0_25 247# 637 674
CRM0_26 248# 636 673
CRM0_27 249# 635 672
CRM0_28 250# 634 671
CRM0_29 251# 633 670
CRM0_3 225# 545
CRM0_30 252# 632 669
CRM0_31 253# 631 668
CRM0_32 254# 630 667
CRM0_33 255# 629 666
CRM0_34 256# 628 665
CRM0_35 257# 627 664
CRM0_4 226# 544
CRM0_5 227# 543
CRM0_6 228# 542
CRM0_7 229# 541
CRM0_8 230# 540
CRM0_9 231# 539
CRM10_NAME 288# 430 483
CRM11_NAME 289# 434 484
CRM12_NAME 290# 435 485
CRM13_NAME 291# 436 486
CRM14_NAME 292# 437 487
CRM15_NAME 293# 438 488
CRM16_NAME 294# 439 489
CRM17_NAME 295# 440 490
CRM18_NAME 296# 441 491
CRM19_NAME 297# 442 492
CRM1_NAME 279# 421 474
CRM20_NAME 298# 443 493
CRM21_NAME 299# 444 494
CRM22_NAME 300# 445 495
CRM23_NAME 301# 446 496
CRM24_NAME 302# 447 497
CRM25_NAME 303# 448 498
CRM26_NAME 304# 449 499
CRM27_NAME 305# 450 500
CRM28_NAME 306# 451 501
CRM29_NAME 307# 452 502
CRM2_NAME 280# 422 475
CRM30_NAME 308# 453 503
CRM31_NAME 309# 454 504
CRM32_NAME 310# 455 505
CRM33_NAME 311# 456 506
CRM34_NAME 312# 457 507
CRM35_NAME 313# 458 508
CRM3_NAME 281# 423 476
CRM4_NAME 282# 424 477
CRM5_NAME 283# 425 478
CRM6_NAME 284# 426 479
CRM7_NAME 285# 427 480
CRM8_NAME 286# 428 481
CRM9_NAME 287# 429 482
CWRT0_5 134# 549 553
CWRT12_17 136# 592 598
CWRT18_23 137# 593 598
CWRT24_29 138# 639 643
CWRT30_35 139# 640 643
CWRT6_11 135# 550 553
CWRT_DEC 277# 385 386 387 388 389 390
DADR 140# 768 769
DADR1 144# 760 761 762 763 766 769 799 800 801 802 805
807
DADR2 145# 756 757 758 759 765 769 795 796 797 798 804
807
DADR3 146# 752 753 754 755 764 769 791 792 793 794 803
807
DATA_EDIT 52#
DATA_VERSION 51#
DFN0 125# 551 552 553
DFN1 126# 596 597 598 768 769
DFN11 133# 528 529
DFN2 127# 641 642 643 676 677 1013
DFN3 128# 806 807
DFN4 129# 596 597 598
DFN5 130# 641 642 643
DFN6 131# 676 677
DFN7 132# 520
DIAG_FN 276# 376 377 378 379 380 381 382 383 384
DIAG_MUX 275# 367 368 369 370 371 372 373 374 375
DMX0 116# 537 538 539 540 541 542 543 544 545 546 547
548 553 695 696 697
DMX1 117# 752 753 754 755 756 757 758 759 760 761 762
763 769
DMX11 124# 526 529
DMX2 118# 1010 1011 1012
DMX3 119# 791 792 793 794 795 796 797 798 799 800 801
802 807
DMX4 120# 574 575 576 577 578 579 580 581 582 583 584
585 598 704 705 706 707 708 709
DMX5 121# 627 628 629 630 631 632 633 634 635 636 637
638 643 721 722 723 724 725 726
DMX6 122# 664 665 666 667 668 669 670 671 672 673 674
675 677 728 729 730 731 732 733
DMX7 123# 519
DSP_SKP_EN 86# 1096 1097 1098 1099 1107 1108 1109 1116 1117 1123 1124
ES_TBL 1305#
FRSTCYC 87# 1013 1014 1035 1036 1097
IOLTCH 88# 1123 1124
LANGUAGE 4
MAXNETS 53# 1476
MAXTEST 1470# 1473
MSCRAD 3#
NES_TBL 1346#
NET_FAULTS 1476
NET_NAMES 316#
NIC_ENC 97# 1070 1071 1072 1073 1074 1075 1076 1077 1089 1090
NTWK 259# 519 520 526 527 528 529 537 538 539 540 541
542 543 544 545 546 547 548 549 550 551 552 553
574 575 576 577 578 579 580 581 582 583 584 585
586 587 588 589 590 591 592 593 594 595 596 597
598 627 628 629 630 631 632 633 634 635 636 637
638 639 640 641 642 643 664 665 666 667 668 669
670 671 672 673 674 675 676 677 695 696 697 704
705 706 707 708 709 710 721 722 723 724 725 726
727 728 729 730 731 732 733 734 752 753 754 755
756 757 758 759 760 761 762 763 764 765 766 767
768 769 791 792 793 794 795 796 797 798 799 800
801 802 803 804 805 806 807 828 829 830 831 832
833 834 835 836 837 838 839 840 841 842 843 844
845 846 847 848 849 850 851 879 880 881 882 883
884 885 886 887 888 889 890 891 892 893 894 895
896 897 898 899 900 901 902 903 904 905 906 907
908 909 910 911 912 913 914 915 956 957 958 959
960 961 962 963 964 965 966 967 968 969 970 971
972 973 974 975 976 977 978 1005 1010 1011 1012 1013
1014 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033
1034 1035 1036 1054 1055 1056 1057 1065 1070 1071 1072 1073
1074 1075 1076 1077 1089 1090 1096 1097 1098 1099 1107 1108
1109 1116 1117 1123 1124 1130 1131 1137 1138 1144 1145 1151
1152 1158 1159 1165 1166 1167 1168 1169 1170 1171 1172 1184
1185 1186 1187 1188 1197 1198 1199 1200 1201 1202 1203 1204
1205 1206 1207 1208 1209 1226 1227 1228 1229 1230 1231 1232
1233 1234 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256
1257 1258 1259 1260 1278 1283 1288 1293 1294 1300 1301
PARNET 149# 1300 1301
PFBUF 85# 767 1005 1054 1055 1056 1057 1065 1259 1260
RESET 92# 551 596 641 697 710 727 734
RTN 90# 1005 1054 1055 1056 1057 1065 1288
SBRET1 107# 1012 1014 1023 1024 1025 1026 1031 1032 1033 1034 1036
SBRET2 108# 1011 1014 1027 1028 1029 1030 1036
SBRET3 109# 1010 1014 1036
SKIP10 94# 752 791 828 840 967 1023 1074 1089 1090 1096 1098
1107 1108 1116 1117 1123 1124 1130 1131 1137 1138 1169 1184
SPEC10 95# 1124 1293 1294
STACK1 110# 1012 1023 1024 1025 1026 1056
STACK2 111# 1011 1027 1028 1029 1030 1055
STACK3 112# 1010 1031 1032 1033 1034 1054
STKADR 106# 1054 1055 1056 1057 1065 1260
STKRST 93# 1054 1055 1056 1057 1065
STKWRT 75# 1013 1014 1035 1036
SYNCH 84# 594 595 596 598 641 1013 1014 1035 1036 1096 1097
1098 1099 1107 1108 1109 1116 1117 1123 1124
SYNCL 89#
T10_ES 771# 1314
T10_E1 752# 771
T10_E10 761# 780
T10_E11 762# 781
T10_E12 763# 782
T10_E13 764# 783
T10_E14 765# 784
T10_E15 766# 785
T10_E16 767# 786
T10_E17 768# 787
T10_E2 753# 772
T10_E3 754# 773
T10_E4 755# 774
T10_E5 756# 775
T10_E6 757# 776
T10_E7 758# 777
T10_E8 759# 778
T10_E9 760# 779
T10_NE1 769# 788
T10_NES 788# 1355
T11_ES 809# 1315
T11_E1 791# 809
T11_E10 800# 818
T11_E11 801# 819
T11_E12 802# 820
T11_E13 803# 821
T11_E14 804# 822
T11_E15 805# 823
T11_E16 806# 824
T11_E2 792# 810
T11_E3 793# 811
T11_E4 794# 812
T11_E5 795# 813
T11_E6 796# 814
T11_E7 797# 815
T11_E8 798# 816
T11_E9 799# 817
T11_NE1 807# 825
T11_NES 825# 1356
T12_ES 853# 1316
T12_E1 828# 853
T12_E10 837# 862
T12_E11 838# 863
T12_E12 839# 864
T12_E13 840# 865
T12_E14 841# 866
T12_E15 842# 867
T12_E16 843# 868
T12_E17 844# 869
T12_E18 845# 870
T12_E19 846# 871
T12_E2 829# 854
T12_E20 847# 872
T12_E21 848# 873
T12_E22 849# 874
T12_E23 850# 875
T12_E24 851# 876
T12_E3 830# 855
T12_E4 831# 856
T12_E5 832# 857
T12_E6 833# 858
T12_E7 834# 859
T12_E8 835# 860
T12_E9 836# 861
T13_ES 917# 1317
T13_E1 879# 917
T13_E10 888# 926
T13_E11 889# 927
T13_E12 890# 928
T13_E13 891# 929
T13_E14 892# 930
T13_E15 893# 931
T13_E16 894# 932
T13_E17 895# 933
T13_E18 896# 934
T13_E19 897# 935
T13_E2 880# 918
T13_E20 898# 936
T13_E21 899# 937
T13_E22 900# 938
T13_E23 901# 939
T13_E24 902# 940
T13_E25 903# 941
T13_E26 904# 942
T13_E27 905# 943
T13_E28 906# 944
T13_E29 907# 945
T13_E3 881# 919
T13_E30 908# 946
T13_E31 909# 947
T13_E32 910# 948
T13_E33 911# 949
T13_E34 912# 950
T13_E35 913# 951
T13_E36 914# 952
T13_E37 915# 953
T13_E4 882# 920
T13_E5 883# 921
T13_E6 884# 922
T13_E7 885# 923
T13_E8 886# 924
T13_E9 887# 925
T14_ES 980# 1318
T14_E1 956# 980
T14_E10 965# 989
T14_E11 966# 990
T14_E12 967# 991
T14_E13 968# 992
T14_E14 969# 993
T14_E15 970# 994
T14_E16 971# 995
T14_E17 972# 996
T14_E18 973# 997
T14_E19 974# 998
T14_E2 957# 981
T14_E20 975# 999
T14_E21 976# 1000
T14_E22 977# 1001
T14_E23 978# 1002
T14_E3 958# 982
T14_E4 959# 983
T14_E5 960# 984
T14_E6 961# 985
T14_E7 962# 986
T14_E8 963# 987
T14_E9 964# 988
T15_ES 1007# 1319
T15_E1 1005# 1007
T16_ES 1016# 1320
T16_E1 1010# 1016
T16_E2 1011# 1017
T16_E3 1012# 1018
T16_E4 1013# 1019
T16_NE1 1014# 1020
T16_NES 1020# 1361
T17_ES 1038# 1321
T17_E1 1023# 1038
T17_E10 1032# 1047
T17_E11 1033# 1048
T17_E12 1034# 1049
T17_E13 1035# 1050
T17_E2 1024# 1039
T17_E3 1025# 1040
T17_E4 1026# 1041
T17_E5 1027# 1042
T17_E6 1028# 1043
T17_E7 1029# 1044
T17_E8 1030# 1045
T17_E9 1031# 1046
T17_NE1 1036# 1051
T17_NES 1051# 1362
T18_ES 1059# 1322
T18_E1 1054# 1059
T18_E2 1055# 1060
T18_E3 1056# 1061
T18_E4 1057# 1062
T19_ES 1067# 1323
T19_E1 1065# 1067
T1_E1 519# 522
T1_E2 520# 523
T1_ES 522# 1305
T20_ES 1079# 1324
T20_E1 1070# 1079
T20_E2 1071# 1080
T20_E3 1072# 1081
T20_E4 1073# 1082
T20_E5 1074# 1083
T20_E6 1075# 1084
T20_E7 1076# 1085
T20_NE1 1077# 1086
T20_NES 1086# 1365
T21_ES 1092# 1325
T21_E1 1089# 1092
T21_E2 1090# 1093
T22_ES 1101# 1326
T22_E1 1096# 1101
T22_E2 1097# 1102
T22_E3 1098# 1103
T22_NE1 1099# 1104
T22_NES 1104# 1367
T23_ES 1111# 1327
T23_E1 1107# 1111
T23_E2 1108# 1112
T23_NE1 1109# 1113
T23_NES 1113# 1368
T24_ES 1119# 1328
T24_E1 1116# 1119
T24_E2 1117# 1120
T25_ES 1126# 1329
T25_E1 1123# 1126
T25_E2 1124# 1127
T26_ES 1133# 1330
T26_E1 1130# 1133
T26_E2 1131# 1134
T27_ES 1140# 1331
T27_E1 1137# 1140
T27_E2 1138# 1141
T28_ES 1147# 1332
T28_E1 1144# 1147
T28_E2 1145# 1148
T29_ES 1154# 1333
T29_E1 1151# 1154
T29_E2 1152# 1155
T2_E1 526# 531
T2_E2 527# 532
T2_E3 528# 533
T2_ES 531# 1306
T2_NES 534# 1347
T2_NE1 529# 534
T30_ES 1161# 1334
T30_E1 1158# 1161
T30_E2 1159# 1162
T31_ES 1174# 1335
T31_E1 1165# 1174
T31_E2 1166# 1175
T31_E3 1167# 1176
T31_E4 1168# 1177
T31_E5 1169# 1178
T31_E6 1170# 1179
T31_E7 1171# 1180
T31_E8 1172# 1181
T32_ES 1190# 1336
T32_E1 1184# 1190
T32_E2 1185# 1191
T32_E3 1186# 1192
T32_E4 1187# 1193
T32_E5 1188# 1194
T33_ES 1211# 1337
T33_E1 1197# 1211
T33_E10 1206# 1220
T33_E11 1207# 1221
T33_E12 1208# 1222
T33_E13 1209# 1223
T33_E2 1198# 1212
T33_E3 1199# 1213
T33_E4 1200# 1214
T33_E5 1201# 1215
T33_E6 1202# 1216
T33_E7 1203# 1217
T33_E8 1204# 1218
T33_E9 1205# 1219
T34_ES 1236# 1338
T34_E1 1226# 1236
T34_E2 1227# 1237
T34_E3 1228# 1238
T34_E4 1229# 1239
T34_E5 1230# 1240
T34_E6 1231# 1241
T34_E7 1232# 1242
T34_E8 1233# 1243
T34_E9 1234# 1244
T35_ES 1262# 1339
T35_E1 1247# 1262
T35_E10 1256# 1271
T35_E11 1257# 1272
T35_E12 1258# 1273
T35_E13 1259# 1274
T35_E14 1260# 1275
T35_E2 1248# 1263
T35_E3 1249# 1264
T35_E4 1250# 1265
T35_E5 1251# 1266
T35_E6 1252# 1267
T35_E7 1253# 1268
T35_E8 1254# 1269
T35_E9 1255# 1270
T36_ES 1280# 1340
T36_E1 1278# 1280
T37_ES 1285# 1341
T37_E1 1283# 1285
T38_ES 1290# 1342
T38_E1 1288# 1290
T39_ES 1296# 1343
T39_E1 1293# 1296
T39_E2 1294# 1297
T3_E1 537# 555
T3_E10 546# 564
T3_E11 547# 565
T3_E12 548# 566
T3_E13 549# 567
T3_E14 550# 568
T3_E15 551# 569
T3_E16 552# 570
T3_E2 538# 556
T3_E3 539# 557
T3_E4 540# 558
T3_E5 541# 559
T3_E6 542# 560
T3_E7 543# 561
T3_E8 544# 562
T3_E9 545# 563
T3_ES 555# 1307
T3_NES 571# 1348
T3_NE1 553# 571
T40_ES 1303# 1344
T40_E1 1300# 1303
T40_E2 1301# 1304
T4_E1 574# 600
T4_E10 583# 609
T4_E11 584# 610
T4_E12 585# 611
T4_E13 586# 612
T4_E14 587# 613
T4_E15 588# 614
T4_E16 589# 615
T4_E17 590# 616
T4_E18 591# 617
T4_E19 592# 618
T4_E2 575# 601
T4_E20 593# 619
T4_E21 594# 620
T4_E22 595# 621
T4_E23 596# 622
T4_E24 597# 623
T4_E3 576# 602
T4_E4 577# 603
T4_E5 578# 604
T4_E6 579# 605
T4_E7 580# 606
T4_E8 581# 607
T4_E9 582# 608
T4_ES 600# 1308
T4_NES 624# 1349
T4_NE1 598# 624
T5_E1 627# 645
T5_E10 636# 654
T5_E11 637# 655
T5_E12 638# 656
T5_E13 639# 657
T5_E14 640# 658
T5_E15 641# 659
T5_E16 642# 660
T5_E2 628# 646
T5_E3 629# 647
T5_E4 630# 648
T5_E5 631# 649
T5_E6 632# 650
T5_E7 633# 651
T5_E8 634# 652
T5_E9 635# 653
T5_ES 645# 1309
T5_NES 661# 1350
T5_NE1 643# 661
T6_E1 664# 679
T6_E10 673# 688
T6_E11 674# 689
T6_E12 675# 690
T6_E13 676# 691
T6_E2 665# 680
T6_E3 666# 681
T6_E4 667# 682
T6_E5 668# 683
T6_E6 669# 684
T6_E7 670# 685
T6_E8 671# 686
T6_E9 672# 687
T6_ES 679# 1310
T6_NES 692# 1351
T6_NE1 677# 692
T7_E1 695# 699
T7_E2 696# 700
T7_E3 697# 701
T7_ES 699# 1311
T8_E1 704# 712
T8_E2 705# 713
T8_E3 706# 714
T8_E4 707# 715
T8_E5 708# 716
T8_E6 709# 717
T8_E7 710# 718
T8_ES 712# 1312
T9_E1 721# 736
T9_E10 730# 745
T9_E11 731# 746
T9_E12 732# 747
T9_E13 733# 748
T9_E14 734# 749
T9_E2 722# 737
T9_E3 723# 738
T9_E4 724# 739
T9_E5 725# 740
T9_E6 726# 741
T9_E7 727# 742
T9_E8 728# 743
T9_E9 729# 744
T9_ES 736# 1313
TCLKB 76# 1013 1014 1035 1036 1054 1055 1056 1057 1096 1098 1099
1107 1108 1109 1116 1117 1123 1124
TCLKC 77# 528 529
TESTS_FAILED 1473
TEST_DISP 1430#
TEXT 60
TRPCYC 98# 1089 1090
TST1 1388* 1430
TST10 1397 1439
TST11 1398 1440
TST12 1399 1441
TST13 1400 1442
TST14 1401 1443
TST15 1402 1444
TST16 1403 1445
TST17 1404 1446
TST18 1405 1447
TST19 1406 1448
TST2 1389 1431
TST20 1407 1449
TST21 1408 1450
TST22 1409 1451
TST23 1410 1452
TST24 1411 1453
TST25 1412 1454
TST26 1413 1455
TST27 1414 1456
TST28 1415 1457
TST29 1416 1458
TST3 1390 1432
TST30 1417 1459
TST31 1418 1460
TST32 1419 1461
TST33 1420 1462
TST34 1421 1463
TST35 1422 1464
TST36 1423 1465
TST37 1424 1466
TST38 1425 1467
TST39 1426 1468
TST4 1391 1433
TST40 1427 1469
TST5 1392 1434
TST6 1393 1435
TST7 1394 1436
TST8 1395 1437
TST9 1396 1438
UPAZ 60# 275 276 277 278 279 280 281 282 283 284 285
286 287 288 289 290 291 292 293 294 295 296 297
298 299 300 301 302 303 304 305 306 307 308 309
310 311 312 313 316 317 318 319 320 321 322 323
324 325 326 327 328 329 330 331 332 333 334 335
336 337 338 339 340 341 342 343 344 345 346 347
348 349 350 351 356 357 358 359 360 361 362 363
364 365 366 391 395 396 397 398 399 400 401 402
403 404 405 406 407 408 409 410 411 412 413 414
415 416 417 418 419 459 460 461 462 463 464 465
466 467 468 469
W_0 66 67 68 69 70 71 72 73 74 75 76 77
78 79 80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99 100 101
259 260 267#
W_1 105 106 107 108 109 110 111 112 113 114 115 116
117 118 119 120 121 122 123 124 125 126 127 128
129 130 131 132 133 134 135 136 137 138 139 140
259 261 268#
W_2 144 145 146 147 148 149 150 151 152 153 154 155
156 157 158 159 160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175 176 177 178 179
259 262 269#
W_3 183 184 185 186 187 188 189 190 191 192 193 194
195 196 197 198 199 200 201 202 203 204 205 206
207 208 209 210 211 212 213 214 215 216 217 218
259 263 270#
W_4 222 223 224 225 226 227 228 229 230 231 232 233
234 235 236 237 238 239 240 241 242 243 244 245
246 247 248 249 250 251 252 253 254 255 256 257
259 264 271#
XCVRS 148# 519 526 527 529
TIME: 5 SEC.
CORE: 15K