Trailing-Edge
-
PDP-10 Archives
-
klad_sources
-
klad.sources/mscsl.msg
There are no other files named mscsl.msg in the archive.
]1
[1
!STIMULUS:
WRT 100/0 - NEGATE 'RESET'
WRT 100/200 - ASSERT 'CSL3 RESET L'. THIS SHOULD ASSERT
'CSL5 RESET H' WHICH SHOULD ASSERT 'R RESET'.
RESPONSE:
'R RESET' DIDN'T ASSERT
!
[2
!STIMULUS:
WRT 100/0 - NEGATE 'RESET'
WRT 100/200 - ASSERT 'CSL3 RESET L'. THIS SHOULD ASSERT
'CSL5 RESET H' WHICH SHOULD ASSERT 'R RESET'.
WRT 100/0 - NEGATE 'RESET'
RESPONSE:
'R RESET' DIDN'T NEGATE
!
[3
!STIMULUS:
WRT 100/200 - ASSERT 'RESET' AND NEGATE 'PE DETECT'
WRT 100/0 - NEGATE 'RESET'
RESPONSE:
'PE (1)' IS ASSERTED ALTHOUGH 'PE DETECT' IS NEGATED.
!
]2
[1
!STIMULUS:
WRT 205/100 - STOP CLOCK
WRT 210/0 - NEGATE 'BUS REQ'
WRT 210/100 - ASSERT 'BUS REQ'
RESPONSE:
'BUS REQ' DIDN'T ASSERT
!
[2
!STIMULUS:
WRT 205/100 - STOP CLOCK
WRT 210/0 - NEGATE 'BUS REQ'
WRT 210/100 - ASSERT 'BUS REQ'
WRT 210/0 - NEGATE 'BUS REQ'
RESPONSE:
'BUS REQ' DIDN'T NEGATE
!
]3
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 210/100 - ASSERT 'BUS REQ'
RESPONSE:
'BUS REQ' DIDN'T NEGATE
!
]4
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 114/0 (TO NEGATE NEXM)
WRT 210/300 - ASSERT 'MEM' AND 'BUS REQ'.
RESPONSE:
'NEXM' DIDN'T ASSERT
!
[2
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 114/0 (TO NEGATE NEXM)
WRT 210/300 - ASSERT 'MEM' AND 'BUS REQ'
WRT 114/0 (TO NEGATE NEXM)
RESPONSE:
'NEXM' DIDN'T NEGATE
!
]5
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 210/300 - ASSERT 'MEM' AND 'BUS REQ'
ASSERT AND NEGATE 'RESET'
WRT 114/0 (TO NEGATE NEXM)
RESPONSE:
NEXM DIDN'T NEGATE
!
]6
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 115/0 - INSURE THAT 'COM/ADR' WILL BE NEGATED
WRT 210/100 - ASSERT 'BUS REQ' WITHOUT 'MEM'.
RESPONSE:
NEXM ASSERTED
!
]7
[1
!STIMULUS:
WRT 210/0 - NEGATE 'CLOSE LATCHS'
WRT 210/1 - ASSERT 'CLOSE LATCHS'. THIS SHOULD NEGATE
'R CLK ENB'.
RESPONSE:
'R CLK ENB (0) H' DIDN'T ASSERT
!
[2
!STIMULUS:
WRT 210/0 - NEGATE 'CLOSE LATCHS'
WRT 210/1 - ASSERT 'CLOSE LATCHS'. THIS SHOULD NEGATE
'R CLK ENB'.
WRT 210/0 - NEGATE 'CLOSE LATCHS'. THIS SHOULD ASSERT
'R CLK ENB'.
RESPONSE:
'R CLK ENB (0) H' DIDN'T NEGATE
!
]8
[1
!STIMULUS:
WRT 205/100 - STOP CLOCK
WRT 210/1 - ASSERT 'CLOSE LATCHS'
RESPONSE:
'R CLK ENB' NEGATED EVEN THOUGH CLOCK SHOULD HAVE BEEN STOPPED.
!
[2
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 205/100 - STOP CLOCK
WRT 210/1 - ASSERT 'CLOSE LATCHS'.
GENERATE 8 CLOCK TICKS
RESPONSE:
'R CLK ENB (0) H' DIDN'T ASSERT
!
]9
[1
!STIMULUS:
WRT 210/1 - ASSERT 'CLOSE LATCHS'. THIS SHOULD ASSERT
'R CLK ENB (0) H'.
ASSERT AND NEGATE 'RESET'. THIS SHOULD NEGATE 'CLOSE LATCHS',
WHICH SHOULD CAUSE 'R CLK ENB (0) H' TO NEGATE.
RESPONSE:
'R CLK ENB (0) H' DIDN'T NEGATE
!
]10
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 210/103 - ASSERTING 'CLOSE LATCHS' WILL ASSERT 'R CLK
ENB (0) H'. ASSERTING 'BUS REQ' WILL CAUSE
'GRANT (1)' TO ASSERT. THIS TOGETHER WITH
'LATCH DATA SENT' SHOULD CAUSE 'R CLK ENB (0) H'
TO NEGATE.
RESPONSE:
'R CLK ENB (0) H' DIDN'T NEGATE
!
]11
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 210/101 - ASSERTING 'CLOSE LATCHS' WILL ASSERT 'R CLK ENB
(0) H'. ASSERTING 'BUS REQ' WILL ASSERT 'GRANT
(1)'. BUT WITHOUT 'LATCH DATA SENT' ASSERTED,
'R CLK ENB (0) H' SHOULD STAY ASSERTED.
RESPONSE:
'R CLK ENB (0) H' DIDN'T ASSERT
!
]12
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 210/3 - ASSERTING 'CLOSE LATCHS' WILL ASSERT 'R CLK ENB
(0) H'. ASSERTING 'LATCH DATA SENT' WITHOUT 'BUS
REQ' SHOULD NOT CAUSE 'R CLK ENB (0) H' TO NEGATE.
RESPONSE:
'R CLK ENB (0) H' NEGATED
!
]13
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 210/103 - ASSERTING 'CLOSE LATCHS' WILL ASSERT 'R CLK
ENB (0) H'. ASSERTING 'BUS REQ' WILL CAUSE
'GRANT (1)' TO ASSERT. THIS TOGETHER WITH
'LATCH DATA SENT' SHOULD CAUSE 'R CLK ENB (0) H'
TO NEGATE.
WRT 210/1 - WRITING TO REG 210 SHOULD NEGATE 'LATCH DATA
SENT'. THIS SHOULD ASSERT 'R CLK ENB (0) H'.
RESPONSE:
'R CLK ENB (0) H' DIDN'T ASSERT
!
]14
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 210/1 - ASSERT 'CLOSE LATCHS' TO ASSERT 'R CLK
ENB (0) H'.
STOP CLOCK AND SYNC TO STATE WITH T CLK AND R CLK NEGATED
WRT 210/101 - ASSERT 'BUS REQ'.
ASSERT T CLK - THIS SHOULD NEGATE 'R CLK ENB (0) H'.
RESPONSE:
'R CLK ENB (0) H' DIDN'T NEGATE
!
]15
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
STOP CLOCK AND SYNC TO STATE WITH T CLK AND R CLK NEGATED
ASSERT AND NEGATE 'CRA/M RESET'
WRT 206/2 - ASSERT 'SINGLE CLK'.
GENERATE 2 T-CLK/R-CLK CYCLES. THIS SHOULD CAUSE 'CRA/M CLK
ENABLE' TO ASSERT.
RESPONSE:
'CRA/M CLK ENABLE' DIDN'T ASSERT
!
[2
!STIMULUS:
ASSERT AND NEGATE 'RESET'
STOP CLOCK AND SYNC TO STATE WITH T CLK AND R CLK NEGATED
ASSERT AND NEGATE 'CRA/M RESET'
WRT 206/2 - ASSERT 'SINGLE CLK'.
GENERATE 2 T-CLK/R-CLK CYCLES. THIS SHOULD CAUSE 'DPE/M CLK
ENABLE' TO ASSERT.
RESPONSE:
'DPE/M CLK ENABLE' DIDN'T ASSERT
!
[3
!STIMULUS:
ASSERT AND NEGATE 'RESET'
STOP CLOCK AND SYNC TO STATE WITH T CLK AND R CLK NEGATED
ASSERT AND NEGATE 'CRA/M RESET'
WRT 206/2 - ASSERT 'SINGLE CLK'.
GENERATE 3 T-CLK/R-CLK CYCLES. THIS SHOULD CAUSE 'CRA/M CLK
ENABLE' TO ASSERT THEN NEGATE.
RESPONSE:
'CRA/M CLK ENABLE' DIDN'T NEGATE
!
[4
!STIMULUS:
ASSERT AND NEGATE 'RESET'
STOP CLOCK AND SYNC TO STATE WITH T CLK AND R CLK NEGATED
ASSERT AND NEGATE 'CRA/M RESET'
WRT 206/2 - ASSERT 'SINGLE CLK'.
GENERATE 3 T-CLK/R-CLK CYCLES. THIS SHOULD CAUSE 'DPE/M CLK
ENABLE' TO ASSERT THEN NEGATE.
RESPONSE:
'DPE/M CLK ENABLE' DIDN'T NEGATE
!
[5
!STIMULUS:
ASSERT AND NEGATE 'RESET'
STOP CLOCK AND SYNC TO STATE WITH T CLK AND R CLK NEGATED
ASSERT AND NEGATE 'CRA/M RESET'
WRT 206/2 - ASSERT 'SINGLE CLK'.
GENERATE 4 T-CLK/R-CLK CYCLES. THIS SHOULD CAUSE 'CRA/M CLK
ENABLE' TO ASSERT THEN NEGATE.
RESPONSE:
'CRA/M CLK ENABLE' DIDN'T STAY NEGATE
!
[6
!STIMULUS:
ASSERT AND NEGATE 'RESET'
STOP CLOCK AND SYNC TO STATE WITH T CLK AND R CLK NEGATED
ASSERT AND NEGATE 'CRA/M RESET'
WRT 206/2 - ASSERT 'SINGLE CLK'.
GENERATE 4 T-CLK/R-CLK CYCLES. THIS SHOULD CAUSE 'DPE/M CLK
ENABLE' TO ASSERT THEN NEGATE.
RESPONSE:
'DPE/M CLK ENABLE' DIDN'T STAY NEGATED.
!
]16
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
ASSERT AND NEGATE 'CRA/M RESET'
STOP CLOCK AND SYNC TO STATE WITH T CLK AND R CLK NEGATED
WRT 206/0
GENERATE 2 T-CLK/R-CLK CYCLES. WITH 'SINGLE CLK' AND 'CLK RUN'
NEGATED, 'CRA/M CLK ENABLE' SHOULDN'T ASSERT.
RESPONSE:
'CRA/M CLK ENABLE' ASSERTED
!
]17
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
STOP CLOCK AND SYNC TO STATE WITH T CLK AND R CLK NEGATED
WRT 115/CORRECT DATA
WRT 114/CORRECT DATA COMPLEMENTED
WRT 210/140
GENERATE 10 CLOCK TICKS
RESPONSE:
KS10 BUS CONTROL SIGNALS ARE INCORRECT. THEY ARE READ BACK
FROM REGISTER 102.
!
]18
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
STOP CLOCK AND SYNC TO STATE WITH T CLK AND R CLK NEGATED
WRT 114/CORRECT DATA
WRT 115/CORRECT DATA COMPLEMENTED
WRT 210/120
GENERATE 10 CLOCK TICKS
RESPONSE:
KS10 BUS CONTROL SIGNALS ARE INCORRECT. THEY ARE READ BACK
FROM REGISTER 102.
!
]19
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
RD 0 - TO NEGATE 'DATA ACK'
WRT 114/1 - SO 'R DATA' WILL ASSERT
WRT 210/323 - ASSERTING 'BUS REQ' WILL ASSERT 'GRANT'
- 'GRANT (1)' AND 'LATCH DATA (1)' WILL ASSERT
'LATCH DATA ENB (1)'.
- 'R DATA' AND 'MEM' WILL ASSERT 'RETURN DATA'
- 'RETURN DATA' AND 'LATCH DATA ENB (1)' WILL
ASSERT 'DATA ENB' WHICH IN TURN WILL ASSERT
'DATA ACK'.
RESPONSE:
'DATA ACK' DIDN'T ASSERT
!
[2
!STIMULUS:
ASSERT AND NEGATE 'RESET'
RD 0 - TO NEGATE 'DATA ACK'
WRT 114/1 - SO 'R DATA' WILL ASSERT
WRT 210/323 - ASSERTING 'BUS REQ' WILL ASSERT 'GRANT'
- ASSERTING 'CLOSE LATCHS' WILL NEGATE
'R CLK ENB'
- 'GRANT (1)' AND 'LATCH DATA (1)' WILL ASSERT
'LATCH DATA ENB (1)' WHICH IN TURN WILL
ASSERT 'R CLK ENB'
- 'R DATA' AND 'MEM' WILL ASSERT 'RETURN DATA'
- 'RETURN DATA' AND 'LATCH DATA ENB (1)' WILL
ASSERT 'DATA ENB' WHICH IN TURN WILL NEGATE
'R CLK ENB'.
RESPONSE:
'R CLK ENB' DIDN'T NEGATE
!
[3
!STIMULUS:
ASSERT AND NEGATE 'RESET'
RD 0 - TO NEGATE 'DATA ACK'
WRT 114/1 - SO 'R DATA' WILL ASSERT
WRT 210/323 - ASSERTING 'BUS REQ' WILL ASSERT 'GRANT'
- 'GRANT (1)' AND 'LATCH DATA (1)' WILL ASSERT
'LATCH DATA ENB (1)'.
- 'R DATA' AND 'MEM' WILL ASSERT 'RETURN DATA'
- 'RETURN DATA' AND 'LATCH DATA ENB (1)' WILL
ASSERT 'DATA ENB' WHICH IN TURN WILL ASSERT
'DATA ACK'.
RD 0 - TO NEGATE 'DATA ACK'
RESPONSE:
'DATA ACK' DIDN'T NEGATE.
!
]20
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
RD 0 - TO NEGATE 'DATA ACK'
WRT 114/2 - SO 'R I/O DATA' WILL ASSERT
WRT 210/123 - ASSERTING 'BUS REQ' WILL ASSERT 'GRANT'
- 'GRANT (1)' AND 'LATCH DATA (1)' WILL ASSERT
'LATCH DATA ENB (1)'.
- 'R I/O DATA' WILL ASSERT 'RETURN DATA'
- 'RETURN DATA' AND 'LATCH DATA ENB (1)' WILL
ASSERT 'DATA ENB' WHICH IN TURN WILL ASSERT
'DATA ACK'.
RESPONSE:
'DATA ACK' DIDN'T ASSERT
!
[2
!STIMULUS:
ASSERT AND NEGATE 'RESET'
RD 0 - TO NEGATE 'DATA ACK'
WRT 114/2 - SO 'R I/O DATA' WILL ASSERT
WRT 210/123 - ASSERTING 'BUS REQ' WILL ASSERT 'GRANT'
- ASSERTING 'CLOSE LATCHS' WILL NEGATE
'R CLK ENB'
- 'GRANT (1)' AND 'LATCH DATA (1)' WILL ASSERT
'LATCH DATA ENB (1)' WHICH IN TURN WILL
ASSERT 'R CLK ENB'
- 'R I/O DATA' WILL ASSERT 'RETURN DATA'
- 'RETURN DATA' AND 'LATCH DATA ENB (1)' WILL
ASSERT 'DATA ENB' WHICH IN TURN WILL NEGATE
'R CLK ENB'.
RESPONSE:
'R CLK ENB' DIDN'T NEGATE
!
]21
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
RD 0 - TO NEGATE 'DATA ACK'
WRT 114/1 - SO 'R DATA' WILL ASSERT
WRT 210/123 - ASSERTING 'BUS REQ' WILL ASSERT 'GRANT'
- 'GRANT (1)' AND 'LATCH DATA (1)' WILL ASSERT
'LATCH DATA ENB (1)'.
- WITH 'MEM' AND 'R I/O DATA' NEGATED, 'RETURN
DATA' SHOULD NOT ASSERT.
- WITH 'RETURN DATA' NEGATED, 'DATA ENB' WILL
NOT ASSERT AND THEREFORE 'DATA ACK' WILL NOT
ASSERT.
RESPONSE:
'DATA ACK' ASSERTED
!
[2
!STIMULUS:
ASSERT AND NEGATE 'RESET'
RD 0 - TO NEGATE 'DATA ACK'
WRT 114/1 - SO 'R DATA' WILL ASSERT
WRT 210/323 - ASSERTING 'BUS REQ' WILL ASSERT 'GRANT'
- ASSERTING 'CLOSE LATCHS' WILL NEGATE
'R CLK ENB'
- 'GRANT (1)' AND 'LATCH DATA (1)' WILL ASSERT
'LATCH DATA ENB (1)' WHICH IN TURN WILL
ASSERT 'R CLK ENB'
- WITH 'MEM' AND 'R I/O DATA' NEGATED, 'RETURN
DATA' SHOULD NOT ASSERT.
- WITH 'RETURN DATA' NEGATED, 'DATA ENB' WILL
NOT ASSERT AND THEREFORE 'R CLK ENB' WILL NOT
NEGATE.
RESPONSE:
'R CLK ENB' NEGATED
!
]22
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
RD 0 - TO NEGATE 'DATA ACK'
WRT 114/0 - SO 'R DATA' AND 'R I/O DATA' WILL NEGATE
WRT 210/123 - ASSERTING 'BUS REQ' WILL ASSERT 'GRANT'
- 'GRANT (1)' AND 'LATCH DATA (1)' WILL ASSERT
'LATCH DATA ENB (1)'.
- WITH 'R DATA' AND 'R I/O DATA' NEGATED,
'RETURN DATA' SHOULD NOT ASSERT.
- WITH 'RETURN DATA' NEGATED, 'DATA ENB' WILL
NOT ASSERT AND THEREFORE 'DATA ACK' WILL NOT
ASSERT.
RESPONSE:
'DATA ACK' ASSERTED
!
[2
!STIMULUS:
ASSERT AND NEGATE 'RESET'
RD 0 - TO NEGATE 'DATA ACK'
WRT 114/0 - SO 'R DATA' AND 'R I/O DATA' WILL NEGATE
WRT 210/323 - ASSERTING 'BUS REQ' WILL ASSERT 'GRANT'
- ASSERTING 'CLOSE LATCHS' WILL NEGATE
'R CLK ENB'
- 'GRANT (1)' AND 'LATCH DATA (1)' WILL ASSERT
'LATCH DATA ENB (1)' WHICH IN TURN WILL
ASSERT 'R CLK ENB'
- WITH 'R DATA' AND 'R I/O DATA' NEGATED,
'RETURN DATA' SHOULD NOT ASSERT.
- WITH 'RETURN DATA' NEGATED, 'DATA ENB' WILL
NOT ASSERT AND THEREFORE 'R CLK ENB' WILL NOT
NEGATE.
RESPONSE:
'R CLK ENB' NEGATED
!
]23
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
RD 0 - TO NEGATE 'DATA ACK'
WRT 114/2 - SO 'R I/O DATA' WILL ASSERT
WRT 210/123 - ASSERTING 'BUS REQ' WILL ASSERT 'GRANT'
- WITH 'LATCH DATA (1)' NEGATED, 'LATCH DATA
ENB (1)' WILL NOT ASSERT.
- 'R I/O DATA' WILL ASSERT 'RETURN DATA'
- WITH 'LATCH DATA ENB (1)' NEGATED, 'DATA ENB'
WILL NOT ASSERT AND THEREFORE 'DATA ACK' WILL
NOT ASSERT.
RESPONSE:
'DATA ACK' ASSERTED
!
]24
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 113/CORRECT DATA
WRT 112/CORRECT DATA COMPLEMENTED
WRT 210/141
RESPONSE:
'R DATA 00-03' DID NOT GET GATED ONTO THE BUS CORRECTLY.
!
]25
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 114/2 - LOAD BUFFER SO 'R I/O DATA' ASSERTS
WRT 112/CORRECT DATA
WRT 113/CORRECT DATA COMPLEMENTED
WRT 210/123 - ASSERTING 'BUS REQ' AND 'XMIT DATA
(1)' WILL ASSERT 'T ENB', 'T ENB A',
AND 'DATA CYCLE'. THIS GATES THE
CONTENTS OF THE DATA LOCATIONS ONTO
THE KS10 BUS.
- ASSERTING 'LATCH DATA (1)' WILL LATCH
THIS DATA IN THE 8646 TRANSCEIVERS.
RESPONSE:
'R DATA 00-03' DID NOT GET GATED ONTO THE BUS CORRECTLY.
!
]26
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 111/CORRECT DATA
WRT 110/CORRECT DATA COMPLEMENTED
WRT 210/141
RESPONSE:
'R DATA 04-11' DID NOT GET GATED ONTO THE BUS CORRECTLY.
!
]27
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 114/2 - LOAD BFFER SO 'R I/O DATA' ASSERTS
WRT 110/CORRECT DATA
WRT 111/CORRECT DATA COMPLEMENTED
WRT 210/123 - ASSERTING 'BUS REQ' AND 'XMIT DATA
(1)' WILL ASSERT 'T ENB', 'T ENB A',
AND 'DATA CYCLE'. THIS GATES THE
CONTENTS OF THE DATA LOCATIONS ONTO
THE KS10 BUS.
- ASSERTING 'LATCH DATA (1)' WILL LATCH
THIS DATA IN THE 8646 TRANSCEIVERS.
RESPONSE:
'R DATA 04-11' DID NOT GET GATED ONTO THE BUS CORRECTLY.
!
]28
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 107/CORRECT DATA
WRT 106/CORRECT DATA COMPLEMENTED
WRT 210/141
RESPONSE:
'R DATA 12-19' DID NOT GET GATED ONTO THE BUS CORRECTLY.
!
]29
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 114/2 - LOAD BFFER SO 'R I/O DATA' ASSERTS
WRT 106/CORRECT DATA
WRT 107/CORRECT DATA COMPLEMENTED
WRT 210/123 - ASSERTING 'BUS REQ' AND 'XMIT DATA
(1)' WILL ASSERT 'T ENB', 'T ENB A',
AND 'DATA CYCLE'. THIS GATES THE
CONTENTS OF THE DATA LOCATIONS ONTO
THE KS10 BUS.
- ASSERTING 'LATCH DATA (1)' WILL LATCH
THIS DATA IN THE 8646 TRANSCEIVERS.
RESPONSE:
'R DATA 12-19' DID NOT GET GATED ONTO THE BUS CORRECTLY.
!
]30
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 105/CORRECT DATA
WRT 104/CORRECT DATA COMPLEMENTED
WRT 210/141
RESPONSE:
'R DATA 20-27' DID NOT GET GATED ONTO THE BUS CORRECTLY.
!
]31
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 114/2 - LOAD BFFER SO 'R I/O DATA' ASSERTS
WRT 104/CORRECT DATA
WRT 105/CORRECT DATA COMPLEMENTED
WRT 210/123 - ASSERTING 'BUS REQ' AND 'XMIT DATA
(1)' WILL ASSERT 'T ENB', 'T ENB A',
AND 'DATA CYCLE'. THIS GATES THE
CONTENTS OF THE DATA LOCATIONS ONTO
THE KS10 BUS.
- ASSERTING 'LATCH DATA (1)' WILL LATCH
THIS DATA IN THE 8646 TRANSCEIVERS.
RESPONSE:
'R DATA 20-27' DID NOT GET GATED ONTO THE BUS CORRECTLY.
!
]32
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 103/CORRECT DATA
WRT 102/CORRECT DATA COMPLEMENTED
WRT 210/141
RESPONSE:
'R DATA 28-35' DID NOT GET GATED ONTO THE BUS CORRECTLY.
!
]33
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 114/2 - LOAD BFFER SO 'R I/O DATA' ASSERTS
WRT 102/CORRECT DATA
WRT 103/CORRECT DATA COMPLEMENTED
WRT 210/123 - ASSERTING 'BUS REQ' AND 'XMIT DATA
(1)' WILL ASSERT 'T ENB', 'T ENB A',
AND 'DATA CYCLE'. THIS GATES THE
CONTENTS OF THE DATA LOCATIONS ONTO
THE KS10 BUS.
- ASSERTING 'LATCH DATA (1)' WILL LATCH
THIS DATA IN THE 8646 TRANSCEIVERS.
RESPONSE:
'R DATA 28-35' DID NOT GET GATED ONTO THE BUS CORRECTLY.
!
]34
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 106/252 - PUT DATA INTO 'DATA' LOCATIONS
WRT 107/125 - PUT DATA INTO 'COM/ADR' LOCATIONS
WRT 210/1 - ASSERTING 'CLOSE LATCHS' WILL LATCH THE
TRANSMITTED DATA INTO 'R DATA 12-19'. IN THIS
CASE, THE 'T ENB' SIGNALS SHOULD BE NEGATED
AND ALL ZEROS SHOULD BE TRANSMITTED.
RESPONSE:
DATA FROM 'DATA' LOCATIONS GOT TRANSMITTED. THIS IMPLIES THAT
'T ENB', 'T ENB A', AND 'DATA CYCLE' WERE ALL ASSERTED WHEN
THEY SHOULDN'T HAVE BEEN.
!
[2
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 106/252 - PUT DATA INTO 'DATA' LOCATIONS
WRT 107/125 - PUT DATA INTO 'COM/ADR' LOCATIONS
WRT 210/1 - ASSERTING 'CLOSE LATCHS' WILL LATCH THE
TRANSMITTED DATA INTO 'R DATA 12-19'. IN THIS
CASE, THE 'T ENB' SIGNALS SHOULD BE NEGATED
AND ALL ZEROS SHOULD BE TRANSMITTED.
RESPONSE:
DATA FROM 'COM/ADR' LOCATIONS GOT TRANSMITTED. THIS IMPLIES
THAT 'T ENB' AND 'T ENB A' WERE ASSERTED WHEN THEY SHOULDN'T
HAVE BEEN.
!
[3
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 106/252 - PUT DATA INTO 'DATA' LOCATIONS
WRT 107/125 - PUT DATA INTO 'COM/ADR' LOCATIONS
WRT 210/1 - ASSERTING 'CLOSE LATCHS' WILL LATCH THE
TRANSMITTED DATA INTO 'R DATA 12-19'. IN THIS
CASE, THE 'T ENB' SIGNALS SHOULD BE NEGATED
AND ALL ZEROS SHOULD BE TRANSMITTED.
RESPONSE:
DATA FROM 'COM/ADR' LOCATIONS GOT TRANSMITTED TO 'R DATA 12-15'.
THIS IMPLIES THAT 'T ENB' WAS INCORRECTLY ASSERTED.
!
[4
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 106/252 - PUT DATA INTO 'DATA' LOCATIONS
WRT 107/125 - PUT DATA INTO 'COM/ADR' LOCATIONS
WRT 210/1 - ASSERTING 'CLOSE LATCHS' WILL LATCH THE
TRANSMITTED DATA INTO 'R DATA 12-19'. IN THIS
CASE, THE 'T ENB' SIGNALS SHOULD BE NEGATED
AND ALL ZEROS SHOULD BE TRANSMITTED.
RESPONSE:
DATA FROM 'COM/ADR' LOCATIONS GOT TRANSMITTED TO 'R DATA 16-19'.
THIS IMPLIES THAT 'T ENB A' WAS INCORRECTLY ASSERTED.
!
]35
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 106/252 - PUT DATA INTO 'DATA' LOCATIONS
WRT 107/125 - PUT DATA INTO 'COM/ADR' LOCATIONS
WRT 210/2 - 'BUS REQ' WILL ASSERT 'GRANT
ASSERTING 'CLOSE LATCHS' WILL LATCH THE
TRANSMITTED DATA INTO 'R DATA 12-19'. IN THIS
CASE, THE 'T ENB' SIGNALS SHOULD BE NEGATED
AND ALL ZEROS SHOULD BE TRANSMITTED.
RESPONSE:
DATA FROM 'DATA' LOCATIONS GOT TRANSMITTED. THIS IMPLIES THAT
'T ENB', 'T ENB A', AND 'DATA CYCLE' WERE ALL ASSERTED WHEN
THEY SHOULDN'T HAVE BEEN.
!
[2
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 106/252 - PUT DATA INTO 'DATA' LOCATIONS
WRT 107/125 - PUT DATA INTO 'COM/ADR' LOCATIONS
WRT 210/2 - 'BUS REQ' WILL ASSERT 'GRANT
ASSERTING 'CLOSE LATCHS' WILL LATCH THE
TRANSMITTED DATA INTO 'R DATA 12-19'. IN THIS
CASE, THE 'T ENB' SIGNALS SHOULD BE NEGATED
AND ALL ZEROS SHOULD BE TRANSMITTED.
RESPONSE:
DATA FROM 'COM/ADR' LOCATIONS GOT TRANSMITTED. THIS IMPLIES
THAT 'T ENB' AND 'T ENB A' WERE ASSERTED WHEN THEY SHOULDN'T
HAVE BEEN.
!
[3
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 106/252 - PUT DATA INTO 'DATA' LOCATIONS
WRT 107/125 - PUT DATA INTO 'COM/ADR' LOCATIONS
WRT 210/2 - 'BUS REQ' WILL ASSERT 'GRANT
ASSERTING 'CLOSE LATCHS' WILL LATCH THE
TRANSMITTED DATA INTO 'R DATA 12-19'. IN THIS
CASE, THE 'T ENB' SIGNALS SHOULD BE NEGATED
AND ALL ZEROS SHOULD BE TRANSMITTED.
RESPONSE:
DATA FROM 'COM/ADR' LOCATIONS GOT TRANSMITTED TO 'R DATA 12-15'.
THIS IMPLIES THAT 'T ENB' WAS INCORRECTLY ASSERTED.
!
[4
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 106/252 - PUT DATA INTO 'DATA' LOCATIONS
WRT 107/125 - PUT DATA INTO 'COM/ADR' LOCATIONS
WRT 210/2 - 'BUS REQ' WILL ASSERT 'GRANT
ASSERTING 'CLOSE LATCHS' WILL LATCH THE
TRANSMITTED DATA INTO 'R DATA 12-19'. IN THIS
CASE, THE 'T ENB' SIGNALS SHOULD BE NEGATED
AND ALL ZEROS SHOULD BE TRANSMITTED.
RESPONSE:
DATA FROM 'COM/ADR' LOCATIONS GOT TRANSMITTED TO 'R DATA 16-19'.
THIS IMPLIES THAT 'T ENB A' WAS INCORRECTLY ASSERTED.
!
]36
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 106/252 - PUT DATA INTO 'DATA' LOCATIONS
WRT 107/125 - PUT DATA INTO 'COM/ADR' LOCATIONS
WRT 210/20 - ASSERT 'XMIT DATA (1)'
WRT 210/21 - ASSERTING 'CLOSE LATCHS' WILL LATCH THE
TRANSMITTED DATA INTO 'R DATA 12-19'. IN THIS
CASE, THE 'T ENB' SIGNALS SHOULD BE NEGATED
SINCE 'GRANT' WILL NOT GET ASSERTED. SO
ALL ZEROS SHOULD BE TRANSMITTED.
RESPONSE:
DATA FROM 'DATA' LOCATIONS GOT TRANSMITTED. THIS IMPLIES THAT
'T ENB', 'T ENB A', AND 'DATA CYCLE' WERE ALL ASSERTED WHEN
THEY SHOULDN'T HAVE BEEN.
!
[2
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 106/252 - PUT DATA INTO 'DATA' LOCATIONS
WRT 107/125 - PUT DATA INTO 'COM/ADR' LOCATIONS
WRT 210/20 - ASSERT 'XMIT DATA (1)'
WRT 210/21 - ASSERTING 'CLOSE LATCHS' WILL LATCH THE
TRANSMITTED DATA INTO 'R DATA 12-19'. IN THIS
CASE, THE 'T ENB' SIGNALS SHOULD BE NEGATED
SINCE 'GRANT' WILL NOT GET ASSERTED. SO
ALL ZEROS SHOULD BE TRANSMITTED.
RESPONSE:
DATA FROM 'COM/ADR' LOCATIONS GOT TRANSMITTED. THIS IMPLIES
THAT 'T ENB' AND 'T ENB A' WERE ASSERTED WHEN THEY SHOULDN'T
HAVE BEEN.
!
[3
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 106/252 - PUT DATA INTO 'DATA' LOCATIONS
WRT 107/125 - PUT DATA INTO 'COM/ADR' LOCATIONS
WRT 210/20 - ASSERT 'XMIT DATA (1)'
WRT 210/21 - ASSERTING 'CLOSE LATCHS' WILL LATCH THE
TRANSMITTED DATA INTO 'R DATA 12-19'. IN THIS
CASE, THE 'T ENB' SIGNALS SHOULD BE NEGATED
SINCE 'GRANT' WILL NOT GET ASSERTED. SO
ALL ZEROS SHOULD BE TRANSMITTED.
RESPONSE:
DATA FROM 'COM/ADR' LOCATIONS GOT TRANSMITTED TO 'R DATA 12-15'.
THIS IMPLIES THAT 'T ENB' WAS INCORRECTLY ASSERTED.
!
[4
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 106/252 - PUT DATA INTO 'DATA' LOCATIONS
WRT 107/125 - PUT DATA INTO 'COM/ADR' LOCATIONS
WRT 210/20 - ASSERT 'XMIT DATA (1)'
WRT 210/21 - ASSERTING 'CLOSE LATCHS' WILL LATCH THE
TRANSMITTED DATA INTO 'R DATA 12-19'. IN THIS
CASE, THE 'T ENB' SIGNALS SHOULD BE NEGATED
SINCE 'GRANT' WILL NOT GET ASSERTED. SO
ALL ZEROS SHOULD BE TRANSMITTED.
RESPONSE:
DATA FROM 'COM/ADR' LOCATIONS GOT TRANSMITTED TO 'R DATA 16-19'.
THIS IMPLIES THAT 'T ENB A' WAS INCORRECTLY ASSERTED.
!
]37
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 106/252 - PUT DATA INTO 'DATA' LOCATIONS
WRT 107/125 - PUT DATA INTO 'COM/ADR' LOCATIONS
WRT 210/20 - ASSERT 'XMIT ADR (1)'
WRT 210/21 - ASSERTING 'CLOSE LATCHS' WILL LATCH THE
TRANSMITTED DATA INTO 'R DATA 12-19'. IN THIS
CASE, THE 'T ENB' SIGNALS SHOULD BE NEGATED
SINCE 'GRANT' WILL NOT GET ASSERTED. SO
ALL ZEROS SHOULD BE TRANSMITTED.
RESPONSE:
DATA FROM 'DATA' LOCATIONS GOT TRANSMITTED. THIS IMPLIES THAT
'T ENB', 'T ENB A', AND 'DATA CYCLE' WERE ALL ASSERTED WHEN
THEY SHOULDN'T HAVE BEEN.
!
[2
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 106/252 - PUT DATA INTO 'DATA' LOCATIONS
WRT 107/125 - PUT DATA INTO 'COM/ADR' LOCATIONS
WRT 210/20 - ASSERT 'XMIT ADR (1)'
WRT 210/21 - ASSERTING 'CLOSE LATCHS' WILL LATCH THE
TRANSMITTED DATA INTO 'R DATA 12-19'. IN THIS
CASE, THE 'T ENB' SIGNALS SHOULD BE NEGATED
SINCE 'GRANT' WILL NOT GET ASSERTED. SO
ALL ZEROS SHOULD BE TRANSMITTED.
RESPONSE:
DATA FROM 'COM/ADR' LOCATIONS GOT TRANSMITTED. THIS IMPLIES
THAT 'T ENB' AND 'T ENB A' WERE ASSERTED WHEN THEY SHOULDN'T
HAVE BEEN.
!
[3
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 106/252 - PUT DATA INTO 'DATA' LOCATIONS
WRT 107/125 - PUT DATA INTO 'COM/ADR' LOCATIONS
WRT 210/20 - ASSERT 'XMIT ADR (1)'
WRT 210/21 - ASSERTING 'CLOSE LATCHS' WILL LATCH THE
TRANSMITTED DATA INTO 'R DATA 12-19'. IN THIS
CASE, THE 'T ENB' SIGNALS SHOULD BE NEGATED
SINCE 'GRANT' WILL NOT GET ASSERTED. SO
ALL ZEROS SHOULD BE TRANSMITTED.
RESPONSE:
DATA FROM 'COM/ADR' LOCATIONS GOT TRANSMITTED TO 'R DATA 12-15'.
THIS IMPLIES THAT 'T ENB' WAS INCORRECTLY ASSERTED.
!
[4
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 106/252 - PUT DATA INTO 'DATA' LOCATIONS
WRT 107/125 - PUT DATA INTO 'COM/ADR' LOCATIONS
WRT 210/20 - ASSERT 'XMIT ADR (1)'
WRT 210/21 - ASSERTING 'CLOSE LATCHS' WILL LATCH THE
TRANSMITTED DATA INTO 'R DATA 12-19'. IN THIS
CASE, THE 'T ENB' SIGNALS SHOULD BE NEGATED
SINCE 'GRANT' WILL NOT GET ASSERTED. SO
ALL ZEROS SHOULD BE TRANSMITTED.
RESPONSE:
DATA FROM 'COM/ADR' LOCATIONS GOT TRANSMITTED TO 'R DATA 16-19'.
THIS IMPLIES THAT 'T ENB A' WAS INCORRECTLY ASSERTED.
!
]38
[1
!STIMULUS:
WRT 210/1 - ASSERT 'CLOSE LATCHS' TO NEGATE 'STATUS RD (1)'
ASSERT AND NEGATE 'RESET'
WRT 107/1 - ASSERT 'R DATA 19' IN COM/ADR LOC
WRT 106/1 - ASSERT 'R DATA 19' IN DATA LOC
WRT 113/10 - ASSERT 'R DATA 00' IN COM/ADR LOC
WRT 112/10 - ASSERT 'R DATA 00' IN DATA LOC
WRT 115/4 - ASSERT 'R COM/ADR' IN COM/ADR LOC
WRT 114/4 - ASSERT 'R COM/ADR' IN DATA LOC
WRT 110/63 - PUT TEST DATA IN BUFFER
WRT 111/0 - NEGATE 'R DATA 4-11' IN COM/ADR LOCS
STOP CLOCK AND SYNC IT SO T-CLK AND R-CLK ARE NEGATED.
WRT 210/140 - ASSERT 'BUS REQ' AND 'XMIT ADR (1)'
GENERATE 5 T-CLK/R-CLK CYCLES - THE 2ND CYCLE WILL ASSERT
'T ENB' AND 'T ENB A'. THE 3RD CYCLE WILL
CLOCK THE DATA FROM THE COM/ADR LOCS ONTO THE
BUS AND INTO THE RECEIVERS. THE 4TH CYCLE
WILL ASSERT 'STATUS RD (1)', WHICH WILL ASSERT
'T ENB', 'T ENB A' AND 'DATA CYCLE'. THE 5TH
CYCLE SHOULD CLOCK THE DATA FROM THE DATA
LOCS ONTO THE BUS AND INTO THE RECEIVERS.
RESPONSE:
'R DATA 04-11' IS NOT THE TEST DATA. THIS IMPLIES THAT
'STATUS RD (1)' IS NOT ASSERTED.
!
]39
[1
!STIMULUS:
WRT 210/1 - ASSERT 'CLOSE LATCHS' TO NEGATE 'STATUS RD (1)'
ASSERT AND NEGATE 'RESET'
WRT 107/0 - NEGATE 'R DATA 19' IN COM/ADR LOC
WRT 106/0 - NEGATE 'R DATA 19' IN DATA LOC
WRT 113/10 - ASSERT 'R DATA 00' IN COM/ADR LOC
WRT 112/10 - ASSERT 'R DATA 00' IN DATA LOC
WRT 115/4 - ASSERT 'R COM/ADR' IN COM/ADR LOC
WRT 114/4 - ASSERT 'R COM/ADR' IN DATA LOC
WRT 110/63 - PUT TEST DATA IN BUFFER
WRT 111/0 - NEGATE 'R DATA 4-11' IN COM/ADR LOCS
STOP CLOCK AND SYNC IT SO T-CLK AND R-CLK ARE NEGATED.
WRT 210/140 - ASSERT 'BUS REQ' AND 'XMIT ADR (1)'
GENERATE 5 T-CLK/R-CLK CYCLES - THE 2ND CYCLE WILL ASSERT
'T ENB' AND 'T ENB A'. THE 3RD CYCLE WILL
CLOCK THE DATA FROM THE COM/ADR LOCS ONTO THE
BUS AND INTO THE RECEIVERS. WITH 'R DATA 19'
NEGATED, 'STATUS RD (1)' WILL NOT ASSERT ON
THE 4TH CYCLE. SO ON THE 5TH CYCLE THE DATA
FROM THE DATA LOCS SHOULD NOT GET TRANSMITTED
ONTO THE BUS AND INTO THE RECEIVERS.
RESPONSE:
'R DATA 04-11' IS THE TEST DATA. THIS IMPLIES THAT
'STATUS RD (1)' IS ASSERTED.
!
]40
[1
!STIMULUS:
WRT 210/1 - ASSERT 'CLOSE LATCHS' TO NEGATE 'STATUS RD (1)'
ASSERT AND NEGATE 'RESET'
WRT 107/1 - ASSERT 'R DATA 19' IN COM/ADR LOC
WRT 106/1 - ASSERT 'R DATA 19' IN DATA LOC
WRT 113/0 - NEGATE 'R DATA 00' IN COM/ADR LOC
WRT 112/0 - NEGATE 'R DATA 00' IN DATA LOC
WRT 115/4 - ASSERT 'R COM/ADR' IN COM/ADR LOC
WRT 114/4 - ASSERT 'R COM/ADR' IN DATA LOC
WRT 110/63 - PUT TEST DATA IN BUFFER
WRT 111/0 - NEGATE 'R DATA 4-11' IN COM/ADR LOCS
STOP CLOCK AND SYNC IT SO T-CLK AND R-CLK ARE NEGATED.
WRT 210/140 - ASSERT 'BUS REQ' AND 'XMIT ADR (1)'
GENERATE 5 T-CLK/R-CLK CYCLES - THE 2ND CYCLE WILL ASSERT
'T ENB' AND 'T ENB A'. THE 3RD CYCLE WILL
CLOCK THE DATA FROM THE COM/ADR LOCS ONTO THE
BUS AND INTO THE RECEIVERS. WITH 'R DATA 00'
NEGATED, 'STATUS RD (1)' WILL NOT ASSERT ON
THE 4TH CYCLE. SO ON THE 5TH CYCLE THE DATA
FROM THE DATA LOCS SHOULD NOT GET TRANSMITTED
ONTO THE BUS AND INTO THE RECEIVERS.
RESPONSE:
'R DATA 04-11' IS THE TEST DATA. THIS IMPLIES THAT
'STATUS RD (1)' IS ASSERTED.
!
]41
[1
!STIMULUS:
WRT 210/1 - ASSERT 'CLOSE LATCHS' TO NEGATE 'STATUS RD (1)'
ASSERT AND NEGATE 'RESET'
WRT 107/1 - ASSERT 'R DATA 19' IN COM/ADR LOC
WRT 106/1 - ASSERT 'R DATA 19' IN DATA LOC
WRT 113/10 - ASSERT 'R DATA 00' IN COM/ADR LOC
WRT 112/10 - ASSERT 'R DATA 00' IN DATA LOC
WRT 115/0 - NEGATE 'R COM/ADR' IN COM/ADR LOC
WRT 114/0 - NEGATE 'R COM/ADR' IN DATA LOC
WRT 110/63 - PUT TEST DATA IN BUFFER
WRT 111/0 - NEGATE 'R DATA 4-11' IN COM/ADR LOCS
STOP CLOCK AND SYNC IT SO T-CLK AND R-CLK ARE NEGATED.
WRT 210/140 - ASSERT 'BUS REQ' AND 'XMIT ADR (1)'
GENERATE 5 T-CLK/R-CLK CYCLES - THE 2ND CYCLE WILL ASSERT
'T ENB' AND 'T ENB A'. THE 3RD CYCLE WILL
CLOCK THE DATA FROM THE COM/ADR LOCS ONTO THE
BUS AND INTO THE RECEIVERS. WITH 'R COM/ADR'
NEGATED, 'STATUS RD (1)' WILL NOT ASSERT ON
THE 4TH CYCLE. SO ON THE 5TH CYCLE THE DATA
FROM THE DATA LOCS SHOULD NOT GET TRANSMITTED
ONTO THE BUS AND INTO THE RECEIVERS.
RESPONSE:
'R DATA 04-11' IS THE TEST DATA. THIS IMPLIES THAT
'STATUS RD (1)' IS ASSERTED.
!
]42
[1
!STIMULUS:
WRT 210/1 - ASSERT 'CLOSE LATCHS' TO NEGATE 'STATUS RD (1)'
ASSERT AND NEGATE 'RESET'
WRT 107/41 - ASSERT 'R DATA 14 AND 19' IN COM/ADR LOC
WRT 106/41 - ASSERT 'R DATA 14 AND 19' IN DATA LOC
WRT 113/10 - ASSERT 'R DATA 00' IN COM/ADR LOC
WRT 112/10 - ASSERT 'R DATA 00' IN DATA LOC
WRT 115/4 - ASSERT 'R COM/ADR' IN COM/ADR LOC
WRT 114/4 - ASSERT 'R COM/ADR' IN DATA LOC
WRT 110/63 - PUT TEST DATA IN BUFFER
WRT 111/0 - NEGATE 'R DATA 4-11' IN COM/ADR LOCS
STOP CLOCK AND SYNC IT SO T-CLK AND R-CLK ARE NEGATED.
WRT 210/140 - ASSERT 'BUS REQ' AND 'XMIT ADR (1)'
GENERATE 5 T-CLK/R-CLK CYCLES - THE 2ND CYCLE WILL ASSERT
'T ENB' AND 'T ENB A'. THE 3RD CYCLE WILL
CLOCK THE DATA FROM THE COM/ADR LOCS ONTO THE
BUS AND INTO THE RECEIVERS. WITH 'R DATA 14'
ASSERTED, 'STATUS RD (1)' WILL NOT ASSERT ON
THE 4TH CYCLE. SO ON THE 5TH CYCLE THE DATA
FROM THE DATA LOCS SHOULD NOT GET TRANSMITTED
ONTO THE BUS AND INTO THE RECEIVERS.
RESPONSE:
'R DATA 04-11' IS THE TEST DATA. THIS IMPLIES THAT
'STATUS RD (1)' IS ASSERTED.
!
]43
[1
!STIMULUS:
WRT 210/1 - ASSERT 'CLOSE LATCHS' TO NEGATE 'STATUS RD (1)'
ASSERT AND NEGATE 'RESET'
WRT 107/21 - ASSERT 'R DATA 15 AND 19' IN COM/ADR LOC
WRT 106/21 - ASSERT 'R DATA 15 AND 19' IN DATA LOC
WRT 113/10 - ASSERT 'R DATA 00' IN COM/ADR LOC
WRT 112/10 - ASSERT 'R DATA 00' IN DATA LOC
WRT 115/4 - ASSERT 'R COM/ADR' IN COM/ADR LOC
WRT 114/4 - ASSERT 'R COM/ADR' IN DATA LOC
WRT 110/63 - PUT TEST DATA IN BUFFER
WRT 111/0 - NEGATE 'R DATA 4-11' IN COM/ADR LOCS
STOP CLOCK AND SYNC IT SO T-CLK AND R-CLK ARE NEGATED.
WRT 210/140 - ASSERT 'BUS REQ' AND 'XMIT ADR (1)'
GENERATE 5 T-CLK/R-CLK CYCLES - THE 2ND CYCLE WILL ASSERT
'T ENB' AND 'T ENB A'. THE 3RD CYCLE WILL
CLOCK THE DATA FROM THE COM/ADR LOCS ONTO THE
BUS AND INTO THE RECEIVERS. WITH 'R DATA 15'
ASSERTED, 'STATUS RD (1)' WILL NOT ASSERT ON
THE 4TH CYCLE. SO ON THE 5TH CYCLE THE DATA
FROM THE DATA LOCS SHOULD NOT GET TRANSMITTED
ONTO THE BUS AND INTO THE RECEIVERS.
RESPONSE:
'R DATA 04-11' IS THE TEST DATA. THIS IMPLIES THAT
'STATUS RD (1)' IS ASSERTED.
!
]44
[1
!STIMULUS:
WRT 210/1 - ASSERT 'CLOSE LATCHS' TO NEGATE 'STATUS RD (1)'
ASSERT AND NEGATE 'RESET'
WRT 107/11 - ASSERT 'R DATA 16 AND 19' IN COM/ADR LOC
WRT 106/11 - ASSERT 'R DATA 16 AND 19' IN DATA LOC
WRT 113/10 - ASSERT 'R DATA 00' IN COM/ADR LOC
WRT 112/10 - ASSERT 'R DATA 00' IN DATA LOC
WRT 115/4 - ASSERT 'R COM/ADR' IN COM/ADR LOC
WRT 114/4 - ASSERT 'R COM/ADR' IN DATA LOC
WRT 110/63 - PUT TEST DATA IN BUFFER
WRT 111/0 - NEGATE 'R DATA 4-11' IN COM/ADR LOCS
STOP CLOCK AND SYNC IT SO T-CLK AND R-CLK ARE NEGATED.
WRT 210/140 - ASSERT 'BUS REQ' AND 'XMIT ADR (1)'
GENERATE 5 T-CLK/R-CLK CYCLES - THE 2ND CYCLE WILL ASSERT
'T ENB' AND 'T ENB A'. THE 3RD CYCLE WILL
CLOCK THE DATA FROM THE COM/ADR LOCS ONTO THE
BUS AND INTO THE RECEIVERS. WITH 'R DATA 16'
ASSERTED, 'STATUS RD (1)' WILL NOT ASSERT ON
THE 4TH CYCLE. SO ON THE 5TH CYCLE THE DATA
FROM THE DATA LOCS SHOULD NOT GET TRANSMITTED
ONTO THE BUS AND INTO THE RECEIVERS.
RESPONSE:
'R DATA 04-11' IS THE TEST DATA. THIS IMPLIES THAT
'STATUS RD (1)' IS ASSERTED.
!
]45
[1
!STIMULUS:
WRT 210/1 - ASSERT 'CLOSE LATCHS' TO NEGATE 'STATUS RD (1)'
ASSERT AND NEGATE 'RESET'
WRT 107/5 - ASSERT 'R DATA 17 AND 19' IN COM/ADR LOC
WRT 106/5 - ASSERT 'R DATA 17 AND 19' IN DATA LOC
WRT 113/10 - ASSERT 'R DATA 00' IN COM/ADR LOC
WRT 112/10 - ASSERT 'R DATA 00' IN DATA LOC
WRT 115/4 - ASSERT 'R COM/ADR' IN COM/ADR LOC
WRT 114/4 - ASSERT 'R COM/ADR' IN DATA LOC
WRT 110/63 - PUT TEST DATA IN BUFFER
WRT 111/0 - NEGATE 'R DATA 4-11' IN COM/ADR LOCS
STOP CLOCK AND SYNC IT SO T-CLK AND R-CLK ARE NEGATED.
WRT 210/140 - ASSERT 'BUS REQ' AND 'XMIT ADR (1)'
GENERATE 5 T-CLK/R-CLK CYCLES - THE 2ND CYCLE WILL ASSERT
'T ENB' AND 'T ENB A'. THE 3RD CYCLE WILL
CLOCK THE DATA FROM THE COM/ADR LOCS ONTO THE
BUS AND INTO THE RECEIVERS. WITH 'R DATA 17'
ASSERTED, 'STATUS RD (1)' WILL NOT ASSERT ON
THE 4TH CYCLE. SO ON THE 5TH CYCLE THE DATA
FROM THE DATA LOCS SHOULD NOT GET TRANSMITTED
ONTO THE BUS AND INTO THE RECEIVERS.
RESPONSE:
'R DATA 04-11' IS THE TEST DATA. THIS IMPLIES THAT
'STATUS RD (1)' IS ASSERTED.
!
]46
[1
!STIMULUS:
WRT 210/1 - MAKE SURE 'STATUS RD (1)' IS NEGATED
ASSERT AND NEGATE 'RESET'
WRT 107/1 - ASSERT 'R DATA 19' IN COM/ADR LOC
WRT 106/1 - ASSERT 'R DATA 19' IN DATA LOC
WRT 113/10 - ASSERT 'R DATA 00' IN COM/ADR LOC
WRT 112/10 - ASSERT 'R DATA 00' IN DATA LOC
WRT 115/4 - ASSERT 'R COM/ADR' IN COM/ADR LOC
WRT 114/4 - ASSERT 'R COM/ADR' IN DATA LOC
WRT 110/0 - NEGATE 'R DATA 4-11' IN DATA LOCS
WRT 111/0 - NEGATE 'R DATA 4-11' IN COM/ADR LOCS
STOP CLOCK AND SYNC IT SO T-CLK AND R-CLK ARE NEGATED
WRT 210/120 - ASSERT 'BUS REQ' AND 'XMIT ADR (1)'.
GENERATE 5 T-CLK/R-CLK CYCLES - THE 2ND CYCLE WILL ASSERT
'T ENB' AND 'T ENB A'. THE 3RD CYCLE WILL
CLOCK THE DATA FROM THE COM/ADR LOCS ONTO THE
BUS AND INTO THE RECEIVERS. THE 4TH CYCLE
WILL ASSERT 'STATUS RD (1)', WHICH WILL ASSERT
'T ENB', 'T ENB A' AND 'DATA CYCLE'. THE 5TH
CYCLE SHOULD CLOCK THE DATA FROM THE DATA
LOCS ONTO THE BUS AND INTO THE RECEIVERS.
WRT 210/1 - ASSERT 'CLOSE LATCHS'
GENERATE 4 T-CLK/R-CLK CYCLES - THE 2ND CYCLE ASSERTS FLOP E418
WHICH SHOULD NEGATE 'STATUS RD (1)'. THIS
WILL NEGATE 'T ENB','T ENB A' AND 'DATA CYCLE'
ON THE 4TH CYCLE ZEROS SHOULD GET CLOCKED ONTO
THE BUS AND INTO THE RECEIVERS.
RESPONSE:
'R COM/ADR' DIDN'T NEGATE. THIS IMPLIES THAT 'T ENB',
'T ENB A' AND 'DATA CYCLE' DID NOT NEGATE, WHICH IN TURN
IMPLIES THAT 'STATUS RD (1)' DID NOT NEGATE.
!
]47
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 103/252 - SETUP DATA TO BE TRANSMITTED
WRT 210/144 - ASSERTING 'BUS REQ' ASSERTS 'GRANT'
AND 'GRANT (1)'.
- 'GRANT' AND 'XMIT ADR (1)' WILL CAUSE
THE TEST DATA TO BE GATED ONTO THE
KS10 BUS.
- 'GRANT (1)' AND 'CRA R CLK' WILL CAUSE
THE TEST DATA TO BE LATCHED INTO THE
TRANSCEIVERS ON THE CRA BOARD.
WRT 205/11 - SET DIAG FUNCTION BITS = 11
WRT 210/115 - ASSERTING 'BUS REQ' ASSERTS 'GRANT'
- 'GRANT' AND 'CRA T CLK ENB(1)' WILL
ASSERT 'CRA T CLK ENABLE' WHICH WILL
GATE THE CRA TRANSCEIVER DATA ONTO THE
KS10 BUS.
- 'CLOSE LATCHS' WILL LATCH THAT DATA IN
THE CSL TRANSCEIVERS.
RESPONSE:
THE DATA LATCHED IN THE CSL TRANSCEIVERS FOR DATA BITS 28-35
(ER 0) IS NOT WHAT WAS TRANSMITTED. EITHER 'CRA R CLK #20'
OR 'CRA T CLK ENABLE' DID NOT ASSERT PROPERLY, OR THE DIAG FN
BITS DID NOT GET SET CORRECTLY.
!
]48
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 103/252 - SETUP DATA TO BE TRANSMITTED
WRT 210/144 - ASSERTING 'BUS REQ' ASSERTS 'GRANT'
AND 'GRANT (1)'.
- 'GRANT' AND 'XMIT ADR (1)' WILL CAUSE
THE TEST DATA TO BE GATED ONTO THE
KS10 BUS.
- 'GRANT (1)' AND 'CRA R CLK' WILL CAUSE
THE TEST DATA TO BE LATCHED INTO THE
TRANSCEIVERS ON THE CRA BOARD.
WRT 205/11 - SET DIAG FUNCTION BITS = 11
WRT 210/111 - 'CRA T CLK ENB (1)' AND 'GRANT'
ASSERT 'CRA T CLK ENABLE'. WITHOUT
'CRA R CLK', 'CRA T CLK C' SHOULD NOT
ASSERT AND ALL ZEROS WILL BE PLACED ON
THE KS10 BUS.
- 'CLOSE LATCHS' WILL LATCH THAT DATA IN
THE CSL TRANSCEIVERS.
RESPONSE:
THE DATA LATCHED IN THE CSL TRANSCEIVERS FOR DATA BITS 28-35
(ER 0) IS WHAT WAS TRANSMITTED. THIS MEANS THAT 'CRA R CLK #20'
ASSERTED WITHOUT 'CRA R CLK' BEING ASSERTED.
!
]49
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 103/252 - SETUP DATA TO BE TRANSMITTED
WRT 210/144 - ASSERTING 'BUS REQ' ASSERTS 'GRANT'
AND 'GRANT (1)'.
- 'GRANT' AND 'XMIT ADR (1)' WILL CAUSE
THE TEST DATA TO BE GATED ONTO THE
KS10 BUS.
- 'GRANT (1)' AND 'CRA R CLK' WILL CAUSE
THE TEST DATA TO BE LATCHED INTO THE
TRANSCEIVERS ON THE CRA BOARD.
WRT 205/11 - SET DIAG FUNCTION BITS = 11
WRT 210/105 - 'GRANT' ALONE SHOULD NOT
NOT ASSERT 'CRA T CLK ENABLE'. SO ALL
ZEROS SHOULD BE ON THE KS10 BUS.
- 'CLOSE LATCHS' WILL LATCH THAT DATA IN
THE CSL TRANSCEIVERS.
RESPONSE:
THE DATA LATCHED IN THE CSL TRANSCEIVERS FOR DATA BITS 28-35
(ER 0) IS WHAT WAS TRANSMITTED. THIS MEANS THAT 'CRA T CLK
ENABLE' GOT ASSERTED WITHOUT 'CRA T CLK ENB (1)' BEING ASSERTED.
!
]50
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 103/125 - PUT DATA INTO CSL I/O BUFFER
WRT 210/144 - CLOCK DATA INTO CRA BOARD TRANSCEIVERS
WRT 205/0 - SET DIAG FN BITS = 0
WRT 204/40 - ASSERT 'CRAM WRITE'. THIS SHOULD
CAUSE THE DATA TO BE WRITTEN INTO THE
CRAM BITS 0-11.
WRT 204/0 - NEGATE 'CRAM WRITE'
WRT 206/2 - ASSERT 'SINGLE CLK (1)'. THIS SHOULD
CLOCK THE RAM DATA INTO CRA LATCHES.
WRT 210/115 - CLOCK THE RAM DATA INTO THE CSL TRANS-
CEIVERS.
RESPONSE:
THE RAM DATA READ BACK WAS NOT WHAT SHOULD HAVE BEEN WRITTEN.
THIS MEANS THAT EITHER THE DIAG FN BITS, THE 'CRAM WRITE'
SIGNAL OR THE 'CRA/M RESET' SIGNAL ARE FAULTY.
!
]51
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 103/252 - PUT DATA INTO CSL I/O BUFFER
WRT 210/144 - CLOCK DATA INTO CRA BOARD TRANSCEIVERS
WRT 205/1 - SET DIAG FN BITS = 1
WRT 204/40 - ASSERT 'CRAM WRITE'. THIS SHOULD
CAUSE THE DATA TO BE WRITTEN INTO THE
CRAM BITS 12-23.
WRT 204/0 - NEGATE 'CRAM WRITE'
WRT 206/2 - ASSERT 'SINGLE CLK (1)'. THIS SHOULD
CLOCK THE RAM DATA INTO CRA LATCHES.
WRT 205/4 - SET DIAG FN = 4 TO READ BACK CRAM
BITS 12-23.
WRT 210/115 - CLOCK THE RAM DATA INTO THE CSL TRANS-
CEIVERS.
RESPONSE:
THE RAM DATA READ BACK WAS NOT WHAT SHOULD HAVE BEEN WRITTEN.
THIS MEANS THAT EITHER THE DIAG FN BITS, THE 'CRAM WRITE'
SIGNAL OR THE 'CRA/M RESET' SIGNAL ARE FAULTY.
!
]52
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 103/125 - PUT DATA INTO CSL I/O BUFFER
WRT 210/144 - CLOCK DATA INTO CRA BOARD TRANSCEIVERS
WRT 205/2 - SET DIAG FN BITS = 2
WRT 204/40 - ASSERT 'CRAM WRITE'. THIS SHOULD
CAUSE THE DATA TO BE WRITTEN INTO THE
CRAM BITS 24-35.
WRT 204/0 - NEGATE 'CRAM WRITE'
WRT 206/2 - ASSERT 'SINGLE CLK (1)'. THIS SHOULD
CLOCK THE RAM DATA INTO CRA LATCHES.
WRT 205/5 - SET DIAG FN = 5 TO READ BACK CRAM
BITS 24-35.
WRT 210/115 - CLOCK THE RAM DATA INTO THE CSL TRANS-
CEIVERS.
RESPONSE:
THE RAM DATA READ BACK WAS NOT WHAT SHOULD HAVE BEEN WRITTEN.
THIS MEANS THAT EITHER THE DIAG FN BITS, THE 'CRAM WRITE'
SIGNAL OR THE 'CRA/M RESET' SIGNAL ARE FAULTY.
!
]53
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 103/777 - PUT DATA INTO CSL I/O BUFFER
WRT 210/144 - CLOCK DATA INTO CRA BOARD TRANSCEIVERS
WRT 205/0 - SET DIAG FN BITS = 0
WRT 204/40 - ASSERT 'CRAM WRITE'. THIS SHOULD
CAUSE THE DATA TO BE WRITTEN INTO THE
CRAM BITS 0-11.
WRT 204/0 - NEGATE 'CRAM WRITE'
WRT 206/2 - ASSERT 'SINGLE CLK (1)'. THIS SHOULD
CLOCK THE RAM DATA INTO CRA LATCHES.
WRT 204/1 - ASSERT 'CRA/M RESET'. THIS SHOULD
CLEAR ALL LATCHED CRAM BITS.
WRT 210/115 - CLOCK THE RAM DATA INTO THE CSL TRANS-
CEIVERS.
RESPONSE:
THE RAM DATA READ BACK WAS NOT ZEROS. THIS MEANS THAT THE
'CRA/M RESET' SIGNAL DID NOT GET ASSERTED.
!
]54
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 103/125 - PUT DATA INTO CSL I/O BUFFER
WRT 210/144 - CLOCK DATA INTO CRA BOARD TRANSCEIVERS
WRT 205/0 - SET DIAG FN BITS = 0
WRT 204/40 - ASSERT 'CRAM WRITE'. THIS SHOULD
CAUSE THE DATA TO BE WRITTEN INTO THE
CRAM BITS 0-11.
WRT 204/0 - NEGATE 'CRAM WRITE'
WRT 103/252 - PUT DATA INTO CSL I/O BUFFER
WRT 210/144 - CLOCK DATA INTO CRA BUS BUFFER
WRT 206/2 - ASSERT 'SINGLE CLK (1)'. THIS SHOULD
CLOCK THE RAM DATA INTO CRA LATCHES.
WRT 210/115 - CLOCK THE RAM DATA INTO THE CSL TRANS-
CEIVERS.
RESPONSE:
THE CRAM BITS 4-11 GOT CHANGED FROM '125' TO '252' WITHOUT
ASSERTING 'CRAM WRITE'. THIS MEANS THAT 'CRAM WRITE' MUST BE
STUCK ASSERTED.
!
]55
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
ASSERT AND NEGATE 'CRA/M RESET'
WRT 103/377 - PUT DATA INTO CSL I/O BUFFER
WRT 210/144 - CLOCK DATA INTO CRA BOARD TRANSCEIVERS
WRT 204/20 - ASSERT 'CRAM ADR LOAD'. THIS SHOULD
CAUSE THE DATA TO BE WRITTEN INTO THE
'DIAG ADDR' BITS.
WRT 204/0 - NEGATE 'CRAM ADR LOAD'
WRT 205/1 - SET DIAG FN BITS = 1. THIS SELECT THE
NEXT CRAM ADDRESS TO BE READ.
WRT 210/115 - CLOCK THE ADDRESS INTO THE CSL TRANS-
CEIVERS.
RESPONSE:
THE NEXT CRAM ADDRESS BITS 4-11 WERE NOT READ BACK AS ALL ONES.
THIS MEANS THAT THE 'CRAM ADR LOAD' SIGNAL IS FAULTY.
!
]56
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
ASSERT AND NEGATE 'CRA/M RESET'
WRT 103/777 - PUT ONES INTO CSL I/O BUFFER
WRT 210/144 - CLOCK ONES INTO CRA BOARD TRANSCEIVERS
WRT 204/20 - ASSERT 'CRAM ADR LOAD'. THIS SHOULD
CAUSE ONES TO BE WRITTEN INTO THE
'DIAG ADDR' BITS.
WRT 103/0 - PUT ZEROES INTO CSL I/O BUFFER
WRT 210/144 - CLOCK ZEROES TO CRA BOARD TRANSCEIVERS
ASSERT AND NEGATE 'RESET'
WRT 204/20 - ASSERT 'CRAM ADR LOAD'. THIS SHOULD
CAUSE ZEROES TO BE WRITTEN INTO THE
'DIAG ADDR' BITS.
WRT 204/0 - NEGATE 'CRAM ADR LOAD'
WRT 205/1 - SET DIAG FN BITS = 1. THIS SELECT THE
NEXT CRAM ADDRESS TO BE READ.
WRT 210/115 - CLOCK THE ADDRESS INTO THE CSL TRANS-
CEIVERS.
RESPONSE:
THE NEXT CRAM ADDRESS BITS 4-11 WERE NOT READ BACK AS ZEROES.
THIS MEANS THAT THE 'CRAM ADR LOAD' SIGNAL DID NOT GET CLEARED
BY THE 'RESET L' SIGNAL.
!
]57
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
SET CRAM BIT 'CRM2 # 15B' AND SET 'SPEC' FIELD TO '10'
WRT 206/2 - ASSERTING 'SINGLE CLK' CLOCKS THE CRAM BITS
INTO THEIR LATCHES.
WRT 206/2 - ASSERTING 'SINGLE CLK' ASSERTS 'CRAM CLK'.
'CRAM CLK' AND 'SPEC' ASSERT 'CPM CMD LD'.
'CPM CMD LD' AND 'CRM2 # 15B' SHOULD ASSERT
'HALT LOOP'.
RESPONSE:
'HALT LOOP' DID NOT ASSERT.
!
[2
!STIMULUS:
ASSERT AND NEGATE 'RESET'
SET CRAM BIT 'CRM2 # 15B' AND SET 'SPEC' FIELD TO '10'
WRT 206/2 - ASSERTING 'SINGLE CLK' CLOCKS THE CRAM BITS
INTO THEIR LATCHES.
WRT 206/2 - ASSERTING 'SINGLE CLK' ASSERTS 'CRAM CLK'.
'CRAM CLK' AND 'SPEC' ASSERT 'CPM CMD LD'.
'CPM CMD LD' AND 'CRM2 # 15B' SHOULD ASSERT
'HALT LOOP'.
RESET CRAM BITS
ASSERT AND NEGATE RESET - THIS SHOULD NEGATE 'HALT LOOP'
RESPONSE:
'HALT LOOP' DID NOT NEGATE WHEN 'RESET' WAS TOGGLED.
!
]58
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
SET CRAM BIT 'CRM2 # 15B' AND SET 'SPEC' FIELDS TO DEFAULT
WRT 206/2 - ASSERTING 'SINGLE CLK' CLOCKS THE CRAM BITS
INTO THEIR LATCHES.
WRT 206/2 - ASSERTING 'SINGLE CLK' ASSERTS 'CRAM CLK'.
WITH 'CRA2 SPEC/CONSOLE' NEGATED, 'CPM CMD LD'
SHOULD NOT ASSERT. SO, 'HALT LOOP (1)' SHOULD
NOT ASSERT.
RESPONSE:
'HALT LOOP' ASSERTED.
!
]59
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
NEGATE CRAM BIT 'CRM2 # 15B' AND SET 'SPEC' FIELDS TO '10'
WRT 206/2 - ASSERTING 'SINGLE CLK' CLOCKS THE CRAM BITS
INTO THEIR LATCHES.
WRT 206/2 - ASSERTING 'SINGLE CLK' ASSERTS 'CRAM CLK'.
WITH 'CRA2 SPEC/CONSOLE' ASSERTED,'CPM CMD LD'
ASSERT. BUT WITH 'CRM2 # 15B' NEGATED,
'HALT LOOP (1)' SHOULD NOT ASSERT.
RESPONSE:
'HALT LOOP' ASSERTED.
!
]60
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
SET CRAM BIT 'CRM2 # 15B' AND SET 'SPEC' FIELDS TO '10'
WRT 206/2 - ASSERTING 'SINGLE CLK' CLOCKS THE CRAM
BITS INTO THEIR LATCHES.
WRT 206/2 - ASSERTING 'SINGLE CLK' CAUSES 'HALT
LOOP (1)' TO ASSERT.
SET 'CRM2 # 16B' AND CLEAR 'CRM2 # 15B' AND SET 'SPEC' TO '10'
WRT 206/2 - ASSERTING 'SINGLE CLK' ASSERTS 'CRAM
CLK' AND CLOCK CRAM BITS INTO CONTROL
FLOPS ON CRA BOARD. WITH 'CRA2 SPEC/
CONSOLE' ASSERTED, 'CPM CMD LD' SHOULD
ASSERT. BUT WITH 'CRM2 # 15B' NEGATED
AND 'CRM2 # 16B' ASSERTED, 'HALT LOOP
(1)' SHOULD NEGATE.
RESPONSE:
'HALT LOOP' IS ASSERTED.
!
]61
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
SET CRAM BIT 'CRM2 # 15B' AND SET 'SPEC' FIELDS TO '10'
WRT 206/2 - ASSERTING 'SINGLE CLK' CLOCKS THE CRAM
BITS INTO THEIR LATCHES.
WRT 206/2 - ASSERTING 'SINGLE CLK' CAUSES 'HALT
LOOP (1)' TO ASSERT.
CLEAR 'CRM2 # 16B' AND 'CRM2 # 15B' AND SET 'SPEC' TO '10'
WRT 206/2 - ASSERTING 'SINGLE CLK' ASSERTS 'CRAM
CLK' AND CLOCK CRAM BITS INTO CONTROL
FLOPS ON CRA BOARD. WITH 'CRA2 SPEC/
CONSOLE' ASSERTED, 'CPM CMD LD' SHOULD
ASSERT. BUT WITH 'CRM2 # 16B' NEGATED,
'HALT LOOP (1)' SHOULD NOT NEGATE.
RESPONSE:
'HALT LOOP' NEGATED.
!
]62
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
SET CRAM BIT 'CRM2 # 15B' AND SET 'SPEC' FIELDS TO '10'
WRT 206/2 - ASSERTING 'SINGLE CLK' CLOCKS THE CRAM
BITS INTO THEIR LATCHES.
WRT 206/2 - ASSERTING 'SINGLE CLK' CAUSES 'HALT
LOOP (1)' TO ASSERT.
SET 'CRM2 # 16B' AND CLEAR 'CRM2 # 15B' AND SET 'SPEC' TO '70'
WRT 206/2 - ASSERTING 'SINGLE CLK' ASSERTS 'CRAM
CLK' AND CLOCK CRAM BITS INTO CONTROL
FLOPS ON CRA BOARD. WITH 'CRA2 SPEC/
CONSOLE' NEGATED, 'CPM CMD LD' SHOULD
NOT ASSERT. THEREFORE, 'HALT LOOP (1)'
SHOULD NOT NEGATE.
RESPONSE:
'HALT LOOP' NEGATED.
!
]63
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
ASSERT AND NEGATE 'CRA/M RESET'
WRT 212/7 - ASSERT 1ST STAGE FLOPS
WRT 206/2 - ASSERT 'SINGLE CLK'. THIS SHOULD
TOGGLE 'ENABLE (0)' WHICH IN TURN
SHOULD CLOCK THE 'RUN (1)' FLOP.
RESPONSE:
'RUN (1)' DID NOT ASSERT.
!
[2
!STIMULUS:
ASSERT AND NEGATE 'RESET'
ASSERT AND NEGATE 'CRA/M RESET'
WRT 212/7 - ASSERT 1ST STAGE FLOPS
WRT 206/2 - ASSERT 'SINGLE CLK'. THIS SHOULD
TOGGLE 'ENABLE (0)' WHICH IN TURN
SHOULD CLOCK THE 'EXECUTE B' FLOP.
RESPONSE:
'EXECUTE B' DID NOT ASSERT.
!
[3
!STIMULUS:
ASSERT AND NEGATE 'RESET'
ASSERT AND NEGATE 'CRA/M RESET'
WRT 212/7 - ASSERT 1ST STAGE FLOPS
WRT 206/2 - ASSERT 'SINGLE CLK'. THIS SHOULD
TOGGLE 'ENABLE (0)' WHICH IN TURN
SHOULD CLOCK THE 'CONTINUE' FLOP.
RESPONSE:
'CONTINUE' DID NOT ASSERT.
!
[4
!STIMULUS:
ASSERT AND NEGATE 'RESET'
ASSERT AND NEGATE 'CRA/M RESET'
WRT 212/7 - ASSERT 1ST STAGE FLOPS
WRT 206/2 - ASSERT 'SINGLE CLK'. THIS SHOULD
TOGGLE 'ENABLE (0)' WHICH IN TURN
SHOULD CLOCK THE 'RUN (1)' FLOP.
ASSERT AND NEGATE 'RESET'
RESPONSE:
'RUN (1)' DID NOT NEGATE.
!
[5
!STIMULUS:
ASSERT AND NEGATE 'RESET'
ASSERT AND NEGATE 'CRA/M RESET'
WRT 212/7 - ASSERT 1ST STAGE FLOPS
WRT 206/2 - ASSERT 'SINGLE CLK'. THIS SHOULD
TOGGLE 'ENABLE (0)' WHICH IN TURN
SHOULD CLOCK THE 'EXECUTE B' FLOP.
ASSERT AND NEGATE 'RESET'
RESPONSE:
'EXECUTE B' DID NOT NEGATE.
!
[6
!STIMULUS:
ASSERT AND NEGATE 'RESET'
ASSERT AND NEGATE 'CRA/M RESET'
WRT 212/7 - ASSERT 1ST STAGE FLOPS
WRT 206/2 - ASSERT 'SINGLE CLK'. THIS SHOULD
TOGGLE 'ENABLE (0)' WHICH IN TURN
SHOULD CLOCK THE 'CONTINUE' FLOP.
ASSERT AND NEGATE 'RESET'
RESPONSE:
'CONTINUE' DID NOT NEGATE.
!
]64
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
ASSERT AND NEGATE 'CRA/M RESET'
WRT 212/7 - ASSERT 1ST STAGE FLOPS
WRT 206/2 - ASSERT 'SINGLE CLK'. THIS SHOULD
TOGGLE 'ENABLE (0)' WHICH IN TURN
SHOULD CLOCK THE 'RUN (1)' FLOP.
WRT 212/0 - NEGATE 1ST STAGE FLOPS
WRT 206/2 - ASSERT 'SINGLE CLK'. THIS SHOULD
TOGGLE 'ENABLE (0)' WHICH IN TURN
SHOULD CLOCK THE 'RUN (1)' FLOP.
RESPONSE:
'RUN (1)' DID NOT NEGATE.
!
[2
!STIMULUS:
ASSERT AND NEGATE 'RESET'
ASSERT AND NEGATE 'CRA/M RESET'
WRT 212/7 - ASSERT 1ST STAGE FLOPS
WRT 206/2 - ASSERT 'SINGLE CLK'. THIS SHOULD
TOGGLE 'ENABLE (0)' WHICH IN TURN
SHOULD CLOCK THE 'EXECUTE B' FLOP.
WRT 212/0 - NEGATE 1ST STAGE FLOPS
WRT 206/2 - ASSERT 'SINGLE CLK'. THIS SHOULD
TOGGLE 'ENABLE (0)' WHICH IN TURN
SHOULD CLOCK THE 'EXECUTE B' FLOP.
RESPONSE:
'EXECUTE B' DID NOT NEGATE.
!
[3
!STIMULUS:
ASSERT AND NEGATE 'RESET'
ASSERT AND NEGATE 'CRA/M RESET'
WRT 212/7 - ASSERT 1ST STAGE FLOPS
WRT 206/2 - ASSERT 'SINGLE CLK'. THIS SHOULD
TOGGLE 'ENABLE (0)' WHICH IN TURN
SHOULD CLOCK THE 'CONTINUE' FLOP.
WRT 212/0 - NEGATE 1ST STAGE FLOPS
WRT 206/2 - ASSERT 'SINGLE CLK'. THIS SHOULD
TOGGLE 'ENABLE (0)' WHICH IN TURN
SHOULD CLOCK THE 'CONTINUE' FLOP.
RESPONSE:
'CONTINUE' DID NOT NEGATE.
!
]65
[1
!STIMULUS:
SET CRAM BIT 'CRM2 # 14B' AND SET 'SPEC' FIELD TO '10'
ASSERT AND NEGATE 'RESET'
ASSERT AND NEGATE 'CRA/M RESET'
WRT 212/7 - ASSERT 1ST STAGE FLOPS
WRT 206/2 - ASSERTING 'SINGLE CLK' CLOCKS THE CRAM
BITS INTO THEIR LATCHES.
WRT 206/2 - ASSERT 'SINGLE CLK'. THIS SHOULD
CAUSE 'CPM CMD LD' TO ASSERT, WHICH
TOGETHER WITH 'CRM2 # 14B' WILL CLEAR
THE 1ST STAGE FLOP. WHEN 'ENABLE (0)'
TOGGLES, THE 'RUN (1)' FLOP WON'T
ASSERT.
RESPONSE:
'RUN (1)' DID NOT NEGATE.
!
[2
!STIMULUS:
SET CRAM BIT 'CRM2 # 13B' AND SET 'SPEC' FIELD TO '10'
ASSERT AND NEGATE 'RESET'
ASSERT AND NEGATE 'CRA/M RESET'
WRT 212/7 - ASSERT 1ST STAGE FLOPS
WRT 206/2 - ASSERTING 'SINGLE CLK' CLOCKS THE CRAM
BITS INTO THEIR LATCHES.
WRT 206/2 - ASSERT 'SINGLE CLK'. THIS SHOULD
CAUSE 'CPM CMD LD' TO ASSERT, WHICH
TOGETHER WITH 'CRM2 # 13B' WILL CLEAR
THE 1ST STAGE FLOP. WHEN 'ENABLE (0)'
TOGGLES, THE 'EXECUTE B' FLOP WON'T
ASSERT.
RESPONSE:
'EXECUTE B' DID NOT NEGATE.
!
[3
!STIMULUS:
SET CRAM BIT 'CRM2 # 12B' AND SET 'SPEC' FIELD TO '10'
ASSERT AND NEGATE 'RESET'
ASSERT AND NEGATE 'CRA/M RESET'
WRT 212/7 - ASSERT 1ST STAGE FLOPS
WRT 206/2 - ASSERTING 'SINGLE CLK' CLOCKS THE CRAM
BITS INTO THEIR LATCHES.
WRT 206/2 - ASSERT 'SINGLE CLK'. THIS SHOULD
CAUSE 'CPM CMD LD' TO ASSERT, WHICH
TOGETHER WITH 'CRM2 # 12B' WILL CLEAR
THE 1ST STAGE FLOP. WHEN 'ENABLE (0)'
TOGGLES, THE 'CONTINUE' FLOP WON'T
ASSERT.
RESPONSE:
'CONTINUE' DID NOT NEGATE.
!
]66
[1
!STIMULUS:
CLEAR CRAM BIT 'CRM2 # 14B' AND SET 'SPEC' FIELD TO '10'
ASSERT AND NEGATE 'RESET'
ASSERT AND NEGATE 'CRA/M RESET'
WRT 212/7 - ASSERT 1ST STAGE FLOPS
WRT 206/2 - ASSERTING 'SINGLE CLK' CLOCKS THE CRAM
BITS INTO THEIR LATCHES.
WRT 206/2 - ASSERT 'SINGLE CLK'. THIS TOGGLES
'ENABLE (0)' WHICH SHOULD ASSERT
'RUN (1)'. SINCE 'CRM2 # 14B' IS
NEGATED, THE 1ST STAGE FLOP SHOULD NOT
GET NEGATED.
RESPONSE:
'RUN (1)' DID NOT ASSERT.
!
[2
!STIMULUS:
CLEAR CRAM BIT 'CRM2 # 13B' AND SET 'SPEC' FIELD TO '10'
ASSERT AND NEGATE 'RESET'
ASSERT AND NEGATE 'CRA/M RESET'
WRT 212/7 - ASSERT 1ST STAGE FLOPS
WRT 206/2 - ASSERTING 'SINGLE CLK' CLOCKS THE CRAM
BITS INTO THEIR LATCHES.
WRT 206/2 - ASSERT 'SINGLE CLK'. THIS TOGGLES
'ENABLE (0)' WHICH SHOULD ASSERT
'EXECUTE B'. SINCE 'CRM2 # 13B' IS
NEGATED, THE 1ST STAGE FLOP SHOULD NOT
GET NEGATED.
RESPONSE:
'EXECUTE B' DID NOT ASSERT.
!
[3
!STIMULUS:
CLEAR CRAM BIT 'CRM2 # 12B' AND SET 'SPEC' FIELD TO '10'
ASSERT AND NEGATE 'RESET'
ASSERT AND NEGATE 'CRA/M RESET'
WRT 212/7 - ASSERT 1ST STAGE FLOPS
WRT 206/2 - ASSERTING 'SINGLE CLK' CLOCKS THE CRAM
BITS INTO THEIR LATCHES.
WRT 206/2 - ASSERT 'SINGLE CLK'. THIS TOGGLES
'ENABLE (0)' WHICH SHOULD ASSERT
'CONTINUE'. SINCE 'CRM2 # 12B' IS
NEGATED, THE 1ST STAGE FLOP SHOULD NOT
GET NEGATED.
RESPONSE:
'CONTINUE' DID NOT ASSERT.
!
]67
[1
!STIMULUS:
SET CRAM BIT 'CRM2 # 14B' AND SET 'SPEC' FIELD TO '70'
ASSERT AND NEGATE 'RESET'
ASSERT AND NEGATE 'CRA/M RESET'
WRT 212/7 - ASSERT 1ST STAGE FLOPS
WRT 206/2 - ASSERTING 'SINGLE CLK' CLOCKS THE CRAM
BITS INTO THEIR LATCHES.
WRT 206/2 - ASSERT 'SINGLE CLK'. THIS TOGGLES
'ENABLE (0)' WHICH SHOULD ASSERT
'RUN (1)'. SINCE 'CRA2 SPEC/CONSOLE'
IS NEGATED, THE 1ST STAGE FLOP SHOULD
NOT GET NEGATED.
RESPONSE:
'RUN (1)' DID NOT ASSERT.
!
[2
!STIMULUS:
SET CRAM BIT 'CRM2 # 13B' AND SET 'SPEC' FIELD TO '70'
ASSERT AND NEGATE 'RESET'
ASSERT AND NEGATE 'CRA/M RESET'
WRT 212/7 - ASSERT 1ST STAGE FLOPS
WRT 206/2 - ASSERTING 'SINGLE CLK' CLOCKS THE CRAM
BITS INTO THEIR LATCHES.
WRT 206/2 - ASSERT 'SINGLE CLK'. THIS TOGGLES
'ENABLE (0)' WHICH SHOULD ASSERT
'EXECUTE B'. SINCE 'CRA2 SPEC/CONSOLE'
IS NEGATED, THE 1ST STAGE FLOP SHOULD
NOT GET NEGATED.
RESPONSE:
'EXECUTE B' DID NOT ASSERT.
!
[3
!STIMULUS:
SET CRAM BIT 'CRM2 # 12B' AND SET 'SPEC' FIELD TO '70'
ASSERT AND NEGATE 'RESET'
ASSERT AND NEGATE 'CRA/M RESET'
WRT 212/7 - ASSERT 1ST STAGE FLOPS
WRT 206/2 - ASSERTING 'SINGLE CLK' CLOCKS THE CRAM
BITS INTO THEIR LATCHES.
WRT 206/2 - ASSERT 'SINGLE CLK'. THIS TOGGLES
'ENABLE (0)' WHICH SHOULD ASSERT
'CONTINUE'. SINCE 'CRA2 SPEC/CONSOLE'
IS NEGATED, THE 1ST STAGE FLOP SHOULD
NOT GET NEGATED.
RESPONSE:
'CONTINUE' DID NOT ASSERT.
!
]68
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 103/21 - WRITE DATA PATTERN TO BUFFERS
WRT 105/21 THIS PATTERN SHOULD CAUSE
WRT 107/20 R DATA 00-35 TO BE 042104010421
WRT 111/21
WRT 113/1
WRT 210/141 - CLOCK DATA INTO RECEIVER LATCHES.
THE SIGNALS TPR1-4 SHOULD ALL BE
ASSERTED AND SIGNALS TD18 AND TD19
SHOULD BE NEGATED. THIS SHOULD CAUSE
'R PAR RIGHT' TO BE NEGATED.
RESPONSE:
'R PAR RIGHT' IS ASSERTED.
!
[2
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 103/21 - WRITE DATA PATTERN TO BUFFERS
WRT 105/21 THIS PATTERN SHOULD CAUSE
WRT 107/20 R DATA 00-35 TO BE 042104010421
WRT 111/21
WRT 113/1
WRT 210/141 - CLOCK DATA INTO RECEIVER LATCHES.
THE SIGNALS TPL1-4 SHOULD ALL BE
ASSERTED AND SIGNALS TD16 AND TD17
SHOULD BE NEGATED. THIS SHOULD CAUSE
'R PAR LEFT' TO BE NEGATED.
RESPONSE:
'R PAR LEFT' IS ASSERTED.
!
[3
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 103/1 - WRITE DATA PATTERN TO BUFFERS
WRT 105/21 THIS PATTERN SHOULD CAUSE
WRT 107/25 R DATA 00-35 TO BE 042005210401
WRT 111/20
WRT 113/1
WRT 210/141 - CLOCK DATA INTO RECEIVER LATCHES.
THE SIGNALS TPR1,TPR3,TPR4 AND TD19
SHOULD BE ASSERTED. TPR2 AND TD18
SHOULD BE NEGATED. THIS SHOULD CAUSE
'R PAR RIGHT' TO BE NEGATED.
RESPONSE:
'R PAR RIGHT' IS ASSERTED.
!
[4
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 103/1 - WRITE DATA PATTERN TO BUFFERS
WRT 105/21 THIS PATTERN SHOULD CAUSE
WRT 107/25 R DATA 00-35 TO BE 042005210401
WRT 111/20
WRT 113/1
WRT 210/141 - CLOCK DATA INTO RECEIVER LATCHES.
THE SIGNALS TPL1,TPL3,TPL4 AND TD17
SHOULD BE ASSERTED. TPL2 AND TD16
SHOULD BE NEGATED. THIS SHOULD CAUSE
'R PAR LEFT' TO BE NEGATED.
RESPONSE:
'R PAR LEFT' IS ASSERTED.
!
[5
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 103/1 - WRITE DATA PATTERN TO BUFFERS
WRT 105/20 THIS PATTERN SHOULD CAUSE
WRT 107/37 R DATA 00-35 TO BE 040007610001
WRT 111/0
WRT 113/1
WRT 210/141 - CLOCK DATA INTO RECEIVER LATCHES.
THE SIGNALS TPR1,TPR4,TD18 AND TD19
SHOULD BE ASSERTED. TPR2 AND TPR3
SHOULD BE NEGATED. THIS SHOULD CAUSE
'R PAR RIGHT' TO BE NEGATED.
RESPONSE:
'R PAR RIGHT' IS ASSERTED.
!
[6
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 103/1 - WRITE DATA PATTERN TO BUFFERS
WRT 105/20 THIS PATTERN SHOULD CAUSE
WRT 107/37 R DATA 00-35 TO BE 040007610001
WRT 111/0
WRT 113/1
WRT 210/141 - CLOCK DATA INTO RECEIVER LATCHES.
THE SIGNALS TPL1,TPL4,TD16 AND TD17
SHOULD BE ASSERTED. TPL2 AND TPL3
SHOULD BE NEGATED. THIS SHOULD CAUSE
'R PAR RIGHT' TO BE NEGATED.
RESPONSE:
'R PAR LEFT' IS ASSERTED.
!
[7
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 103/21 - WRITE DATA PATTERN TO BUFFERS
WRT 105/20 THIS PATTERN SHOULD CAUSE
WRT 107/32 R DATA 00-35 TO BE 040106410021
WRT 111/0
WRT 113/1
WRT 210/141 - CLOCK DATA INTO RECEIVER LATCHES.
THE SIGNALS TPR1,TPR2,TPR4 AND TD18
SHOULD BE ASSERTED. TPR3 AND TD19
SHOULD BE NEGATED. THIS SHOULD CAUSE
'R PAR RIGHT' TO BE NEGATED.
RESPONSE:
'R PAR RIGHT' IS ASSERTED.
!
[8
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 103/21 - WRITE DATA PATTERN TO BUFFERS
WRT 105/20 THIS PATTERN SHOULD CAUSE
WRT 107/32 R DATA 00-35 TO BE 040106410021
WRT 111/0
WRT 113/1
WRT 210/141 - CLOCK DATA INTO RECEIVER LATCHES.
THE SIGNALS TPL1,TPL2,TPL4 AND TD16
SHOULD BE ASSERTED. TPL3 AND TD17
SHOULD BE NEGATED. THIS SHOULD CAUSE
'R PAR LEFT' TO BE NEGATED.
RESPONSE:
'R PAR LEFT' IS ASSERTED.
!
[9
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 103/20 - WRITE DATA PATTERN TO BUFFERS
WRT 105/0 THIS PATTERN SHOULD CAUSE
WRT 107/0 R DATA 00-35 TO BE 000100000020
WRT 111/1
WRT 113/0
WRT 210/141 - CLOCK DATA INTO RECEIVER LATCHES.
THE SIGNALS TPR1,TPR3,TPR4,TD18 AND
TD19 SHOULD BE NEGATED. TPR3
SHOULD BE ASSERTED. THIS SHOULD CAUSE
'R PAR RIGHT' TO BE ASSERTED.
RESPONSE:
'R PAR RIGHT' IS NEGATED.
!
[10
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 103/20 - WRITE DATA PATTERN TO BUFFERS
WRT 105/0 THIS PATTERN SHOULD CAUSE
WRT 107/0 R DATA 00-35 TO BE 000100000020
WRT 111/1
WRT 113/0
WRT 210/141 - CLOCK DATA INTO RECEIVER LATCHES.
THE SIGNALS TPL1,TPL3,TPL4,TD16 AND
TD17 SHOULD BE NEGATED. TPL3
SHOULD BE ASSERTED. THIS SHOULD CAUSE
'R PAR LEFT' TO BE ASSERTED.
RESPONSE:
'R PAR LEFT' IS NEGATED.
!
[11
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 103/20 - WRITE DATA PATTERN TO BUFFERS
WRT 105/1 THIS PATTERN SHOULD CAUSE
WRT 107/5 R DATA 00-35 TO BE 002101200420
WRT 111/21
WRT 113/0
WRT 210/141 - CLOCK DATA INTO RECEIVER LATCHES.
THE SIGNALS TPR1,TPR4 AND TD18
SHOULD BE NEGATED. TPR2,TPR3 AND TD19
SHOULD BE ASSERTED. THIS SHOULD CAUSE
'R PAR RIGHT' TO BE ASSERTED.
RESPONSE:
'R PAR RIGHT' IS NEGATED.
!
[12
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 103/20 - WRITE DATA PATTERN TO BUFFERS
WRT 105/1 THIS PATTERN SHOULD CAUSE
WRT 107/5 R DATA 00-35 TO BE 002101200420
WRT 111/21
WRT 113/0
WRT 210/141 - CLOCK DATA INTO RECEIVER LATCHES.
THE SIGNALS TPL1,TPL4 AND TD16
SHOULD BE NEGATED. TPL2,TPL3 AND TD17
SHOULD BE ASSERTED. THIS SHOULD CAUSE
'R PAR LEFT' TO BE ASSERTED.
RESPONSE:
'R PAR LEFT' IS NEGATED.
!
[13
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 103/0 - WRITE DATA PATTERN TO BUFFERS
WRT 105/1 THIS PATTERN SHOULD CAUSE
WRT 107/17 R DATA 00-35 TO BE 002003600400
WRT 111/20
WRT 113/0
WRT 210/141 - CLOCK DATA INTO RECEIVER LATCHES.
THE SIGNALS TPR1,TPR2 AND TPR4
SHOULD BE NEGATED. TPR3,TD18 AND TD19
SHOULD BE ASSERTED. THIS SHOULD CAUSE
'R PAR RIGHT' TO BE ASSERTED.
RESPONSE:
'R PAR RIGHT' IS NEGATED.
!
[14
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 103/0 - WRITE DATA PATTERN TO BUFFERS
WRT 105/1 THIS PATTERN SHOULD CAUSE
WRT 107/17 R DATA 00-35 TO BE 002003600400
WRT 111/20
WRT 113/0
WRT 210/141 - CLOCK DATA INTO RECEIVER LATCHES.
THE SIGNALS TPL1,TPL2 AND TPL4
SHOULD BE NEGATED. TPL3,TD16 AND TD17
SHOULD BE ASSERTED. THIS SHOULD CAUSE
'R PAR LEFT' TO BE ASSERTED.
RESPONSE:
'R PAR LEFT' IS NEGATED.
!
[15
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 103/0 - WRITE DATA PATTERN TO BUFFERS
WRT 105/0 THIS PATTERN SHOULD CAUSE
WRT 107/12 R DATA 00-35 TO BE 000002400000
WRT 111/0
WRT 113/0
WRT 210/141 - CLOCK DATA INTO RECEIVER LATCHES.
THE SIGNALS TPR1,TPR2,TPR3,TPR4 AND
TD19 SHOULD BE NEGATED. TD18
SHOULD BE ASSERTED. THIS SHOULD CAUSE
'R PAR RIGHT' TO BE ASSERTED.
RESPONSE:
'R PAR RIGHT' IS NEGATED.
!
[16
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 103/0 - WRITE DATA PATTERN TO BUFFERS
WRT 105/0 THIS PATTERN SHOULD CAUSE
WRT 107/12 R DATA 00-35 TO BE 000002400000
WRT 111/0
WRT 113/0
WRT 210/141 - CLOCK DATA INTO RECEIVER LATCHES.
THE SIGNALS TPL1,TPL2,TPL3,TPL4 AND
TD17 SHOULD BE NEGATED. TD16
SHOULD BE ASSERTED. THIS SHOULD CAUSE
'R PAR LEFT' TO BE ASSERTED.
RESPONSE:
'R PAR LEFT' IS NEGATED.
!
]69
[1
!STIMULUS:
LOAD UCODE WITH T00 = T01 = 0.
ASSERT AND NEGATE 'RESET'
STOP CLOCK AND SYNC TO A T CLK/R CLK NEGATED STATE
ASSERT AND NEGATE 'CRA/M RESET' - THIS NEGATES 'T00' AND 'T01'
WRT 206/2 - ASSERT 'SINGLE CLK'.
GENERATE 3 T-CLK/R-CLK CYCLES - THIS ASSERTS AND NEGATES
'ENABLE (1)' WHICH RESETS ALL THE
CPU CLOCK CONTROL FLOPS.
WRT 206/1 - ASSERT 'CLK RUN'
GENERATE 2 T-CLK/R-CLK CYCLES - THIS SHOULD CAUSE 'ENABLE (1)'
TO ASSERT WHICH IN TURN CAUSES 'CRA/M
CLK ENABLE' TO ASSERT.
RESPONSE:
'CRA/M CLK ENABLE' DIDN'T ASSERT.
!
[2
!STIMULUS:
LOAD UCODE WITH T00 = T01 = 0.
ASSERT AND NEGATE 'RESET'
STOP CLOCK AND SYNC TO A T-CLK/R-CLK NEGATED STATE
ASSERT AND NEGATE 'CRA/M RESET' - THIS NEGATES 'T00' AND 'T01'
WRT 206/2 - ASSERT 'SINGLE CLK'.
GENERATE 3 T-CLK/R-CLK CYCLES - THIS ASSERTS AND NEGATES
'ENABLE (1)' WHICH RESETS ALL THE
CPU CLOCK CONTROL FLOPS.
WRT 206/1 - ASSERT 'CLK RUN'
GENERATE 2 T-CLK/R-CLK CYCLES - THIS SHOULD CAUSE 'ENABLE (1)'
TO ASSERT WHICH IN TURN CAUSES 'DPE/M
CLK ENABLE' TO ASSERT.
RESPONSE:
'DPE/M CLK ENABLE' DIDN'T ASSERT.
!
[3
!STIMULUS:
LOAD UCODE WITH T00 = T01 = 0.
ASSERT AND NEGATE 'RESET'
STOP CLOCK AND SYNC TO A T-CLK/R-CLK NEGATED STATE
ASSERT AND NEGATE 'CRA/M RESET' - THIS NEGATES 'T00' AND 'T01'
WRT 206/2 - ASSERT 'SINGLE CLK'.
GENERATE 3 T-CLK/R-CLK CYCLES - THIS ASSERTS AND NEGATES
'ENABLE (1)' WHICH RESETS ALL THE
CPU CLOCK CONTROL FLOPS.
WRT 206/1 - ASSERT 'CLK RUN'
GENERATE 3 T-CLK/R-CLK CYCLES - THIS SHOULD CAUSE 'ENABLE (1)'
TO ASSERT THEN NEGATE WHICH SHOULD
CAUSE 'CRA/M CLK ENABLE' TO ASSERT THEN
NEGATE.
RESPONSE:
'CRA/M CLK ENABLE' DIDN'T NEGATE.
!
[4
!STIMULUS:
LOAD UCODE WITH T00 = T01 = 0.
ASSERT AND NEGATE 'RESET'
STOP CLOCK AND SYNC TO A T-CLK/R-CLK NEGATED STATE
ASSERT AND NEGATE 'CRA/M RESET' - THIS NEGATES 'T00' AND 'T01'
WRT 206/2 - ASSERT 'SINGLE CLK'.
GENERATE 3 T-CLK/R-CLK CYCLES - THIS ASSERTS AND NEGATES
'ENABLE (1)' WHICH RESETS ALL THE
CPU CLOCK CONTROL FLOPS.
WRT 206/1 - ASSERT 'CLK RUN'
GENERATE 4 T-CLK/R-CLK CYCLES - THIS SHOULD CAUSE 'ENABLE (1)'
TO ASSERT, NEGATE THEN ASSERT AGAIN.
THIS CAUSES 'CRA/M CLK ENABLE' TO
ASSERT, NEGATE THEN ASSERT AGAIN.
RESPONSE:
'CRA/M CLK ENABLE' DIDN'T ASSERT.
!
]70
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 205/100 - STOP CLOCKS
ASSERT AND NEGATE 'CRA/M RESET' - THIS NEGATES 'T00' AND 'T01'
WRT 206/1 - ASSERT 'CLK RUN' PRE-FLOP
ASSERT AND NEGATE 'RESET'
WRT 205/100 - STOP CLOCKS
GENERATE 2 T-CLK/R-CLK CYCLES - SINCE THE 'CLK RUN' PRE-FLOP
SHOULD BE NEGATED, 'ENABLE (1)' AND
'CRA/M CLK ENABLE' SHOULDN'T ASSERT.
RESPONSE:
'CRA/M CLK ENABLE' ASSERTED.
!
]71
[1
!STIMULUS:
ASSERT AND NEGATE 'RESET'
WRT 205/100 - STOP CLOCKS
ASSERT AND NEGATE 'CRA/M RESET' - THIS NEGATES 'T00' AND 'T01'
WRT 206/1 - ASSERT 'CLK RUN'
GENERATE 1 T-CLK/R-CLK CYCLE - THIS SHOULD ASSERT 'CLK RUN'
ASSERT AND NEGATE 'RESET'
WRT 205/100 - STOP CLOCKS
GENERATE 1 T-CLK/R-CLK CYCLE - SINCE 'CLK RUN' SHOULD BE
NEGATED 'ENABLE (1)' AND 'CRA/M CLK
ENABLE' SHOULD NOT ASSERT.
RESPONSE:
'CRA/M CLK ENABLE' ASSERTED.
!
]72
[1
!STIMULUS:
LOAD CRAM AND CLOCK BITS INTO CONTROL LATCHES - THIS ASSERTS
'T01' AND NEGATES 'T00'.
ASSERT AND NEGATE 'RESET'
STOP CLOCK AND SYNC TO A T CLK/R CLK NEGATED STATE
WRT 206/2 - ASSERT 'SINGLE CLK'.
GENERATE 3 T-CLK/R-CLK CYCLES - THIS ASSERTS AND NEGATES
'ENABLE (1)' WHICH RESETS ALL THE
CPU CLOCK CONTROL FLOPS.
WRT 206/1 - ASSERT 'CLK RUN'
GENERATE 2 T-CLK/R-CLK CYCLES - THIS SHOULD CAUSE 'CLK RUN' TO
ASSERT ON THE FIRST CYCLE, THEN
'ENABLE (1)' AND 'CRA/M CLK ENABLE'
SHOULD ASSERT ON THE SECOND CYCLE.
RESPONSE:
'CRA/M CLK ENABLE' DIDN'T ASSERT.
!
[2
!STIMULUS:
LOAD CRAM AND CLOCK BITS INTO CONTROL LATCHES - THIS ASSERTS
'T01' AND NEGATES 'T00'.
ASSERT AND NEGATE 'RESET'
STOP CLOCK AND SYNC TO A T CLK/R CLK NEGATED STATE
WRT 206/2 - ASSERT 'SINGLE CLK'.
GENERATE 3 T-CLK/R-CLK CYCLES - THIS ASSERTS AND NEGATES
'ENABLE (1)' WHICH RESETS ALL THE
CPU CLOCK CONTROL FLOPS.
WRT 206/1 - ASSERT 'CLK RUN'
GENERATE 3 T-CLK/R-CLK CYCLES - THE FIRST CYCLE ASSERTS 'CLK
RUN'. THE 2ND CYCLE ASSERTS 'ENABLE (1)'
WHICH ASSERTS 'CRA/M CLK ENABLE'. THE
3RD CYCLE SHOULD NEGATE 'T COUNT DONE
(1)' AND 'CRA/M CLK ENABLE'.
RESPONSE:
'CRA/M CLK ENABLE' DIDN'T NEGATE.
!
[3
!STIMULUS:
LOAD CRAM AND CLOCK BITS INTO CONTROL LATCHES - THIS ASSERTS
'T01' AND NEGATES 'T00'.
ASSERT AND NEGATE 'RESET'
STOP CLOCK AND SYNC TO A T CLK/R CLK NEGATED STATE
WRT 206/2 - ASSERT 'SINGLE CLK'.
GENERATE 3 T-CLK/R-CLK CYCLES - THIS ASSERTS AND NEGATES
'ENABLE (1)' WHICH RESETS ALL THE
CPU CLOCK CONTROL FLOPS.
WRT 206/1 - ASSERT 'CLK RUN'
GENERATE 4 T-CLK/R-CLK CYCLES - THE FIRST CYCLE ASSERTS 'CLK
RUN'. THE 2ND CYCLE ASSERTS 'ENABLE (1)'
WHICH IN TURN ASSERTS 'CRA/M CLK ENABLE'
THE 3RD CYCLE NEGATES 'T COUNT DONE (1)'
AND 'CRA/M CLK ENABLE'. 'T COUNT DONE
(1)' SHOULD STAY NEGATED ON THE 4TH
CYCLE. THEREFORE, 'ENABLE (1)' AND
'CRA/M CLK ENABLE' SHOULD STAY NEGATED.
RESPONSE:
'CRA/M CLK ENABLE' ASSERTED.
!
[4
!STIMULUS:
LOAD CRAM AND CLOCK BITS INTO CONTROL LATCHES - THIS ASSERTS
'T01' AND NEGATES 'T00'.
ASSERT AND NEGATE 'RESET'
STOP CLOCK AND SYNC TO A T CLK/R CLK NEGATED STATE
WRT 206/2 - ASSERT 'SINGLE CLK'.
GENERATE 3 T-CLK/R-CLK CYCLES - THIS ASSERTS AND NEGATES
'ENABLE (1)' WHICH RESETS ALL THE
CPU CLOCK CONTROL FLOPS.
WRT 206/1 - ASSERT 'CLK RUN'
GENERATE 5 T-CLK/R-CLK CYCLES - THE FIRST CYCLE ASSERTS 'CLK
RUN'. THE 2ND CYCLE ASSERTS 'ENABLE (1)'
WHICH IN TURN ASSERTS 'CRA/M CLK ENABLE'
THE 3RD CYCLE NEGATES 'T COUNT DONE (1)'
AND 'CRA/M CLK ENABLE'. 'T COUNT DONE
(1)' SHOULD STAY NEGATED ON THE 4TH
CYCLE. THEREFORE, 'ENABLE (1)' AND
'CRA/M CLK ENABLE' SHOULD STAY NEGATED.
THE 5TH CYCLE ASSERTS 'T COUNT DONE (1)'
WHICH SHOULD CAUSE 'ENABLE (1)' AND
'CRA/M CLK ENABLE' TO ASSERT.
RESPONSE:
'CRA/M CLK ENABLE' DIDN'T ASSERT.
!
]73
[1
!STIMULUS:
LOAD CRAM AND CLOCK BITS INTO CONTROL LATCHES - THIS ASSERTS
'T00' AND NEGATES 'T01'.
ASSERT AND NEGATE 'RESET'
STOP CLOCK AND SYNC TO A T CLK/R CLK NEGATED STATE
WRT 206/2 - ASSERT 'SINGLE CLK'.
GENERATE 3 T-CLK/R-CLK CYCLES - THIS ASSERTS AND NEGATES
'ENABLE (1)' WHICH RESETS ALL THE
CPU CLOCK CONTROL FLOPS.
WRT 206/1 - ASSERT 'CLK RUN'
GENERATE 2 T-CLK/R-CLK CYCLES - THE FIRST CYCLE CAUSES 'CLK
RUN' TO ASSERT. THE 2ND CYCLE DOES NOT
ASSERT 'ENABLE (1)' BECAUSE 'T COUNT
DONE (1)' SHOULD STILL BE NEGATED.
RESPONSE:
'CRA/M CLK ENABLE' ASSERTED PREMATURELY. THIS IMPLIES THAT
'T COUNT DONE (1)' MUST HAVE ASSERTED PREMATURELY.
!
[2
!STIMULUS:
LOAD CRAM AND CLOCK BITS INTO CONTROL LATCHES - THIS ASSERTS
'T00' AND NEGATES 'T01'.
ASSERT AND NEGATE 'RESET'
STOP CLOCK AND SYNC TO A T CLK/R CLK NEGATED STATE
WRT 206/2 - ASSERT 'SINGLE CLK'.
GENERATE 3 T-CLK/R-CLK CYCLES - THIS ASSERTS AND NEGATES
'ENABLE (1)' WHICH RESETS ALL THE
CPU CLOCK CONTROL FLOPS.
WRT 206/1 - ASSERT 'CLK RUN'
GENERATE 3 T-CLK/R-CLK CYCLES - THE FIRST CYCLE CAUSES 'CLK
RUN' TO ASSERT. THE 2ND CYCLE DOES NOT
ASSERT 'ENABLE (1)' BECAUSE 'T COUNT
DONE (1)' SHOULD STILL BE NEGATED. THE
3RD CYCLE SHOULD ASSERT 'T COUNT DONE
(1)', 'ENABLE (1)', AND 'CRA/M CLK
ENABLE'.
RESPONSE:
'CRA/M CLK ENABLE' DIDN'T ASSERT. THIS IMPLIES THAT 'T COUNT
DONE (1)' PROBABLY DIDN'T ASSERT.
!
]74
[1
!STIMULUS:
LOAD CRAM AND CLOCK BITS INTO CONTROL LATCHES - THIS ASSERTS
'T00' AND 'T01'.
ASSERT AND NEGATE 'RESET'
STOP CLOCK AND SYNC TO A T CLK/R CLK NEGATED STATE
WRT 206/2 - ASSERT 'SINGLE CLK'.
GENERATE 3 T-CLK/R-CLK CYCLES - THIS ASSERTS AND NEGATES
'ENABLE (1)' WHICH RESETS ALL THE
CPU CLOCK CONTROL FLOPS.
WRT 206/1 - ASSERT 'CLK RUN'
GENERATE 2 T-CLK/R-CLK CYCLES - THE FIRST CYCLE CAUSES 'CLK
RUN' TO ASSERT. THE 2ND CYCLE DOES NOT
ASSERT 'ENABLE (1)' BECAUSE 'T COUNT
DONE (1)' SHOULD STILL BE NEGATED.
RESPONSE:
'CRA/M CLK ENABLE' ASSERTED PREMATURELY. THIS IMPLIES THAT
'T COUNT DONE (1)' MUST HAVE ASSERTED PREMATURELY.
!
[2
!STIMULUS:
LOAD CRAM AND CLOCK BITS INTO CONTROL LATCHES - THIS ASSERTS
'T00' AND 'T01'.
ASSERT AND NEGATE 'RESET'
STOP CLOCK AND SYNC TO A T CLK/R CLK NEGATED STATE
WRT 206/2 - ASSERT 'SINGLE CLK'.
GENERATE 3 T-CLK/R-CLK CYCLES - THIS ASSERTS AND NEGATES
'ENABLE (1)' WHICH RESETS ALL THE
CPU CLOCK CONTROL FLOPS.
WRT 206/1 - ASSERT 'CLK RUN'
GENERATE 3 T-CLK/R-CLK CYCLES - THE FIRST CYCLE CAUSES 'CLK
RUN' TO ASSERT. THE 2ND AND 3RD CYCLES
DO NOT ASSERT 'ENABLE (1)' BECAUSE
'T COUNT DONE (1)' SHOULD STILL BE
NEGATED.
RESPONSE:
'CRA/M CLK ENABLE' ASSERTED PREMATURELY. THIS IMPLIES THAT
'T COUNT DONE (1)' MUST HAVE ASSERTED PREMATURELY.
!
[3
!STIMULUS:
LOAD CRAM AND CLOCK BITS INTO CONTROL LATCHES - THIS ASSERTS
'T00' AND 'T01'.
ASSERT AND NEGATE 'RESET'
STOP CLOCK AND SYNC TO A T CLK/R CLK NEGATED STATE
WRT 206/2 - ASSERT 'SINGLE CLK'.
GENERATE 3 T-CLK/R-CLK CYCLES - THIS ASSERTS AND NEGATES
'ENABLE (1)' WHICH RESETS ALL THE
CPU CLOCK CONTROL FLOPS.
WRT 206/1 - ASSERT 'CLK RUN'
GENERATE 4 T-CLK/R-CLK CYCLES - THE FIRST CYCLE CAUSES 'CLK
RUN' TO ASSERT. THE 2ND AND 3RD CYCLES
DO NOT ASSERT 'ENABLE (1)' BECAUSE
'T COUNT DONE (1)' SHOULD STILL BE
NEGATED. THE 4TH CYCLE SHOULD CAUSE
'T COUNT DONE (1)' TO ASSERT, WHICH
SHOULD CAUSE 'ENABLE (1)' AND 'CRA/M
CLK ENABLE' TO ASSERT.
RESPONSE:
'CRA/M CLK ENABLE' DIDN'T ASSERT. THIS IMPLIES THAT 'T COUNT
DONE (1)' PROBABLY DIDN'T ASSERT.
!
]75
[1
!STIMULUS:
RESET CRAM BITS
WRT 100/200 - ASSERT 'RESET'
WRT 100/100 - NEGATE 'RESET' AND ASSERT 'PE DETECT'
RESPONSE:
'PE (1)' ASSERTED. THIS IMPLIES THAT EITHER THERE IS AN
UNEXPECTED PARITY ERROR SOMEWHERE OR THERE IS A FAULT IN THE
PE DETECT LOGIC.
!
]76
[1
!STIMULUS:
WRT 100/200 - ASSERT 'RESET'
WRT 100/120 - NEGATE 'RESET' AND ASSERT 'DP PE DETECT' AND
'PE DETECT'.
RESPONSE:
'PE (1)' ASSERTED.
!
]77
[1
!STIMULUS:
WRT 204/1 - ASSERT 'CRA/M RESET'. THIS SHOULD NEGATE ALL
CRAM BITS, GIVING GOOD PARITY.
WRT 204/0 - CLEAR 'CRA/M RESET'
WRT 100/200 - ASSERT 'RESET'
WRT 100/140 - NEGATE 'RESET' AND ASSERT 'CRM DETECT' AND
'PE DETECT'.
RESPONSE:
'PE (1)' ASSERTED.
!
]78
[1
!STIMULUS:
MR - DO A MASTER RESET
LC0,DC0 - CLEAR ALL CRAM BITS
LF0,DF1 - ASSERT ONE BIT IN THE CRAM. THIS GIVES BAD
PARITY.
WRT 206/2 - ASSERT 'SINGLE_CLK'. THIS CLOCKS CRAM BITS
INTO LATCHES AND ASSERTS 'CRA6 CRAM PARITY
ERR'.
WRT 100/100 - ASSERT 'PE DETECT'. SINCE 'CRM DETECT' IS NOT
ASSERTED, 'PE (1)' SHOULD NOT ASSERT.
RESPONSE:
'PE (1)' ASSERTED.
!
]79
[1
!STIMULUS:
MR - DO A MASTER RESET
LC0,DC0 - CLEAR ALL CRAM BITS
LF0,DF1 - ASSERT ONE BIT IN THE CRAM. THIS GIVES BAD
PARITY.
WRT 206/2 - ASSERT 'SINGLE_CLK'. THIS CLOCKS CRAM BITS
INTO LATCHES AND ASSERTS 'CRA6 CRAM PARITY
ERR'. THIS SHOULD ASSERT 'CRA PE'.
RESPONSE:
'CRA PE' DID NOT ASSERT.
!
[2
!STIMULUS:
MR - DO A MASTER RESET
LC0,DC0 - CLEAR ALL CRAM BITS
LF0,DF1 - ASSERT ONE BIT IN THE CRAM. THIS GIVES BAD
PARITY.
WRT 206/2 - ASSERT 'SINGLE_CLK'. THIS CLOCKS CRAM BITS
INTO LATCHES AND ASSERTS 'CRA6 CRAM PARITY
ERR'.
WRT 100/140 - ASSERT 'PE DETECT' AND 'CRM DETECT'. THIS
SHOULD CAUSE 'PE (1)' TO ASSERT.
RESPONSE:
'PE (1)' DID NOT ASSERT.
!
[3
!STIMULUS:
MR - DO A MASTER RESET
LC0,DC0 - CLEAR ALL CRAM BITS
LF0,DF1 - ASSERT ONE BIT IN THE CRAM. THIS GIVES BAD
PARITY.
WRT 206/2 - ASSERT 'SINGLE_CLK'. THIS CLOCKS CRAM BITS
INTO LATCHES AND ASSERTS 'CRA6 CRAM PARITY
ERR'.
WRT 100/140 - ASSERT 'PE DETECT' AND 'CRM DETECT'. THIS
SHOULD CAUSE 'PE (1)' TO ASSERT.
WRT 100/100 - NEGATE 'CRM DETECT'. THE 'WRT 100 L' SIGNAL
SHOULD NEGATE 'PE (1)'.
RESPONSE:
'PE (1)' DID NOT NEGATE.
!
]80
[1
!STIMULUS:
MR - DO A MASTER RESET
LC0,DC0 - CLEAR ALL CRAM BITS
LF7,DF2 - ASSERT ONE BIT IN THE CRAM. THIS GIVES BAD
PARITY.
WRT 206/2 - ASSERT 'SINGLE_CLK'. THIS CLOCKS CRAM BITS
INTO LATCHES AND ASSERTS 'CRM3 PARITY
ERROR'. THIS SHOULD ASSERT 'CRAM PE'.
RESPONSE:
'CRAM PE' DID NOT ASSERT.
!
[2
!STIMULUS:
MR - DO A MASTER RESET
LC0,DC0 - CLEAR ALL CRAM BITS
LF7,DF2 - ASSERT ONE BIT IN THE CRAM. THIS GIVES BAD
PARITY.
WRT 206/2 - ASSERT 'SINGLE_CLK'. THIS CLOCKS CRAM BITS
INTO LATCHES AND ASSERTS 'CRM3 PARITY ERROR'.
WRT 100/140 - ASSERT 'PE DETECT' AND 'CRM DETECT'. THIS
SHOULD CAUSE 'PE (1)' TO ASSERT.
RESPONSE:
'PE (1)' DID NOT ASSERT.
!
[3
!STIMULUS:
MR - DO A MASTER RESET
LC0,DC0 - CLEAR ALL CRAM BITS
LF7,DF2 - ASSERT ONE BIT IN THE CRAM. THIS GIVES BAD
PARITY.
WRT 206/2 - ASSERT 'SINGLE_CLK'. THIS CLOCKS CRAM BITS
INTO LATCHES AND ASSERTS 'CRM3 PARITY ERROR'.
WRT 100/140 - ASSERT 'PE DETECT' AND 'CRM DETECT'. THIS
SHOULD CAUSE 'PE (1)' TO ASSERT.
WRT 204/1 - ASSERT 'CRA/M RESET'. THIS SHOULD CAUSE
'PE (1)' TO NEGATE.
WRT 204/0 - THEN NEGATE IT.
RESPONSE:
'PE (1)' DID NOT NEGATE.
!
]81
[1
!STIMULUS:
MR - DO A MASTER RESET
LC0,DC0 - CLEAR ALL CRAM BITS
LF7,DF2 - ASSERT ONE BIT IN THE CRAM. THIS GIVES BAD
PARITY.
WRT 206/2 - ASSERT 'SINGLE_CLK'. THIS CLOCKS CRAM BITS
INTO LATCHES AND ASSERTS 'CRM3 PARITY ERROR'.
WRT 100/40 - ASSERT 'CRM DETECT'. WITH 'PE DETECT' NEGATED,
'PE (1)' SHOULD NOT ASSERT.
RESPONSE:
'PE (1)' ASSERTED.
!
]82
[1
!STIMULUS:
MR - DO A MASTER RESET
LC0,DC0 - CLEAR ALL CRAM BITS
LF2,DF4000 - ASSERT ONE BIT IN THE CRAM. THIS GIVES BAD
PARITY.
WRT 206/2 - ASSERT 'SINGLE_CLK'. THIS CLOCKS CRAM BITS
INTO LATCHES AND ASSERTS 'CRA6 CRAM PARITY
ERR'.
WRT 100/140 - ASSERT 'PE DETECT' AND 'CRM DETECT'. THIS
SHOULD CAUSE 'PE (1)' TO ASSERT.
WRT 103/0 - WRITE 8080 I/O BUFFERS WITH ZEROS
WRT 105/0
WRT 205/2 - SET DIAG FN BITS = 2
WRT 210/144 - CLOCK ZEROS TO CRA BOARD.
WRT 204/40 - CLOCK DATA INTO CRAM
WRT 204/0
WRT 206/2 - ASSERT 'SINGLE CLK'. THIS CLOCK CRAM DATA INTO
LATCHES AND SHOULD CLEAR 'CRA6 CRAM PARITY
ERR'. 'PE (1)' SHOULD STAY ASSERTED.
RESPONSE:
'PE (1)' NEGATED.
!
[2
!STIMULUS:
MR - DO A MASTER RESET
LC0,DC0 - CLEAR ALL CRAM BITS
LF2,DF4000 - ASSERT ONE BIT IN THE CRAM. THIS GIVES BAD
PARITY.
WRT 206/2 - ASSERT 'SINGLE_CLK'. THIS CLOCKS CRAM BITS
INTO LATCHES AND ASSERTS 'CRA6 CRAM PARITY
ERR'.
WRT 100/140 - ASSERT 'PE DETECT' AND 'CRM DETECT'. THIS
SHOULD CAUSE 'PE (1)' TO ASSERT.
WRT 103/0 - WRITE 8080 I/O BUFFERS WITH ZEROS
WRT 105/0
WRT 205/2 - SET DIAG FN BITS = 2
WRT 210/144 - CLOCK ZEROS TO CRA BOARD.
WRT 204/40 - CLOCK DATA INTO CRAM
WRT 204/0
WRT 206/2 - ASSERT 'SINGLE CLK'. THIS CLOCK CRAM DATA INTO
LATCHES AND SHOULD CLEAR 'CRA6 CRAM PARITY
ERR'. 'CRA PE' SHOULD STAY ASSERTED.
RESPONSE:
'CRA PE' DIDN'T STAY ASSERTED.
!
]83
[1
!STIMULUS:
MR - DO A MASTER RESET
LC0,DC0 - CLEAR ALL CRAM BITS
LF0,DF1 - ASSERT ONE BIT IN THE CRAM. THIS GIVES BAD
PARITY.
WRT 206/2 - ASSERT 'SINGLE_CLK'. THIS CLOCKS CRAM BITS
INTO LATCHES AND ASSERTS 'CRA6 CRAM PARITY
ERR'.
WRT 100/140 - ASSERT 'PE DETECT' AND 'CRM DETECT'. THIS
SHOULD CAUSE 'PE (1)' TO ASSERT.
STOP CLOCK AND SYNC TO A T CLK/R CLK NEGATED STATE
WRT 206/2 - ASSERT 'SINGLE CLK'.
GENERATE 3 T-CLK/R-CLK CYCLES - THIS ASSERTS AND NEGATES
'ENABLE (1)' WHICH RESETS ALL THE
CPU CLOCK CONTROL FLOPS.
WRT 206/1 - ASSERT 'CLK RUN'
GENERATE 2 T-CLK/R-CLK CYCLES - THE FIRST CYCLE CAUSES 'CLK
RUN' TO ASSERT. THE 2ND CYCLE DOES NOT
ASSERT 'ENABLE (1)' BECAUSE 'PE (0) H'
IS NEGATED.
RESPONSE:
'CRA/M CLK ENABLE' ASSERTED. THIS MEANS THAT 'PE (1)' BEING
ASSERTED DID NOT INHIBIT ASSERTION OF 'ENABLE (1)'.
!
]84
[1
!STIMULUS:
WRT 114/2 - SETUP BUFFER SO 'R I/O DATA' WILL ASSERT
WRT 102/0 - SETUP BUFFERS WITH TEST DATA
WRT 104/0
WRT 106/0
WRT 110/0
WRT 112/0
WRT 100/200 - ASSERT 'RESET'
WRT 100/100 - NEGATE 'RESET' AND ASSERT 'PE DETECT'
WRT 210/123 - ASSERTING 'BUS REQ' AND 'XMIT DATA (1)' CLOCKS
THE BUFFER DATA ONTO THE KS10 BUS. 'LATCH
DATA' AND 'R I/O DATA' WILL ASSERT 'DATA ENB'.
SINCE THE DATA HAS GOOD PARITY, 'REC PE'
SHOULD BE NEGATED AND THEREFORE 'PE (1)' WILL
NOT ASSERT.
RESPONSE:
'PE (1)' ASSERTED.
!
[2
!STIMULUS:
WRT 114/2 - SETUP BUFFER SO 'R I/O DATA' WILL ASSERT
WRT 102/0 - SETUP BUFFERS WITH TEST DATA
WRT 104/0
WRT 106/0
WRT 110/1
WRT 112/0
WRT 100/200 - ASSERT 'RESET'
WRT 100/100 - NEGATE 'RESET' AND ASSERT 'PE DETECT'
WRT 210/123 - ASSERTING 'BUS REQ' AND 'XMIT DATA (1)' CLOCKS
THE BUFFER DATA ONTO THE KS10 BUS. 'LATCH
DATA' AND 'R I/O DATA' WILL ASSERT 'DATA ENB'.
SINCE THE DATA HAS GOOD PARITY, 'REC PE'
SHOULD BE NEGATED AND THEREFORE 'PE (1)' WILL
NOT ASSERT.
RESPONSE:
'PE (1)' ASSERTED.
!
[3
!STIMULUS:
WRT 114/2 - SETUP BUFFER SO 'R I/O DATA' WILL ASSERT
WRT 102/1 - SETUP BUFFERS WITH TEST DATA
WRT 104/1
WRT 106/24
WRT 110/21
WRT 112/0
WRT 100/200 - ASSERT 'RESET'
WRT 100/100 - NEGATE 'RESET' AND ASSERT 'PE DETECT'
WRT 210/123 - ASSERTING 'BUS REQ' AND 'XMIT DATA (1)' CLOCKS
THE BUFFER DATA ONTO THE KS10 BUS. 'LATCH
DATA' AND 'R I/O DATA' WILL ASSERT 'DATA ENB'.
SINCE THE DATA HAS GOOD PARITY, 'REC PE'
SHOULD BE NEGATED AND THEREFORE 'PE (1)' WILL
NOT ASSERT.
RESPONSE:
'PE (1)' ASSERTED.
!
[4
!STIMULUS:
WRT 114/2 - SETUP BUFFER SO 'R I/O DATA' WILL ASSERT
WRT 102/1 - SETUP BUFFERS WITH TEST DATA
WRT 104/1
WRT 106/24
WRT 110/20
WRT 112/0
WRT 100/200 - ASSERT 'RESET'
WRT 100/100 - NEGATE 'RESET' AND ASSERT 'PE DETECT'
WRT 210/123 - ASSERTING 'BUS REQ' AND 'XMIT DATA (1)' CLOCKS
THE BUFFER DATA ONTO THE KS10 BUS. 'LATCH
DATA' AND 'R I/O DATA' WILL ASSERT 'DATA ENB'.
SINCE THE DATA HAS GOOD PARITY, 'REC PE'
SHOULD BE NEGATED AND THEREFORE 'PE (1)' WILL
NOT ASSERT.
RESPONSE:
'PE (1)' ASSERTED.
!
[5
!STIMULUS:
WRT 114/2 - SETUP BUFFER SO 'R I/O DATA' WILL ASSERT
WRT 102/20 - SETUP BUFFERS WITH TEST DATA
WRT 104/21
WRT 106/25
WRT 110/0
WRT 112/1
WRT 100/200 - ASSERT 'RESET'
WRT 100/100 - NEGATE 'RESET' AND ASSERT 'PE DETECT'
WRT 210/123 - ASSERTING 'BUS REQ' AND 'XMIT DATA (1)' CLOCKS
THE BUFFER DATA ONTO THE KS10 BUS. 'LATCH
DATA' AND 'R I/O DATA' WILL ASSERT 'DATA ENB'.
SINCE THE DATA HAS GOOD PARITY, 'REC PE'
SHOULD BE NEGATED AND THEREFORE 'PE (1)' WILL
NOT ASSERT.
RESPONSE:
'PE (1)' ASSERTED.
!
[6
!STIMULUS:
WRT 114/2 - SETUP BUFFER SO 'R I/O DATA' WILL ASSERT
WRT 102/20 - SETUP BUFFERS WITH TEST DATA
WRT 104/21
WRT 106/25
WRT 110/1
WRT 112/1
WRT 100/200 - ASSERT 'RESET'
WRT 100/100 - NEGATE 'RESET' AND ASSERT 'PE DETECT'
WRT 210/123 - ASSERTING 'BUS REQ' AND 'XMIT DATA (1)' CLOCKS
THE BUFFER DATA ONTO THE KS10 BUS. 'LATCH
DATA' AND 'R I/O DATA' WILL ASSERT 'DATA ENB'.
SINCE THE DATA HAS GOOD PARITY, 'REC PE'
SHOULD BE NEGATED AND THEREFORE 'PE (1)' WILL
NOT ASSERT.
RESPONSE:
'PE (1)' ASSERTED.
!
[7
!STIMULUS:
WRT 114/2 - SETUP BUFFER SO 'R I/O DATA' WILL ASSERT
WRT 102/21 - SETUP BUFFERS WITH TEST DATA
WRT 104/20
WRT 106/1
WRT 110/21
WRT 112/1
WRT 100/200 - ASSERT 'RESET'
WRT 100/100 - NEGATE 'RESET' AND ASSERT 'PE DETECT'
WRT 210/123 - ASSERTING 'BUS REQ' AND 'XMIT DATA (1)' CLOCKS
THE BUFFER DATA ONTO THE KS10 BUS. 'LATCH
DATA' AND 'R I/O DATA' WILL ASSERT 'DATA ENB'.
SINCE THE DATA HAS GOOD PARITY, 'REC PE'
SHOULD BE NEGATED AND THEREFORE 'PE (1)' WILL
NOT ASSERT.
RESPONSE:
'PE (1)' ASSERTED.
!
[8
!STIMULUS:
WRT 114/2 - SETUP BUFFER SO 'R I/O DATA' WILL ASSERT
WRT 102/21 - SETUP BUFFERS WITH TEST DATA
WRT 104/20
WRT 106/1
WRT 110/20
WRT 112/1
WRT 100/200 - ASSERT 'RESET'
WRT 100/100 - NEGATE 'RESET' AND ASSERT 'PE DETECT'
WRT 210/123 - ASSERTING 'BUS REQ' AND 'XMIT DATA (1)' CLOCKS
THE BUFFER DATA ONTO THE KS10 BUS. 'LATCH
DATA' AND 'R I/O DATA' WILL ASSERT 'DATA ENB'.
SINCE THE DATA HAS GOOD PARITY, 'REC PE'
SHOULD BE NEGATED AND THEREFORE 'PE (1)' WILL
NOT ASSERT.
RESPONSE:
'PE (1)' ASSERTED.
!
]85
[1
!STIMULUS:
ASSERT AND NEGATE 'CRA/M RESET'
ASSERT AND NEGATE 'RESET'
RESPONSE:
'REC PE' IS ASSERTED.
!
[2
!STIMULUS:
ASSERT AND NEGATE 'CRA/M RESET'
ASSERT AND NEGATE 'RESET'
RESPONSE:
'DP PE' IS ASSERTED.
!
[3
!STIMULUS:
ASSERT AND NEGATE 'CRA/M RESET'
ASSERT AND NEGATE 'RESET'
RESPONSE:
'RAM ERROR' IS ASSERTED.
!
]86
[1
!STIMULUS:
WRT 100/200 - ASSERT 'RESET'
WRT 100/100 - NEGATE 'RESET' AND ASSERT 'PE DETECT'
LI 100000 - LOAD I/O ADDRESS 100000
DI 40000000000 - SET 'PAR ERR' BIT IN MEMORY STATUS REG
THIS SHOULD ASSERT 'MEM PARITY ERR'
RESPONSE:
'MEM PARITY ERR' DID NOT ASSERT.
!
[2
!STIMULUS:
WRT 100/200 - ASSERT 'RESET'
WRT 100/100 - NEGATE 'RESET' AND ASSERT 'PE DETECT'
ASSERT AND NEGATE 'RESET'
LI 100000 - LOAD I/O ADDRESS 100000
DI 40000000000 - SET 'PAR ERR' BIT IN MEMORY STATUS REG
WRT 100/100 - ASSERT 'PE DETECT'. SINCE 'MEM PARITY
ERR' IS ASSERTED, 'PE (1)' SHOULD
ASSERT.
RESPONSE:
'PE (1)' DID NOT ASSERT.
!
]87
[1
!STIMULUS:
WRT 205/0 - NEGATE '10 INT'
WRT 205/1 - ASSERT '10 INT'
RESPONSE:
'10 INT' DID NOT ASSERT.
!
[2
!STIMULUS:
WRT 205/0 - NEGATE '10 INT'
WRT 205/1 - ASSERT '10 INT'
WRT 205/0 - NEGATE '10 INT'
RESPONSE:
'10 INT' DID NOT NEGATE.
!
]88
[1
!STIMULUS:
LOAD MICROINSTRUCTION AT LOC 0
MR - DO A MASTER RESET
WRT 205/0 - MAKE SURE '10 INT' IS NEGATED.
CP 1 - EXECUTE THE MICRO-INSTRUCTION. THIS SHOULD
CAUSE 'DPMB CSL INTERRUPT' TO ASSERT, WHICH
IN TURN SHOULD CAUSE '10 INT' TO ASSERT.
RESPONSE:
'10 INT' DID NOT ASSERT.
!
[2
!STIMULUS:
LOAD MICROINSTRUCTION AT LOC 0
MR - DO A MASTER RESET
WRT 205/0 - MAKE SURE '10 INT' IS NEGATED.
CP 1 - EXECUTE THE MICRO-INSTRUCTION. THIS SHOULD
CAUSE 'DPMB CSL INTERRUPT' TO ASSERT, WHICH
IN TURN SHOULD CAUSE '10 INT' TO ASSERT.
WRT 204/4 - ASSERT 'DP RESET'. THIS SHOULD NEGATE 'DPMB
CSL INTERRUPT', THUS ALLOWING '10 INT' TO BE
NEGATED.
WRT 204/0 - NEGATE 'DP RESET'
WRT 205/0 - NEGATE '10 INT'.
RESPONSE:
'10 INT' DID NOT NEGATE. THIS IMPLIES THAT 'DP RESET' DID NOT
NEGATE 'DPMB CSL INTERRUPT'.
!
]89
[1
!STIMULUS:
LOAD 2 MICRO-INSTRUCTIONS AT LOC 0
ASSERT AND NEGATE 'RESET'
SET NEXT ADDRESS TO 0
STOP CLOCK AND SYNC IT SO T-CLK AND R-CLK ARE NEGATED.
WRT 206/2 - ASSERT 'SINGLE CLK'
GENERATE 4 T-CLK/R-CLK CYCLES - THIS EXECUTES MICRO-INSTR AT 0.
THIS LOADS 'FE SIGN' WITH A 1.
WRT 206/2 - ASSERT 'SINGLE CLK'
GENERATE 4 T-CLK/R-CLK CYCLES - THIS EXECUTES MICRO-INSTR AT 1.
THIS ASSERTS 'MULTI SHIFT'.'MULTI SHIFT' AND
'FE SIGN' SHOULD ASSERT 'FS (1)'. THIS WILL
HOLD 'ENABLE (1)' ASSERTED AND CAUSE 'CRA/M
CLK ENABLE' TO NEGATE WHILE 'DPE/M CLK ENABLE'
IS ASSERTED.
RESPONSE:
'CRA/M CLK ENABLE' DIDN'T NEGATE.
!
[2
!STIMULUS:
LOAD 2 MICRO-INSTRUCTIONS AT LOC 0
ASSERT AND NEGATE 'RESET'
SET NEXT ADDRESS TO 0
STOP CLOCK AND SYNC IT SO T-CLK AND R-CLK ARE NEGATED.
WRT 206/2 - ASSERT 'SINGLE CLK'
GENERATE 4 T-CLK/R-CLK CYCLES - THIS EXECUTES MICRO-INSTR AT 0.
THIS LOADS 'FE SIGN' WITH A 1.
WRT 206/2 - ASSERT 'SINGLE CLK'
GENERATE 4 T-CLK/R-CLK CYCLES - THIS EXECUTES MICRO-INSTR AT 1.
THIS ASSERTS 'MULTI SHIFT'.'MULTI SHIFT' AND
'FE SIGN' SHOULD ASSERT 'FS (1)'. THIS WILL
HOLD 'ENABLE (1)' ASSERTED AND CAUSE 'CRA/M
CLK ENABLE' TO NEGATE WHILE 'DPE/M CLK ENABLE'
IS ASSERTED.
RESPONSE:
'DPE/M CLK ENABLE' DIDN'T STAY ASSERTED.
!
]90
[1
!STIMULUS:
LOAD 2 MICRO-INSTRUCTIONS AT LOC 0
ASSERT AND NEGATE 'RESET'
SET NEXT ADDRESS TO 0
STOP CLOCK AND SYNC IT SO T-CLK AND R-CLK ARE NEGATED.
WRT 206/2 - ASSERT 'SINGLE CLK'
GENERATE 4 T-CLK/R-CLK CYCLES - THIS EXECUTES MICRO-INSTR AT 0.
THIS LOADS 'FE SIGN' WITH A 0.
WRT 206/2 - ASSERT 'SINGLE CLK'
GENERATE 2 T-CLK/R-CLK CYCLES - THIS EXECUTES MICRO-INSTR AT 1.
THIS ASSERTS 'MULTI SHIFT'. WITH 'FE SIGN'
NEGATED, 'CRA/M CLK ENABLE' SHOULD ASSERT AND
'DPE/M CLK ENABLE' SHOULD NEGATE.
RESPONSE:
'CRA/M CLK ENABLE' DIDN'T ASSERT.
!
[2
!STIMULUS:
LOAD 2 MICRO-INSTRUCTIONS AT LOC 0
ASSERT AND NEGATE 'RESET'
SET NEXT ADDRESS TO 0
STOP CLOCK AND SYNC IT SO T-CLK AND R-CLK ARE NEGATED.
WRT 206/2 - ASSERT 'SINGLE CLK'
GENERATE 4 T-CLK/R-CLK CYCLES - THIS EXECUTES MICRO-INSTR AT 0.
THIS LOADS 'FE SIGN' WITH A 0.
WRT 206/2 - ASSERT 'SINGLE CLK'
GENERATE 2 T-CLK/R-CLK CYCLES - THIS EXECUTES MICRO-INSTR AT 1.
THIS ASSERTS 'MULTI SHIFT'. WITH 'FE SIGN'
NEGATED, 'CRA/M CLK ENABLE' SHOULD ASSERT AND
'DPE/M CLK ENABLE' SHOULD NEGATE.
RESPONSE:
'DPE/M CLK ENABLE' DIDN'T NEGATE.
!
]91
[1
!STIMULUS:
LOAD 2 MICRO-INSTRUCTIONS AT LOC 0
ASSERT AND NEGATE 'RESET'
SET NEXT ADDRESS TO 0
STOP CLOCK AND SYNC IT SO T-CLK AND R-CLK ARE NEGATED.
WRT 206/2 - ASSERT 'SINGLE CLK'
GENERATE 4 T-CLK/R-CLK CYCLES - THIS EXECUTES MICRO-INSTR AT 0.
THIS LOADS 'FE SIGN' WITH A 1.
WRT 206/2 - ASSERT 'SINGLE CLK'
GENERATE 2 T-CLK/R-CLK CYCLES - THIS EXECUTES MICRO-INSTR AT 1.
WITH 'MULTI SHIFT' NEGATED, 'CRA/M CLK ENABLE'
AND 'DPE/M CLK ENABLE' SHOULD BOTH ASSERT.
RESPONSE:
'CRA/M CLK ENABLE' DIDN'T ASSERT.
!
[2
!STIMULUS:
LOAD 2 MICRO-INSTRUCTIONS AT LOC 0
ASSERT AND NEGATE 'RESET'
SET NEXT ADDRESS TO 0
STOP CLOCK AND SYNC IT SO T-CLK AND R-CLK ARE NEGATED.
GENERATE 4 T-CLK/R-CLK CYCLES - THIS EXECUTES MICRO-INSTR AT 0.
THIS LOADS 'FE SIGN' WITH A 1.
WRT 206/2 - ASSERT 'SINGLE CLK'
GENERATE 2 T-CLK/R-CLK CYCLES - THIS EXECUTES MICRO-INSTR AT 1.
THIS ASSERTS 'MULTI SHIFT'. WITH 'FE SIGN'
NEGATED, 'CRA/M CLK ENABLE' SHOULD ASSERT AND
'DPE/M CLK ENABLE' SHOULD NEGATE.
RESPONSE:
'DPE/M CLK ENABLE' DIDN'T ASSERT.
!
]92
[1
!STIMULUS:
EM 0 - EXAMINE MEMORY LOCATION 0. SHOULD NOT GET
A 'NEXM' ERROR.
RESPONSE:
'NEXM' ASSERTED.
!
]93
[1
!STIMULUS:
LOAD 4 MICRO-INSTRUCTIONS STARTING AT LOC 0
MR - DO A MASTER RESET
LC 0 - SET CRAM ADDRESS = 0
LF3 - SET DIAG FN TO MODIFY MAGIC # FIELD
DF 2\O0 - SET MAGIC # TO ENABLE APR FLAG 31 AND TO
SELECT PI REQ \O0.
WRT 116/1 - ASSERT 'INT 10' PRE-FLOP.
CP 2 - EXECUTE THE 2 MICRO-INSTRUCTIONS. THIS SHOULD
CAUSE 'INT 10' TO ASSERT WHICH WILL CAUSE
'DPMB APR FLAG 31' TO ASSERT. THIS IN TURN
ASSERTS 'DPMB APR INT REQ' WHICH CAUSES 'BUS
PI REQ \O0' TO ASSERT.
RESPONSE:
'BUS PI REQ \O0' DID NOT ASSERT.
!
[2
!STIMULUS:
LOAD 4 MICRO-INSTRUCTIONS STARTING AT LOC 0
MR - DO A MASTER RESET
LC 0 - SET CRAM ADDRESS = 0
LF3 - SET DIAG FN TO MODIFY MAGIC # FIELD
DF 2\O0 - SET MAGIC # TO ENABLE APR FLAG 31 AND TO
SELECT PI REQ \O0.
WRT 116/1 - ASSERT 'INT 10' PRE-FLOP.
CP 4 - EXECUTE THE 4 MICRO-INSTRUCTIONS. THIS SHOULD
CAUSE 'INT 10' TO ASSERT WHICH WILL CAUSE
'DPMB APR FLAG 31' TO ASSERT. THIS IN TURN
ASSERTS 'DPMB APR INT REQ' WHICH CAUSES 'BUS
PI REQ \O0' TO ASSERT. THE 4TH CLOCK PULSE
SHOULD NEGATE 'INT 10' WHICH WILL ALLOW THE
4TH MICRO-INSTR TO NEGATE 'DPMB APR FLAG 31'.
THIS WILL NEGATE 'PI REQ \O0'.
RESPONSE:
'PI REQ \O0' DID NOT NEGATE.
!
]94
[1
!STIMULUS:
LOAD 2 MICRO-INSTRUCTIONS STARTING AT LOC 0
MR - DO A MASTER RESET
LC 0 - SET CRAM ADDRESS = 0
WRT 116/1 - ASSERT 'INT 10' PRE-FLOP.
CP 1 - EXECUTE 1 MICRO-INSTRUCTION. THIS SHOULD
CAUSE THE 2ND-STAGE FLOP TO ASSERT AND SETUP
THE CPU SO THAT 'INT 10' WILL CAUSE A PI REQ.
WRT 100/200 - ASSERT 'RESET'. THIS SHOULD NEGATE 2ND-STAGE
FLOP.
WRT 100/0 - NEGATE 'RESET'
CP 1 - EXECUTE THE 2ND MICRO-INSTRUCTION. SINCE THE
2ND-STAGE FLOP IS NEGATED, 'INT 10' SHOULD NOT
ASSERT AND 'PI REQ 1' SHOULD NOT ASSERT.
RESPONSE:
'PI REQ 1' ASSERTED.
!
]95
[1
!STIMULUS:
LOAD 2 MICRO-INSTRUCTIONS STARTING AT LOC 0
MR - DO A MASTER RESET
LC 0 - SET CRAM ADDRESS = 0
WRT 116/1 - ASSERT 'INT 10' PRE-FLOP.
WRT 116/0 - NEGATE 'INT 10' PRE-FLOP
CP 2 - EXECUTE THE 2 MICRO-INSTRUCTIONS. SINCE FLOP
IS NEGATED, 'INT 10' SHOULD NOT ASSERT
AND 'PI REQ 1' SHOULD NOT ASSERT.
RESPONSE:
'PI REQ 1' ASSERTED.
!
]96
[1
!STIMULUS:
LOAD MICRO-INSTRS TO CAUSE A PAGE FAIL TRAP
X1 0 - SET CRAM ADDR = 0.
STOP CLOCK AND SYNC IT SO T-CLK AND R-CLK ARE NEGATED.
WRT 206/2 - ASSERT 'SINGLE CLK'.
GENERATE 3 T-CLK/R-CLK CYCLES - THIS TOGGLES 'ENABLE (1)' WHICH
RESETS ALL THE CPU CONTROL FLOPS AND LATCHES THE CRAM
BITS FOR THE 1ST MICRO-INSTR.
WRT 206/1 - ASSERT 'CLK RUN'.
GENERATE 33 T-CLK/R-CLK CYCLES -
THE FIRST 5 INSTRS CLEAR ANY LEFT OVER PAGE FAULT
CONDITIONS AND LOAD A ZERO ENTRY INTO THE PAGE
TABLE AT PAGE -1. THE NEXT 2 INSTRS ATTEMPT A PAGED
MEMORY REFERENCE TO PAGE -1. THIS SHOULD CAUSE A PAGE
FAIL (SINCE 'PAGE VALID' IS NEGATED) WHICH SHOULD
CAUSE 'CRA/M CLK ENABLE' TO ASSERT WHILE 'DPE/M CLK
ENABLE' IS NEGATED.
RESPONSE:
'CRA/M CLK ENABLE' DID NOT ASSERT AND 'DPE/M CLK ENABLE' DID NOT
NEGATE.
!
[2
!STIMULUS:
LOAD MICRO-INSTRS TO CAUSE A PAGE FAIL TRAP
X1 0 - SET CRAM ADDR = 0.
STOP CLOCK AND SYNC IT SO T-CLK AND R-CLK ARE NEGATED.
WRT 206/2 - ASSERT 'SINGLE CLK'.
GENERATE 3 T-CLK/R-CLK CYCLES - THIS TOGGLES 'ENABLE (1)' WHICH
RESETS ALL THE CPU CONTROL FLOPS AND LATCHES THE CRAM
BITS FOR THE 1ST MICRO-INSTR.
WRT 206/1 - ASSERT 'CLK RUN'.
GENERATE 33 T-CLK/R-CLK CYCLES -
THE FIRST 3 INSTRS CLEAR ANY LEFT OVER PAGE FAULT
CONDITIONS AND LOAD A ZERO ENTRY INTO THE PAGE
TABLE AT PAGE -1. THE NEXT 2 INSTRS ATTEMPT A PAGED
MEMORY REFERENCE TO PAGE -1. THIS SHOULD CAUSE A PAGE
FAIL (SINCE 'PAGE VALID' IS NEGATED) WHICH SHOULD
CAUSE 'CRA/M CLK ENABLE' TO ASSERT WHILE 'DPE/M CLK
ENABLE' IS NEGATED.
RESPONSE:
'CRA/M CLK ENABLE' ASSERTED BUT 'DPE/M CLK ENABLE' DIDN'T
NEGATE.
!
[3
!STIMULUS:
LOAD MICRO-INSTRS TO CAUSE A PAGE FAIL TRAP
X1 0 - SET CRAM ADDR = 0.
STOP CLOCK AND SYNC IT SO T-CLK AND R-CLK ARE NEGATED.
WRT 206/2 - ASSERT 'SINGLE CLK'.
GENERATE 3 T-CLK/R-CLK CYCLES - THIS TOGGLES 'ENABLE (1)' WHICH
RESETS ALL THE CPU CONTROL FLOPS AND LATCHES THE CRAM
BITS FOR THE 1ST MICRO-INSTR.
WRT 206/1 - ASSERT 'CLK RUN'.
GENERATE 33 T-CLK/R-CLK CYCLES -
THE FIRST 3 INSTRS CLEAR ANY LEFT OVER PAGE FAULT
CONDITIONS AND LOAD A ZERO ENTRY INTO THE PAGE
TABLE AT PAGE -1. THE NEXT 2 INSTRS ATTEMPT A PAGED
MEMORY REFERENCE TO PAGE -1. THIS SHOULD CAUSE A PAGE
FAIL (SINCE 'PAGE VALID' IS NEGATED) WHICH SHOULD
CAUSE 'CRA/M CLK ENABLE' TO ASSERT WHILE 'DPE/M CLK
ENABLE' IS NEGATED.
RESPONSE:
'DPE/M CLK ENABLE' NEGATED BUT 'CRA/M CLK ENABLE' DIDN'T ASSERT.
!
]97
[1
!STIMULUS:
LOAD MICRO-INSTRS TO SET 'DPE9 TRAP 1' AND DO A TRAP CYCLE SKIP
TO 3776.
TP 1 - ASSERT 'CSL4 TRAP EN'.
X1 0 - SET NEXT CRAM ADDR TO 0.
CP 4 - EXECUTION OF THE FIRST MICRO-INSTR ASSERTS
'DPEB TRAP EN'. THE 2ND INSTR ASSERTS
'DPE9 TRAP 1'. THE 3RD INSTR ASSERTS 'SPEC/
NICOND' WHICH SHOULD ASSERT 'TRAP CYCLE'.
THE 4TH INSTR DOES A TRAP CYCLE SKIP.
RESPONSE:
THE NEXT CRAM ADDR DID NOT SKIP TO 3777. THIS IMPLIES THAT
'TRAP EN' DID NOT ASSERT.
!
[2
!STIMULUS:
LOAD MICRO-INSTR TO ASSERT 'SPEC/NICOND' AND DO A TRAP CYCLE
SKIP TO 3776.
TP 0 - NEGATE 'CSL4 TRAP EN'. THIS WILL NEGATE
'DPE9 TRAP 1,2 AND 3'.
X1 3 - SET NEXT CRAM ADDR TO 3.
CP 2 - THE 1ST INSTR WILL ASSERT 'SPEC/NICOND'. WITH
ALL TRAPS NEGATED, 'NICOND 9' IS ASSERTED. SO
'TRAP CYCLE' WILL BE NEGATED. WITH 'TRAP
CYCLE' NEGATED, THE 2ND INSTR WHICH DOES A
TRAP CYCLE SKIP, SHOULD NOT SKIP.
RESPONSE:
THE NEXT CRAM ADDR DID SKIP TO 3777. THIS IMPLIES THAT THE
'TRAP EN' SIGNAL DID NOT NEGATE.
!
]98
[1
!STIMULUS:
LOAD MICRO-INSTR TO EXECUTE A CONSOLE EXECUTE MODE SKIP.
WRT 212/2 - ASSERT 'EXECUTE' PRE-FLOP
CP 1 - ASSERT 'EXECUTE'
X1 0 - SET CRAM ADDR TO 0
CP 1 - EXECUTE THE EXECUTE MODE SKIP.
RESPONSE:
THE NEXT CRAM ADDRESS DID NOT SKIP TO 3777. THIS IMPLIES THAT
THE 'EXECUTE' SIGNAL DID NOT ASSERT ON THE CRA BOARD.
!
[2
!STIMULUS:
LOAD MICRO-INSTR TO EXECUTE A CONSOLE EXECUTE MODE SKIP.
WRT 212/0 - NEGATE 'EXECUTE' PRE-FLOP
CP 1 - NEGATE 'EXECUTE'
X1 0 - SET CRAM ADDR TO 0
CP 1 - EXECUTE THE EXECUTE MODE SKIP.
RESPONSE:
THE NEXT CRAM ADDRESS DID SKIP TO 3777. THIS IMPLIES THAT
THE 'EXECUTE' SIGNAL DID NOT NEGATE ON THE CRA BOARD.
!
]99
[1
!STIMULUS:
LOAD MICRO-INSTR TO EXECUTE A 'NOT CONTINUE' SKIP.
WRT 212/2 - ASSERT 'CONTINUE' PRE-FLOP
CP 1 - ASSERT 'CONTINUE'
X1 0 - SET CRAM ADDR TO 0
CP 1 - EXECUTE THE NOT CONTINUE SKIP. SINCE
'CONTINUE' IS ASSERTED, NO SKIP SHOULD OCCUR.
RESPONSE:
THE NEXT CRAM ADDRESS DID SKIP TO 3777. THIS IMPLIES THAT THE
'CONTINUE' SIGNAL DID NOT ASSERT ON THE CRA BOARD.
!
[2
!STIMULUS:
LOAD MICRO-INSTR TO EXECUTE A 'NOT CONTINUE' SKIP.
WRT 212/0 - NEGATE 'CONTINUE' PRE-FLOP
CP 1 - NEGATE 'CONTINUE'
X1 0 - SET CRAM ADDR TO 0
CP 1 - EXECUTE THE NOT CONTINUE SKIP. SINCE
'CONTINUE' IS NEGATED, WE SHOULD SKIP TO 3777.
RESPONSE:
THE NEXT CRAM ADDRESS DID NOT SKIP TO 3777. THIS IMPLIES THAT
THE 'CONTINUE' SIGNAL DID NOT NEGATE ON THE CRA BOARD.
!
]100
[1
!STIMULUS:
LOAD MICRO-INSTR TO EXECUTE A 'NOT 1 MSEC TIMER' SKIP.
WRT 100/4 - ENABLE 1 MSEC TIMER. THIS SHOULD CAUSE 'DPMC
1 MSEC' TO ASSERT.
X1 0 - SET CRAM ADDR TO 0
CP 1 - EXECUTE THE NOT 1 MSEC TIMER SKIP. SINCE
'1 MSEC' IS ASSERTED, NO SKIP SHOULD OCCUR.
RESPONSE:
THE NEXT CRAM ADDRESS DID SKIP TO 3777. THIS IMPLIES THAT THE
'1 MSEC EN' SIGNAL DID NOT ASSERT.
!
[2
!STIMULUS:
LOAD MICRO-INSTR TO EXECUTE A 'NOT 1 MSEC TIMER' SKIP.
WRT 100/0 - NEGATE '1 MSEC TIMER' ENABLE. THIS SHOULD
CAUSE 'DPMC 1 MSEC' TO NEGATE.
X1 0 - SET CRAM ADDR TO 0
CP 1 - EXECUTE THE NOT 1 MSEC TIMER SKIP. SINCE
'1 MSEC' IS NEGATED, WE SHOULD SKIP TO 3777.
RESPONSE:
THE NEXT CRAM ADDRESS DID NOT SKIP TO 3777. THIS IMPLIES THAT
THE '1 MSEC EN' SIGNAL DID NOT NEGATE.
!
]101
[1
!STIMULUS:
LOAD MICRO-INSTRUCTIONS TO JUMP FROM 0 TO 2, DO A CALL FROM 2 TO
4, DO A CALL FROM 4 TO 6, AND DO A RETURN FROM 6.
X1 0 - SET THE CRAM ADDRESS TO ZERO.
CP 3 - THREE CLOCK PULSES EXECUTE THE CALL INSTRS AT LOCS 2
AND 4.
WRT 204/2 - DO A STACK RESET.
WRT 204/0
CP 1 - EXECUTE THE RETURN INSTR AT LOC 6. AFTER THE STACK
RESET, THIS SHOULD CAUSE THE NEXT CRAM ADDR TO BE 2
INSTEAD OF 4.
RESPONSE:
THE NEXT CRAM ADDRESS AFTER EXECUTING THE RETURN IS NOT 2.
THIS IMPLIES THAT 'STACK RESET' DID NOT ASSERT.
!
]102
[1
!STIMULUS:
LOAD MICRO-INSTRS TO DO A MEMORY READ.
X1 0 - SET THE CRAM ADDRESS TO 0.
STOP CLOCK AND SYNC IT WITH T-CLK AND R-CLK NEGATED.
WRT 206/2 - ASSERT 'SINGLE CLK'.
GENERATE 3 T-CLK/R-CLK CYCLES - THIS INITS ALL THE CLOCK CONTROL
FLOPS AND LATCHES THE CRAM BITS FOR THE FIRST MICRO-
INSTRUCTION.
WRT 206/1 - ASSERT 'CLK RUN'.
GENERATE 9 T-CLK/R-CLK CYCLES - THIS EXECUTES THE FIRST 3 MICRO-
INSTRUCTIONS. AFTER THE LAST ONE, THE CPU SHOULD BE
WAITING FOR THE MEMORY TO RESPOND WITH THE READ DATA.
THE CPU CLOCK ENABLES SHOULD NOW BE DISABLED FOR AT
LEAST 8 T-CLK/R-CLK CYCLES.
GENERATE \O0 T-CLK/R-CLK CYCLES - 'CRA/M CLK ENABLE' SHOULD
STAY NEGATED.
RESPONSE:
'CRA/M CLK ENABLE' ASSERTED BEFORE IT SHOULD HAVE.
!
[2
!STIMULUS:
LOAD MICRO-INSTRS TO DO A MEMORY READ.
X1 0 - SET THE CRAM ADDRESS TO 0.
STOP CLOCK AND SYNC IT WITH T-CLK AND R-CLK NEGATED.
WRT 206/2 - ASSERT 'SINGLE CLK'.
GENERATE 3 T-CLK/R-CLK CYCLES - THIS INITS ALL THE CLOCK CONTROL
FLOPS AND LATCHES THE CRAM BITS FOR THE FIRST MICRO-
INSTRUCTION.
WRT 206/1 - ASSERT 'CLK RUN'.
GENERATE 9 T-CLK/R-CLK CYCLES - THIS EXECUTES THE FIRST 3 MICRO-
INSTRUCTIONS. AFTER THE LAST ONE, THE CPU SHOULD BE
WAITING FOR THE MEMORY TO RESPOND WITH THE READ DATA.
THE CPU CLOCK ENABLES SHOULD NOW BE DISABLED FOR AT
LEAST 8 T-CLK/R-CLK CYCLES.
GENERATE 8 T-CLK/R-CLK CYCLES - 'CRA/M CLK ENABLE' SHOULD
STAY NEGATED WAITING FOR MEMORY TO RESPOND.
GENERATE 8 T-CLK/R-CLK CYCLE - 'CRA/M CLK ENABLE' SHOULD ASSERT.
RESPONSE:
'CRA/M CLK ENABLE' DID NOT ASSERT.
!