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]1
[1
!STIMULUS:
	LOAD \O0 FROM #-FIELD THRU DBM MUX
RESPONSE:
	OUTPUT OF DBM MUX SHOULD BE \O0
!
]2
[1
!STIMULUS:
	LOAD \O0 ONTO DP-SWAPPED AND THRU DBM MUX
RESPONSE:
	OUTPUT OF DBM MUX SHOULD BE \O0
!
]3
[1
!STIMULUS:
	LOAD \O0 ONTO DP AND THRU DBM MUX
RESPONSE:
	OUTPUT OF DBM MUX SHOULD BE \O0
!
]4
[1
!STIMULUS:
	PASS \O0 FROM # THRU SCAD A-MUX AND SCAD
RESPONSE:
	OUTPUT OF SCAD SHOULD BE \O0
!
]5
[1
!STIMULUS:
	PASS \O0 FROM # TO SCAD AND DECREMENT
RESPONSE:
	OUTPUT OF SCAD SHOULD BE \O1
!
]6
[1
!STIMULUS:
	PASS \O0 FROM # TO SCAD AND DOUBLE
RESPONSE:
	OUTPUT OF SCAD SHOULD BE \O1
!
]7
[1
!STIMULUS:
	LOAD \O0 INTO SC, THEN PASS IT THRU SCAD
RESPONSE:
	OUTPUT OF SCAD SHOULD BE \O0
!
]8
[1
!STIMULUS:
	GET POINTER 44 FROM SCADA WITH \O1 ON DP, \O2 IN SC
RESPONSE:
	OUTPUT OF SCAD SHOULD BE \O0
!
]9
[1
!STIMULUS:
	PUT \O1 ON DP AND PICK UP EACH BYTE FROM SCADA
RESPONSE:
	WORD REBUILT FROM 5 BYTES SHOULD BE \O0
!
]10
[1
!STIMULUS:
	LOAD \O0 INTO FE; OR WITH \O1
RESPONSE:
	OUTPUT OF SCAD SHOULD BE \O2
!
]11
[1
!STIMULUS:
	LOAD \O0 ONTO DP; PASS IT THRU SCADB SHIFT-COUNT
RESPONSE:
	OUTPUT OF SCAD SHOULD BE \O1
!
]12
[1
!STIMULUS:
	LOAD \O0 ONTO DP, PASS THRU SCADB BYTE-SIZE
RESPONSE:
	OUTPUT OF SCAD SHOULD BE \O1
!
]13
[1
!STIMULUS:
	LOAD \O0 ONTO DP, PASS THRU SCADB EXP
RESPONSE:
	OUTPUT OF SCAD SHOULD BE \O1
!
]14
[1
!STIMULUS:
	LOAD \O0 ONTO DP & SCAD; PASS THRU BYTES INPUT TO DBM MUX
RESPONSE:
	OUTPUT OF DBM MUX SHOULD BE \O1
!
]15
[1
!STIMULUS:
	LOAD \O0 ONTO DP, \O1 THRU SCAD; INSERT INTO ALL BYTES
RESPONSE:
	OUTPUT OF DBM MUX SHOULD BE \O2
!
]16
[1
!STIMULUS:
	LOAD \O0 INTO FE, THEN AND WITH \O1
RESPONSE:
	OUTPUT OF SCAD SHOULD BE \O2
!
]17
[1
!STIMULUS:
	LOAD SC WITH \O0, LOAD FE WITH \O1, SCAD \S3
RESPONSE:
	OUTPUT OF SCAD SHOULD BE \O2
!
]18
[1
!STIMULUS:
	LOAD \O1 INTO VMA (SWEEP LATCH) AND THRU DBM MUX WITH #=\O2
RESPONSE:
	DBM OUTPUT BITS 0, 2, 8:35 SHOULD BE \O0
	DBM OUTPUT BITS 1, 6 SHOULD BE 0
!
]19
[1
!STIMULUS:
	LOAD 0 FROM DP, SCAD THRU DBM MUX EXP INPUT
RESPONSE:
	OUTPUT OF DBM MUX LEFT HALFWORD SHOULD BE 0
!
[2
!STIMULUS:
	LOAD -1 FROM DP, SCAD THRU DBM MUX EXP INPUT
RESPONSE:
	OUTPUT OF DBM MUX LEFT HALFWORD SHOULD BE 377777
!
]20
[1
!STIMULUS:
	LOAD 0 INTO VMA BITS 0, 2, 8 (SWEEP LATCH)
	AND THRU DBM MUX WITH # = \O0; DP = \O1
RESPONSE:
	DBM OUTPUT BITS 0, 2, 8 SHOULD BE \O2
	DBM OUTPUT BITS 10:13 SHOULD BE 0
CORRECT & ACTUAL ARE VMA FLAGS BITS 0:14
!
]21
[1
!STIMULUS:
	8080:	WRITE -1 TO MEM LOC 0
	KS10:	WRITE -1 TO AC0 VIA IR AC FIELD
		LOAD 0 INTO VMA, THEN WRITE 0 TO AC0 VIA VMA
	8080:	READ MEM LOC 0
RESPONSE:
	MEM LOC 0 SHOULD BE -1
!
[2
!STIMULUS:
	8080:	WRITE -1 TO MEM LOC 0
	KS10:	WRITE 0 TO AC0 VIA IR AC FIELD
		LOAD 0 INTO THE VMA, THEN READ AC0 VIA VMA
RESPONSE:
	AC0 SHOULD BE 0
!
]22
[1
!STIMULUS:
	8080:	DEPOSIT 376 TO I/O REGISTER 100000
		(SETTING ALL MMC ECC FORCE BITS)
	KS10:	DEPOSIT 0 TO MEM LOC 0 (WITH WRONG ECC)
		READ MEM LOC 0 (CAUSING AN ERROR)
	8080:	READ I/O REGISTER 100000 BITS <14:35>
RESPONSE:
	SHOULD GET 0 (ADDR OF LAST ERROR)
!
[2
!STIMULUS:
	8080:	DEPOSIT 376 TO I/O REGISTER 100000
		(SETTING ALL MMC ECC FORCE BITS)
	KS10:	DEPOSIT 0 TO MEM LOC 0 (WITH WRONG ECC)
		READ MEM LOC 0 (CAUSING AN ERROR)
RESPONSE:
	REFERENCE WAS MADE TO NXM (NOT MEM LOC 0)
!
]23
[1
!STIMULUS:
	8080:	WRITE \O0 TO MEM LOC 0
	KS10:	WRITE \O1 TO AC0 VIA IR AC FIELD
		LOAD 0 INTO THE VMA, THEN READ MEM LOC 0
RESPONSE:
	SHOULD GET \O0
!
]24
[1
!STIMULUS:
	8080:	WRITE 0 TO MEM LOC 0
	KS10:	WRITE \O0 TO MEM LOC 0
	8080:	READ MEM LOC 0
RESPONSE:
	SHOULD GET \O0
!
]25
[1
!STIMULUS:
	8080:	WRITE 0 TO MEM LOCS 0, \O0
	KS10:	WRITE -1 TO PHYSICAL EXTENDED MEM LOC \O0
	8080:	READ MEM LOCS 0, \O0
RESPONSE:
	MEM LOC 0 SHOULD BE 0 (IT IS \O1)
	MEM LOC \O0 SHOULD BE -1
!
]26
[1
!STIMULUS:
	8080:	WRITE 0 TO MEM LOCS 0, \O0
	KS10:	WRITE -1 TO EXTENDED MEM LOC \O0
	8080:	READ MEM LOCS 0, \O0
RESPONSE:
	MEM LOC 0 SHOULD BE 0 (IT IS \O1)
	MEM LOC \O0 SHOULD BE -1
!
]27
[1
!STIMULUS:
	\S0 TO MEM LOC 0 CONTROLLED BY #
RESPONSE:
	READ VMA DURING MEMORY CYCLE
	CORRECT & ACTUAL ARE VMA<3:7>
!
]28
[1
!STIMULUS:
	\S0 TO MEM LOC 0 CONTROLLED BY DP
RESPONSE:
	READ VMA DURING MEMORY CYCLE
	CORRECT & ACTUAL ARE VMA<3:7>
!
]29
[1
!STIMULUS:
	LOAD OPCODE \O0 INTO THE IR
	START A MEMORY CYCLE CONTROLLED BY DROM
	ABORT THE MEMORY CYCLE
RESPONSE:
	READ VMA DURING MEMORY CYCLE
	CORRECT & ACTUAL ARE VMA<3:7>
!
]30
[1
!STIMULUS:
	8080:	WRITE -1 TO MEM LOC 0
	KS10:	CONDITIONALLY WRITE 0 TO MEM LOC 0
		TO START CYCLE, #=\O0, MEM=\O1, DROM COND FUNC=\O2
	8080:	READ MEM LOC 0
RESPONSE:
	MEM LOC 0 SHOULD BE \O3
!
]31
[1
!STIMULUS:
	8080:	WRITE -1 TO MEM LOCS 0, \O0
	KS10:	WRITE \O0 TO MEM LOC 0
	8080:	READ MEM LOC 0
RESPONSE:
	MEM LOC 0 SHOULD BE \O0
!
[2
!STIMULUS:
	8080:	WRITE -1 TO MEM LOCS 0, \O0
	KS10:	WRITE 1 TO MEM LOC 0
	8080:	READ MEM LOC \O0
RESPONSE:
	MEM LOC \O0 SHOULD BE -1
!
]32
[1
!STIMULUS:
	8080:	DEPOSIT 376 TO I/O REGISTER 100000
		(SETTING ALL MMC ECC FORCE BITS)
	KS10:	LOAD \O1 INTO PAGE TABLE LOC \O3
		DEPOSIT 0 TO VIRTUAL MEM LOC \O2 (WITH WRONG ECC)
		READ VIRTUAL MEM LOC \O2 (CAUSING AN ERROR)
RESPONSE:
	PAGE FAIL U-TRAP TO CRAM ADDR 7777 (SHOULDN'T HAPPEN)
	PAGE FAIL CODE \O4 (\S5)
!
[2
!STIMULUS:
	8080:	DEPOSIT 376 TO I/O REGISTER 100000
		(SETTING ALL MMC ECC FORCE BITS)
	KS10:	LOAD \O1 INTO PAGE TABLE LOC \O3
		DEPOSIT 0 TO VIRTUAL MEM LOC \O2 (WITH WRONG ECC)
		READ VIRTUAL MEM LOC \O2 (CAUSING AN ERROR)
RESPONSE:
	REFERENCE WAS MADE TO NXM (NOT MEM LOC 0)
!
[3
!STIMULUS:
	8080:	DEPOSIT 376 TO I/O REGISTER 100000
		(SETTING ALL MMC ECC FORCE BITS)
	KS10:	LOAD \O1 INTO PAGE TABLE LOC \O3
		DEPOSIT 0 TO VIRTUAL MEM LOC \O2 (WITH WRONG ECC)
		READ VIRTUAL MEM LOC \O2 (CAUSING AN ERROR)
	8080:	READ I/O REGISTER 100000 BITS <14:35>
RESPONSE:
	SHOULD GET \O0 (PHYSICAL ADDR OF LAST ERROR)
!
]33
[1
!STIMULUS:
	KS10:	LOAD \O2 INTO PAGE TABLE LOC \O3
	8080:	DEPOSIT 376 TO I/O REGISTER 100000
		(SETTING ALL MMC ECC FORCE BITS)
	KS10:	DEPOSIT 0 TO VIRTUAL MEM LOC \O1 (WITH WRONG ECC)
		READ VIRTUAL MEM LOC \O1 (CAUSING AN ERROR)
RESPONSE:
	PAGE FAIL U-TRAP TO CRAM ADDR 7777 (SHOULDN'T HAPPEN)
	PAGE FAIL CODE \O4 (\S5)
!
[2
!STIMULUS:
	KS10:	LOAD \O2 INTO PAGE TABLE LOC \O3
	8080:	DEPOSIT 376 TO I/O REGISTER 100000
		(SETTING ALL MMC ECC FORCE BITS)
	KS10:	DEPOSIT 0 TO VIRTUAL MEM LOC \O1 (WITH WRONG ECC)
		READ VIRTUAL MEM LOC \O1 (CAUSING AN ERROR)
RESPONSE:
	REFERENCE WAS MADE TO NXM (NOT MEM LOC 0)
!
[3
!STIMULUS:
	KS10:	LOAD \O2 INTO PAGE TABLE LOC \O3
	8080:	DEPOSIT 376 TO I/O REGISTER 100000
		(SETTING ALL MMC ECC FORCE BITS)
	KS10:	DEPOSIT 0 TO VIRTUAL MEM LOC \O1 (WITH WRONG ECC)
		READ VIRTUAL MEM LOC \O1 (CAUSING AN ERROR)
	8080:	READ I/O REGISTER 100000 BITS <14:35>
RESPONSE:
	SHOULD GET \O0 (PHYSICAL ADDR OF LAST ERROR)
!
]34
[1
!STIMULUS:
	KS10:	LOAD \O2 INTO PAGE TABLE LOC \O3
		WRITE/WRITE TEST TO VIRTUAL ADDR \O1 (CAUSING AN ERROR)
RESPONSE:
	PAGE FAIL U-TRAP TO CRAM ADDR 7777
	CORRECT: PAGE FAIL CODE \O6 (\S7)
	ACTUAL:  PAGE FAIL CODE \O4 (\S5)
!
[2
!STIMULUS:
	KS10:	LOAD \O2 INTO PAGE TABLE LOC \O3
		WRITE/WRITE TEST TO VIRTUAL ADDR \O1 (CAUSING AN ERROR)
RESPONSE:
	SHOULD GET PAGE FAIL U-TRAP TO CRAM ADDR 7777 (DIDN'T)
	CORRECT: PAGE FAIL CODE \O6 (\S7)
!
]35
[1
!STIMULUS:
	CSL EXECUTE = \O0
	DPE USER = \O5, DPE PCU = \O6
	# = \O7, SPEC FIELD = \O8, LOAD VMA FLAGS
RESPONSE:
	CORRECT: PREV = \O1, USER = \O2
	ACTUAL:  PREV = \O3, USER = \O4
!
]36
[1
!STIMULUS:
	KS10:	LOAD 400000 INTO PAGE TABLE LOC \O1, USER = \O2
		WRITE/WRITE TEST TO VIRTUAL ADDR \O0, USER = \O3
RESPONSE:
	PAGE FAIL U-TRAP TO CRAM ADDR 7777
	CORRECT: PAGE FAIL CODE \O4 (\S5)
	ACTUAL:  PAGE FAIL CODE \O6 (\S7)
!
[2
!STIMULUS:
	KS10:	LOAD 400000 INTO PAGE TABLE LOC \O1, USER = \O2
		WRITE/WRITE TEST TO VIRTUAL ADDR \O0, USER = \O3
RESPONSE:
	PAGE FAIL U-TRAP TO CRAM ADDR 7777 (DIDN'T)
	CORRECT: PAGE FAIL CODE \O4 (\S5)
!
]37
[1
!STIMULUS:
	8080:	WRITE -1 TO MEM LOC 777
	KS10:	LOAD 440000 INTO PAGE TABLE LOC 0
		WRITE 0 TO MEM LOC 777 WITH WRITE-TEST OFF
RESPONSE:
	MEM LOC 777 SHOULD BE 0 (BUT IT IS \O0)
	SHOULD NOT GET PAGE FAIL TRAP (BUT IT DID)
	CORRECT: PAGE FAIL \O1 (\S2)
	ACTUAL:  PAGE FAIL \O3 (\S4)
!
[2
!STIMULUS:
	8080:	WRITE -1 TO MEM LOC 777
	KS10:	LOAD 440000 INTO PAGE TABLE LOC 0
		WRITE 0 TO MEM LOC 777 WITH WRITE-TEST OFF
RESPONSE:
	MEM LOC 777 SHOULD BE 0 (BUT IT IS \O0)
	CORRECT: PAGE FAIL \O1 (\S2)
	ACTUAL:  PAGE FAIL \O3 (\S4)
!
[3
!STIMULUS:
	8080:	WRITE -1 TO MEM LOC 777
	KS10:	LOAD 440000 INTO PAGE TABLE LOC 0
		WRITE 0 TO MEM LOC 777 WITH WRITE-TEST OFF
RESPONSE:
	MEM LOC 777 SHOULD BE 0 (IT IS)
	CORRECT: PAGE FAIL \O1 (\S2)
	ACTUAL:  PAGE FAIL \O3 (\S4)
!
]38
[1
!STIMULUS:
	KS10:	LOAD 443777 INTO PAGE TABLE LOC 777
		WRITE 0 TO VIRTUAL MEM LOC 777777
RESPONSE:
	SHOULD GET PAGE FAIL TRAP
	CORRECT: PAGE FAIL \O1 (\S2)
	ACTUAL:  PAGE FAIL \O3 (\S4)
!
[2
!STIMULUS:
	KS10:	LOAD 443777 INTO PAGE TABLE LOC 777
		WRITE 0 TO VIRTUAL MEM LOC 777777
RESPONSE:
	SHOULD GET PAGE FAIL TRAP (DIDN'T)
	CORRECT: PAGE FAIL \O1 (\S2)
	ACTUAL:  PAGE FAIL \O3 (\S4)
!
[3
!STIMULUS:
	KS10:	CAUSE NXM ERROR, DO NOTHING, SEE IF IT STAYS
RESPONSE:
	PAGE FAIL CONDITION SHOULD STAY (DIDN'T)
	CORRECT: PAGE FAIL \O1 (\S2)
	ACTUAL:  PAGE FAIL \O3 (\S4)
!
[4
!STIMULUS:
	KS10:	CAUSE NXM ERROR AND THEN DO SPEC/MEM CLR
RESPONSE:
	SHOULD CLEAR PAGE FAIL TRAP CONDITION (DIDN'T)
	CORRECT: PAGE FAIL \O1 (\S2)
	ACTUAL:  PAGE FAIL \O3 (\S4)
!
[5
!STIMULUS:
	KS10:	CAUSE NXM ERROR, CLEAR IT (SPEC/MEM CLR),
		DO NOTHING, SEE IF IT STAYS AWAY
RESPONSE:
	PAGE FAIL CONDITION SHOULD STAY AWAY (DIDN'T)
	CORRECT: PAGE FAIL \O1 (\S2)
	ACTUAL:  PAGE FAIL \O3 (\S4)
!
]39
[1
!STIMULUS:
	8080:	DEPOSIT 176 TO I/O REGISTER 100000
		(SETTING EVEN NUMBER OF MMC ECC FORCE BITS)
		DEPOSIT 0 TO PHYSICAL MEM LOC 777 (WITH WRONG ECC)
	KS10:	LOAD 460000 INTO PAGE TABLE LOC 0
		READ VIRTUAL MEM LOC 777 (CAUSING DOUBLE-BIT ERROR)
RESPONSE:
	SHOULD GET PAGE FAIL TRAP
	CORRECT: PAGE FAIL \O1 (\S2)
	ACTUAL:  PAGE FAIL \O3 (\S4)
!
[2
!STIMULUS:
	8080:	DEPOSIT 176 TO I/O REGISTER 100000
		(SETTING EVEN NUMBER OF MMC ECC FORCE BITS)
		DEPOSIT 0 TO PHYSICAL MEM LOC 777 (WITH WRONG ECC)
	KS10:	LOAD 460000 INTO PAGE TABLE LOC 0
		READ VIRTUAL MEM LOC 777 (CAUSING DOUBLE-BIT ERROR)
RESPONSE:
	SHOULD GET PAGE FAIL TRAP (DIDN'T)
	CORRECT: PAGE FAIL \O1 (\S2)
	ACTUAL:  PAGE FAIL \O3 (\S4)
!
[3
!STIMULUS:
	KS10:	CAUSE BAD DATA ERROR, DO NOTHING, SEE IF IT STAYS
RESPONSE:
	PAGE FAIL CONDITION SHOULD STAY (DIDN'T)
	CORRECT: PAGE FAIL \O1 (\S2)
	ACTUAL:  PAGE FAIL \O3 (\S4)
!
[4
!STIMULUS:
	KS10:	CAUSE BAD DATA ERROR AND THEN DO SPEC/MEM CLR
RESPONSE:
	SHOULD CLEAR PAGE FAIL TRAP CONDITION (DIDN'T)
	CORRECT: PAGE FAIL \O1 (\S2)
	ACTUAL:  PAGE FAIL \O3 (\S4)
!
[5
!STIMULUS:
	KS10:	CAUSE BAD DATA ERROR, CLEAR IT (SPEC/MEM CLR),
		DO NOTHING, SEE IF IT STAYS AWAY
RESPONSE:
	PAGE FAIL CONDITION SHOULD STAY AWAY (DIDN'T)
	CORRECT: PAGE FAIL \O1 (\S2)
	ACTUAL:  PAGE FAIL \O3 (\S4)
!
]40
[1
!STIMULUS:
	KS10:	TURN PAGING ON AND LOAD 0 INTO PAGE TABLE LOC 0
		WRITE TO MEM LOC \O0 AND CHECK PAGE FAIL CODE
RESPONSE:
	CORRECT: PAGE FAIL \O1 (\S2)
	ACTUAL:  PAGE FAIL \O3 (\S4)
!
[2
!STIMULUS:
	KS10:	TURN PAGING ON AND LOAD 0 INTO PAGE TABLE LOC 0
		PHYSICAL WRITE TO MEM LOC \O0 AND CHECK PAGE FAIL CODE
RESPONSE:
	CORRECT: PAGE FAIL \O1 (\S2)
	ACTUAL:  PAGE FAIL \O3 (\S4)
!
[3
!STIMULUS:
	KS10:	LOAD 0 INTO PAGE TABLE LOC 0 AND TURN PAGING OFF
		WRITE TO MEM LOC \O0 AND CHECK PAGE FAIL CODE
RESPONSE:
	CORRECT: PAGE FAIL \O1 (\S2)
	ACTUAL:  PAGE FAIL \O3 (\S4)
!
]41
[1
!STIMULUS:
	MAKE PAGE 400 VALID & UNWRITABLE WITH MEM & #
	MAKE PAGE 0 INVALID & WRITABLE WITH SWEEP
	WRITE TO MEM LOC 400000
RESPONSE:
	SHOULD GET PAGE FAIL TRAP (DID)
	CORRECT: PAGE FAIL \O1 (\S2)
	ACTUAL:  PAGE FAIL \O3 (\S4)
!
[2
!STIMULUS:
	MAKE PAGE 400 VALID & UNWRITABLE WITH MEM & #
	MAKE PAGE 0 INVALID & WRITABLE WITH SWEEP
	WRITE TO MEM LOC 400000
RESPONSE:
	SHOULD GET PAGE FAIL TRAP (DIDN'T)
	CORRECT: PAGE FAIL \O1 (\S2)
	ACTUAL:  PAGE FAIL \O3 (\S4)
!
]42
[1
!STIMULUS:
	KS10:	TEST CACHE ENABLE CONDITION: \S2
		MAP PAGE \O4 TO PAGE 0
		WRITE -1 TO VIRTUAL MEM LOC \O3
	8080:	WRITE 0 TO PHYSICAL MEM LOC \O0
	KS10:	READ VIRTUAL MEM LOC \O3
RESPONSE:
	SHOULD GET \S5; DIDN'T
!
]43
[1
!STIMULUS:
	KS10:	TEST CACHE DIRECTORY RAM DATA I/O PINS
		MAP PAGE \O1 TO PAGE 0
		WRITE -1 TO VIRTUAL MEM LOC \O3
	8080:	WRITE 0 TO PHYSICAL MEM LOC \O0
	KS10:	READ VIRTUAL MEM LOC \O3
RESPONSE:
	SHOULD GET -1 (CACHE HIT); DIDN'T
!
]44
[1
!STIMULUS:
	CHECK CACHE DIRECTORY RAM ADDRESS LINES
	KS10:	MAP PHYSICAL PAGE 1 TO VIRTUAL PAGE 1
		WRITE \O0 TO VIRTUAL MEM LOC \O0 (CACHE ENABLED)
		... FOR LOCS 0 AND 2**N FOR EACH SIDE OF RAM PAIRS
	8080:	ZERO PHYSICAL PAGE 1
RESPONSE:
	KS10:	READ VIRTUAL MEM LOC \O0
!
]45
[1
!STIMULUS:
	MAP PAGE 1 TO PAGE 1
	WRITE -1 TO MEM LOC 1777
	WRITE 0 TO MEM LOC 1377 WITH SWEEP SET
	READ MEM LOC 1777, SKIP IF 0
RESPONSE:
	SHOULD SKIP (BUT IT DIDN'T)
!
]46
[1
!STIMULUS:
	KS10:	MAP PAGES \O1 AND 0 TO PAGE 0
		WRITE -1 TO VIRTUAL MEM LOC \O0
	8080:	WRITE 0 TO PHYSICAL MEM LOC 777
	KS10:	READ VIRTUAL MEM LOC 777, SKIP IF 0
RESPONSE:
	KS10:	SHOULD SKIP = GOT 0 = CACHE MISS (DIDN'T)
!
]47
[1
!STIMULUS:
	KS10:	MAP PAGE 0 TO PAGE 0
		WRITE -1 TO PHYSICAL MEM LOC \O0
	8080:	WRITE 0 TO PHYSICAL MEM LOC \O0
	KS10:	READ VIRTUAL MEM LOC \O0, SKIP IF 0
RESPONSE:
	KS10:	SHOULD SKIP = GOT 0 = CACHE MISS (DIDN'T)
!
]48
[1
!STIMULUS:
	LOAD \O2 INTO PAGE TABLE LOC \O3 (\S6)
	DEPOSIT 376 TO I/O REGISTER 100000
	(SETTING ALL MMC ECC FORCE BITS)
	DEPOSIT 0 TO VIRTUAL MEM LOC \O1 (WITH WRONG ECC) (\S6)
	READ VIRTUAL MEM LOC \O1 (CAUSING AN ERROR) (\S6)
RESPONSE:
	PAGE FAIL U-TRAP TO CRAM ADDR 7777 (SHOULDN'T HAPPEN)
	PAGE FAIL CODE \O4 (\S5)
!
[2
!STIMULUS:
	LOAD \O2 INTO PAGE TABLE LOC \O3 (\S6)
	DEPOSIT 376 TO I/O REGISTER 100000
	(SETTING ALL MMC ECC FORCE BITS)
	DEPOSIT 0 TO VIRTUAL MEM LOC \O1 (WITH WRONG ECC) (\S6)
	READ VIRTUAL MEM LOC \O1 (CAUSING AN ERROR) (\S6)
	READ I/O REGISTER 100000 BITS <14:35>
RESPONSE:
	SHOULD GET \O0 (PHYSICAL ADDR OF LAST ERROR)
!
]49
[1
!STIMULUS:
	LOAD \O2 INTO PAGE TABLE LOC \O3
	DEPOSIT 0 TO VIRTUAL MEM LOC 777
	DO A PAGE FAIL DISPATCH
RESPONSE:
	CORRECT: PAGE FAIL CODE \O8 (\S9)
	ACTUAL:  PAGE FAIL CODE \O4 (\S5)
!
]50
[1
!STIMULUS:
	KS10:	MAP PAGE \O0 TO PAGE 1, \S5 MODE
		WRITE -1 TO VIR MEM LOC \O1
	8080:	WRITE 0 TO PHY MEM LOC \O2
	KS10:	READ VIR MEM LOC \O1
RESPONSE:
	SHOULD GET -1 (CACHE HIT); DON'T
!
[2
!STIMULUS:
	KS10:	MAP PAGE \O0 TO PAGE 1, \S5 MODE
		WRITE -1 TO VIR MEM LOC \O1
	8080:	WRITE 0 TO PHY MEM LOC \O2
	KS10:	READ VIR MEM LOC \O1
RESPONSE:
	SHOULD GET -1 (CACHE HIT) BUT PAGE FAIL HAPPENED
	PAGE FAIL CODE \O3 (\S4)
!
]51
[1
!STIMULUS:
	KS10:	MAP PAGE 1 TO PAGE 1
		WRITE -1 TO PHY MEM LOC \O1
	8080:	WRITE 0 TO PHY MEM LOC \O2
	KS10:	READ VIR MEM LOC \O1
RESPONSE:
	SHOULD GET 0 (CACHE MISS); DON'T
!
[2
!STIMULUS:
	KS10:	MAP PAGE 1 TO PAGE 1
		WRITE -1 TO PHY MEM LOC \O1
	8080:	WRITE 0 TO PHY MEM LOC \O2
	KS10:	READ VIR MEM LOC \O1
RESPONSE:
	SHOULD GET 0 (CACHE MISS) BUT PAGE FAIL HAPPENED
	PAGE FAIL CODE \O3 (\S4)
!
]52
[1
!STIMULUS:
	KS10:	LOAD \O2 INTO PAGE TABLE LOC \O3
		DEPOSIT -1 TO VIRTUAL MEM LOC \O0
	8080:	DEPOSIT 0 TO PHYSICAL MEM LOC 777
	KS10:	READ VIRTUAL MEM LOC \O0
RESPONSE:
	SHOULD GET \S1 (BUT GOT PAGE FAIL)
	PAGE FAIL CODE \O4 (\S5)
!
[2
!STIMULUS:
	KS10:	LOAD \O2 INTO PAGE TABLE LOC \O3
		DEPOSIT -1 TO VIRTUAL MEM LOC \O0
	8080:	DEPOSIT 0 TO PHYSICAL MEM LOC 777
	KS10:	READ VIRTUAL MEM LOC \O0
RESPONSE:
	SHOULD GET \S1 (BUT DIDN'T)
!
]53
[1
!STIMULUS:
	KS10:	WRITE TO PHYSICAL MEM LOC 0
		STOP AFTER COMMAND/ADDRESS CYCLE
RESPONSE:
	SHOULDN'T INDICATE PARITY ERROR (BUT IT DID)
	MEM PARITY ERROR L = \O7; DP PARITY ERROR L = \O6
!
[2
!STIMULUS:
	KS10:	WRITE \U0 TO PHYSICAL MEM LOC 0
	8080:	READ REGISTER 100
RESPONSE:
	SHOULDN'T INDICATE PARITY ERROR (BUT IT DID)
	MEM PARITY ERROR L = \O7; DP PARITY ERROR L = \O6
!
[3
!STIMULUS:
	KS10:	WRITE \U0 TO PHYSICAL MEM LOC 0
		READ FROM PHYSICAL MEM LOC 0
	8080:	READ REGISTER 100
RESPONSE:
	SHOULDN'T INDICATE PARITY ERROR (BUT IT DID)
	MEM PARITY ERROR L = \O7; DP PARITY ERROR L = \O6
!
]54
[1
!STIMULUS:
	KS10:	LOAD APR FLAGS FROM DP WITH 7760
		READ APR FLAGS VIA DBM
RESPONSE:
	APR FLAGS SHOULD BE SET
!
[2
!STIMULUS:
	8080:	CLEAR INTERRUPT-10 BIT IN REG 205
	KS10:	LOAD APR FLAGS FROM DP WITH 7760
	8080:	EXAMINE INTERRUPT-10 APR FLAG
RESPONSE:
	INTERRUPT-10 SHOULD BE SET
!
[3
!STIMULUS:
	LOAD APR FLAGS FROM DP WITH 7760
	LOAD APR FROM PREVIOUS ???
	CHECK TO SEE IF THEY STAY SET
RESPONSE:
	THEY SHOULD STAY SET
!
[4
!STIMULUS:
	LOAD APR FLAGS FROM DP WITH 7760
	DO A MASTER RESET
RESPONSE:
	APR FLAGS SHOULD BE CLEARED
!
[5
!STIMULUS:
	DO A MASTER RESET TO CLEAR THE APR FLAGS
	LOAD FROM PREVIOUS ???
RESPONSE:
	APR FLAGS SHOULD STAY CLEAR
!
[6
!STIMULUS:
	LOAD APR FLAGS FROM DP WITH 0
	READ APR FLAGS VIA DBM
RESPONSE:
	APR FLAGS SHOULD BE CLEAR
!
[7
!STIMULUS:
	8080:	CLEAR INTERRUPT-10 BIT IN REG 205
	KS10:	LOAD APR FLAGS FROM DP WITH 0
	8080:	EXAMINE INTERRUPT-10 APR FLAG
RESPONSE:
	INTERRUPT-10 SHOULD BE CLEAR
!
[8
!STIMULUS:
	8080:	SET MMC FORCE BITS TO GET CORRECTABLE ECC ERROR
		DEPOSIT 0 TO PHYSICAL MEM LOC 0
	KS10:	READ PHYSICAL MEM LOC 0
		READ APR FLAGS
RESPONSE:
	MMC CORRECTED DATA APR FLAG SHOULD BE ASSERTED
!
[9
!STIMULUS:
	LOAD VMA WITH -1 AND PERFORM A MEMORY READ
RESPONSE:
	NXM APR FLAG SHOULD BE ASSERTED
!
[10
!STIMULUS:
	8080:	SET MMC FORCE BITS TO GET UNCORRECTABLE ECC ERROR
		DEPOSIT 0 TO PHYSICAL MEM LOC 0
	KS10:	READ PHYSICAL MEM LOC 0
		READ APR FLAGS
RESPONSE:
	MMC BAD DATA ERR APR FLAG SHOULD BE ASSERTED
!
]55
[1
!STIMULUS:
	LOAD APR FLAGS FROM DP WITH \O0
	LOAD APR ENABLES FROM DP WITH \O1
	READ APR FLAGS VIA DBM
	CHECK BITS 22 (TRAP), 23 (PAGE), 32 (IRQ)
RESPONSE:
!
]56
[1
!STIMULUS:
	KS10:	LOAD \O1 INTO PAGE TABLE LOC \O3, \S0 MODE
		READ VIRTUAL MEM LOC \O2, \S0 MODE
	8080:	READ REGISTER 303 BIT 0 (RAM PARITY ERROR)
RESPONSE:
	SHOULD BE 0 TO INDICATE NO PARITY ERROR (BUT IT WASN'T)
!
]57
[1
!STIMULUS:
	KS10:	LOAD \O2 INTO PAGE TABLE LOC \O3
		DEPOSIT 0 TO VIRTUAL MEM LOC \O0
	8080:	READ REGISTER 303 BIT 0 (RAM PARITY ERROR)
RESPONSE:
	SHOULD BE 0 TO INDICATE NO PARITY ERROR (BUT IT WASN'T)
!
]58
[1
!STIMULUS:
	KS10:	LOAD 460000 INTO PAGE TABLE LOC \O3, \S0 MODE
		WRITE, THEN READ VIRTUAL MEM LOC \O2, \S0 MODE
	8080:	READ REGISTER 303 BIT 0 (RAM PARITY ERROR)
RESPONSE:
	SHOULD BE 0 TO INDICATE NO PARITY ERROR (BUT IT WASN'T)
!
[2
!STIMULUS:
	KS10:	LOAD 460000 INTO PAGE TABLE LOC \O3, \S0 MODE
		WRITE -1 TO VIRTUAL MEM LOC \O2, \S0 MODE
	8080:	WRITE 0 TO PHYSICAL MEM LOC \O1
	KS10:	READ VIRTUAL MEM LOC \O2, \S0 MODE
RESPONSE:
	SHOULD GET 0 (CACHE HIT); DIDN'T (CACHE DIR PAR ERR?)
!
]59
[1
!STIMULUS:
	KS10:	LOAD 460001 INTO PAGE TABLE LOC \O3
		WRITE, THEN READ VIRTUAL MEM LOC \O2
	8080:	READ REGISTER 303 BIT 0 (RAM PARITY ERROR)
RESPONSE:
	SHOULD BE 0 TO INDICATE NO PARITY ERROR (BUT IT WASN'T)
!
[2
!STIMULUS:
	KS10:	LOAD 460001 INTO PAGE TABLE LOC \O3
		WRITE -1 TO VIRTUAL MEM LOC \O2
	8080:	WRITE 0 TO PHYSICAL MEM LOC \O1
	KS10:	READ VIRTUAL MEM LOC \O2
RESPONSE:
	SHOULD GET 0 (CACHE HIT); DIDN'T (CACHE DIR PAR ERR?)
!
]60
[1
!STIMULUS:
	SET ALL PXCT BITS TO \O0, PXCT ON = \O4
	LOAD VMA, PXCT SEL #<9:11> = \O1
RESPONSE:
	VMA PREV SHOULD BE \O2 BUT IT WAS \O3
!
]61
[1
!STIMULUS:
	SET CURRENT AC BLOCK TO 0; PREVIOUS AC BLOCK TO 1
	SET AC0 BLOCK 0 TO 0; AC0 BLOCK 1 TO -1
	SET XR PREVIOUS TO \O0 AND READ XR0
RESPONSE:
	SHOULD GET \O1 (BUT DIDN'T)
!
]62
[1
!STIMULUS:
	SET 'DPM SC SIGN'; JUMP TO 0 AND SKIP ON SC SIGN
RESPONSE:
	NEXT CRAM ADDRESS SHOULD BE 1 (BUT IT WASN'T)
!
[2
!STIMULUS:
	CLEAR 'DPM SC SIGN'; JUMP TO 0 AND SKIP ON SC SIGN
RESPONSE:
	NEXT CRAM ADDRESS SHOULD BE 0 (BUT IT WASN'T)
!
]63
[1
!STIMULUS:
	ASSERT AND NEGATE 'RESET'
	STOP CLOCK AND SYNC IT SO T-CLK AND R-CLK ARE NEGATED.
	WRT 206/2	- ASSERT 'SINGLE CLK'
	GENERATE 4 T-CLK/R-CLK CYCLES - THIS EXECUTES MICRO-INSTR AT 0.
			  THIS LOADS 'FE SIGN' WITH A 1.
	WRT 206/2	- ASSERT 'SINGLE CLK'
	GENERATE 4 T-CLK/R-CLK CYCLES - THIS EXECUTES MICRO-INSTR AT 1.
			  THIS ASSERTS 'MULTI SHIFT'.'MULTI SHIFT' AND
			  'FE SIGN' SHOULD ASSERT 'FS (1)'.  THIS WILL
			  HOLD 'ENABLE (1)' ASSERTED AND CAUSE 'CRA/M
			  CLK ENABLE' TO NEGATE WHILE 'DPE/M CLK ENABLE'
			  IS ASSERTED.
RESPONSE:
	'CRA/M CLK ENABLE' DIDN'T NEGATE.
!
[2
!STIMULUS:
	ASSERT AND NEGATE 'RESET'
	STOP CLOCK AND SYNC IT SO T-CLK AND R-CLK ARE NEGATED.
	WRT 206/2	- ASSERT 'SINGLE CLK'
	GENERATE 4 T-CLK/R-CLK CYCLES - THIS EXECUTES MICRO-INSTR AT 0.
			  THIS LOADS 'FE SIGN' WITH A 1.
	WRT 206/2	- ASSERT 'SINGLE CLK'
	GENERATE 4 T-CLK/R-CLK CYCLES - THIS EXECUTES MICRO-INSTR AT 1.
			  THIS ASSERTS 'MULTI SHIFT'.'MULTI SHIFT' AND
			  'FE SIGN' SHOULD ASSERT 'FS (1)'.  THIS WILL
			  HOLD 'ENABLE (1)' ASSERTED AND CAUSE 'CRA/M
			  CLK ENABLE' TO NEGATE WHILE 'DPE/M CLK ENABLE'
			  IS ASSERTED.
RESPONSE:
	'DPE/M CLK ENABLE' DIDN'T STAY ASSERTED.
!
[3
!STIMULUS:
	ASSERT AND NEGATE 'RESET'
	STOP CLOCK AND SYNC IT SO T-CLK AND R-CLK ARE NEGATED.
	WRT 206/2	- ASSERT 'SINGLE CLK'
	GENERATE 4 T-CLK/R-CLK CYCLES - THIS EXECUTES MICRO-INSTR AT 0.
			  THIS LOADS 'FE SIGN' WITH A 0.
	WRT 206/2	- ASSERT 'SINGLE CLK'
	GENERATE 2 T-CLK/R-CLK CYCLES - THIS EXECUTES MICRO-INSTR AT 1.
			  THIS ASSERTS 'MULTI SHIFT'.  WITH 'FE SIGN'
			  NEGATED, 'CRA/M CLK ENABLE' SHOULD ASSERT AND
			  'DPE/M CLK ENABLE' SHOULD NEGATE.
RESPONSE:
	'CRA/M CLK ENABLE' DIDN'T ASSERT.
!
[4
!STIMULUS:
	ASSERT AND NEGATE 'RESET'
	STOP CLOCK AND SYNC IT SO T-CLK AND R-CLK ARE NEGATED.
	WRT 206/2	- ASSERT 'SINGLE CLK'
	GENERATE 4 T-CLK/R-CLK CYCLES - THIS EXECUTES MICRO-INSTR AT 0.
			  THIS LOADS 'FE SIGN' WITH A 0.
	WRT 206/2	- ASSERT 'SINGLE CLK'
	GENERATE 2 T-CLK/R-CLK CYCLES - THIS EXECUTES MICRO-INSTR AT 1.
			  THIS ASSERTS 'MULTI SHIFT'.  WITH 'FE SIGN'
			  NEGATED, 'CRA/M CLK ENABLE' SHOULD ASSERT AND
			  'DPE/M CLK ENABLE' SHOULD NEGATE.
RESPONSE:
	'DPE/M CLK ENABLE' DIDN'T NEGATE.
!
]64
[1
!STIMULUS:
	CHECK OUTPUT PINS OF MILLISECOND COUNTER FOR STUCK \S0
RESPONSE:
	GET THE MILLISECOND COUNTER OUTPUT THROUGH DBM BITS 24:33
!
]65
[1
!STIMULUS:
	CHECK MILLISECOND COUNTER TIMING
RESPONSE:
	THE MILLISECOND COUNTER IS OFF BY MORE THAN 1%
!