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Trailing-Edge - PDP-10 Archives - klad_sources - klad.sources/regbit.r36
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!
!			  COPYRIGHT (c) 1977, 1978 BY
!	      DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASS.
!
! THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND  COPIED
! ONLY  IN  ACCORDANCE  WITH  THE  TERMS  OF  SUCH  LICENSE AND WITH THE
! INCLUSION OF THE ABOVE COPYRIGHT NOTICE.  THIS SOFTWARE OR  ANY  OTHER
! COPIES  THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY
! OTHER PERSON.  NO TITLE TO AND OWNERSHIP OF  THE  SOFTWARE  IS  HEREBY
! TRANSFERRED.
!
! THE INFORMATION IN THIS SOFTWARE IS SUBJECT TO CHANGE  WITHOUT  NOTICE
! AND  SHOULD  NOT  BE  CONSTRUED  AS  A COMMITMENT BY DIGITAL EQUIPMENT
! CORPORATION.
!
! DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE OR  RELIABILITY  OF  ITS
! SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL.
!

!++
! FACILITY:  DECSYSTEM 2020 DIAGNOSTIC RELEASE TAPE 'DSTIR'
!
! ABSTRACT:
!
!	THIS FILE CONTAINS SYMBOLIC BIT DEFINITIONS FOR THE KS10 8080 I/O
!	REGISTERS.  IT IS USED AS A 'REQUIRE' FILE FOR THE STIRS DIAGNOSTICS.
!
! ENVIRONMENT:  RUNS UNDER 'CSL' ON A TOPS-20 SYSTEM.
!
! AUTHOR:  RICH MURATORI	, CREATION DATE:  3-JAN-79
!
! MODIFIED BY:
!
!  RICH MURATORI, 3-JAN-79 : VERSION 0.1
!--
LITERAL

!WRITE REGISTER 100

	FORCE_PAR	= 1^1,		!FORCE PARITY RIGHT
	EN_1MS		= 1^2,		!1 MSEC ENABLE
	CACHE_ENB	= 1^3,		!CACHE ENABLE
	DP_PE_DET	= 1^4,		!DP PE DETECT
	CRM_PE_DET	= 1^5,		!CRM PE DETECT
	PE_DET_ENB	= 1^6,		!PE DETECT ENABLE
	RESET		= 1^7,		!RESET

!WRITE REGISTER 102/103

	DATA35		= 1^0,		!KS10 BUS DATA BIT 35
	DATA34		= 1^1,		!KS10 BUS DATA BIT 34
	DATA33		= 1^2,		!KS10 BUS DATA BIT 33
	DATA32		= 1^3,		!KS10 BUS DATA BIT 32
	DATA31		= 1^4,		!KS10 BUS DATA BIT 31
	DATA30		= 1^5,		!KS10 BUS DATA BIT 30
	DATA29		= 1^6,		!KS10 BUS DATA BIT 29
	DATA28		= 1^7,		!KS10 BUS DATA BIT 28

!WRITE REGISTER 104/105

	DATA27		= 1^0,		!KS10 BUS DATA BIT 27
	DATA26		= 1^1,		!KS10 BUS DATA BIT 26
	DATA25		= 1^2,		!KS10 BUS DATA BIT 25
	DATA24		= 1^3,		!KS10 BUS DATA BIT 24
	DATA23		= 1^4,		!KS10 BUS DATA BIT 23
	DATA22		= 1^5,		!KS10 BUS DATA BIT 22
	DATA21		= 1^6,		!KS10 BUS DATA BIT 21
	DATA20		= 1^7,		!KS10 BUS DATA BIT 20

!WRITE REGISTER 106/107

	DATA19		= 1^0,		!KS10 BUS DATA BIT 19
	DATA18		= 1^1,		!KS10 BUS DATA BIT 18
	DATA17		= 1^2,		!KS10 BUS DATA BIT 17
	DATA16		= 1^3,		!KS10 BUS DATA BIT 16
	DATA15		= 1^4,		!KS10 BUS DATA BIT 15
	DATA14		= 1^5,		!KS10 BUS DATA BIT 14
	DATA13		= 1^6,		!KS10 BUS DATA BIT 13
	DATA12		= 1^7,		!KS10 BUS DATA BIT 12

!WRITE REGISTER 110/111

	DATA11		= 1^0,		!KS10 BUS DATA BIT 11
	DATA10		= 1^1,		!KS10 BUS DATA BIT 10
	DATA9		= 1^2,		!KS10 BUS DATA BIT 9 
	DATA8		= 1^3,		!KS10 BUS DATA BIT 8 
	DATA7		= 1^4,		!KS10 BUS DATA BIT 7 
	DATA6		= 1^5,		!KS10 BUS DATA BIT 6 
	DATA5		= 1^6,		!KS10 BUS DATA BIT 5 
	DATA4		= 1^7,		!KS10 BUS DATA BIT 4 

!WRITE REGISTER 112/113

	DATA3		= 1^0,		!KS10 BUS DATA BIT 3 
	DATA2		= 1^1,		!KS10 BUS DATA BIT 2 
	DATA1		= 1^2,		!KS10 BUS DATA BIT 1 
	DATA0		= 1^3,		!KS10 BUS DATA BIT 0 

!WRITE REGISTER 114/115

	DATA_CYCLE	= 1^0,		!DATA CYCLE
	IO_DATA		= 1^1,		!I/O DATA CYCLE
	COM_ADR		= 1^2,		!COM/ADR CYCLE
	BAD_DATA	= 1^3,		!BAD DATA CYCLE

!WRITE REGISTER 116

	CSL_INT		= 1^0,		!CSL INTERRUPT THE 10

!WRITE REGISTER 204

	CRAM_RESET	= 1^0,		!CRAM RESET
	STK_RESET	= 1^1,		!STACK RESET
	DP_RESET	= 1^2,		!DP RESET
	SS_MODE		= 1^3,		!SINGLE STEP MODE
	CRAM_ADR_LD	= 1^4,		!CRAM ADR LOAD
	CRAM_WRT	= 1^5,		!CRAM WRITE

!WRITE REGISTER 205

	DIAG1		= 1^0,		!DIAG FN BIT 1
	DIAG2		= 1^1,		!DIAG FN BIT 2
	DIAG4		= 1^2,		!DIAG FN BIT 4
	DIAG10		= 1^3,		!DIAG FN BIT 10
	TRAP_ENB	= 1^4,		!TRAP ENABLE
	CLR_INT		= 1^5,		!CLEAR 10 INTERRUPT
	MNT_CLK_ENB	= 1^6,		!MAINT CLK ENABLE
	MAINT_CLK	= 1^7,		!MAINT CLK PULSE

!WRITE REGISTER 206

	CLK_RUN		= 1^0,		!CLOCK RUN
	SINGLE_CLK	= 1^1,		!SINGLE CLOCK

!WRITE REGISTER 210

	CLOSE_LATCH	= 1^0,		!CLOSE LATCHS
	LATCH_DATA	= 1^1,		!LATCH DATA (1)
	CRA_R_CLK	= 1^2,		!CRA R CLK ENB (1)
	CRA_T_CLK	= 1^3,		!CRA T CLK ENB (1)
	XMIT_DATA	= 1^4,		!XMIT DATA (1)
	XMIT_ADR	= 1^5,		!XMIT ADR (1)
	BUS_REQ		= 1^6,		!BUS REQ
	MEM		= 1^7,		!MEM

!WRITE REGISTER 212

	CONTINUE	= 1^0,		!CONTINUE
	EXECUTE		= 1^1,		!EXECUTE
	RUN		= 1^2,		!RUN


!READ REGISTER 0

	RDATA35		= 1^0,		!KS10 BUS DATA BIT 35
	RDATA34		= 1^1,		!KS10 BUS DATA BIT 34
	RDATA33		= 1^2,		!KS10 BUS DATA BIT 33
	RDATA32		= 1^3,		!KS10 BUS DATA BIT 32
	RDATA31		= 1^4,		!KS10 BUS DATA BIT 31
	RDATA30		= 1^5,		!KS10 BUS DATA BIT 30
	RDATA29		= 1^6,		!KS10 BUS DATA BIT 29
	RDATA28		= 1^7,		!KS10 BUS DATA BIT 28

!READ REGISTER 1

	RDATA27		= 1^0,		!KS10 BUS DATA BIT 27
	RDATA26		= 1^1,		!KS10 BUS DATA BIT 26
	RDATA25		= 1^2,		!KS10 BUS DATA BIT 25
	RDATA24		= 1^3,		!KS10 BUS DATA BIT 24
	RDATA23		= 1^4,		!KS10 BUS DATA BIT 23
	RDATA22		= 1^5,		!KS10 BUS DATA BIT 22
	RDATA21		= 1^6,		!KS10 BUS DATA BIT 21
	RDATA20		= 1^7,		!KS10 BUS DATA BIT 20

!READ REGISTER 2

	RDATA19		= 1^0,		!KS10 BUS DATA BIT 19
	RDATA18		= 1^1,		!KS10 BUS DATA BIT 18
	RDATA17		= 1^2,		!KS10 BUS DATA BIT 17
	RDATA16		= 1^3,		!KS10 BUS DATA BIT 16
	RDATA15		= 1^4,		!KS10 BUS DATA BIT 15
	RDATA14		= 1^5,		!KS10 BUS DATA BIT 14
	RDATA13		= 1^6,		!KS10 BUS DATA BIT 13
	RDATA12		= 1^7,		!KS10 BUS DATA BIT 12

!READ REGISTER 3

	RDATA11		= 1^0,		!KS10 BUS DATA BIT 11
	RDATA10		= 1^1,		!KS10 BUS DATA BIT 10
	RDATA9		= 1^2,		!KS10 BUS DATA BIT 9 
	RDATA8		= 1^3,		!KS10 BUS DATA BIT 8 
	RDATA7		= 1^4,		!KS10 BUS DATA BIT 7 
	RDATA6		= 1^5,		!KS10 BUS DATA BIT 6 
	RDATA5		= 1^6,		!KS10 BUS DATA BIT 5 
	RDATA4		= 1^7,		!KS10 BUS DATA BIT 4 

!READ REGISTER 100

	ADPT2_PE	= 1^0,		!UNIBUS ADAPTER 2 PARITY ERR
	CRA_PE		= 1^1,		!CRA PARITY ERR
	DP_PE		= 1^2,		!DP PARITY ERR
	MEM_PE		= 1^3,		!MEM PARITY ERR
	CRAM_PE		= 1^4,		!CRAM PARITY ERR
	ADPT3_PE	= 1^6,		!UNIBUS ADAPTER 3 PARITY ERR
	REC_PE		= 1^7,		!RECEIVED PARITY ERR

!READ REGISTER 101

	MMC_REF_ERR	= 1^0,		!MEM REFRESH ERR
	PI_REQ_7	= 1^1,		!PI REQ 7
	PI_REQ_6	= 1^2,		!PI REQ 6
	PI_REQ_5	= 1^3,		!PI REQ 5
	PI_REQ_4	= 1^4,		!PI REQ 4
	PI_REQ_3	= 1^5,		!PI REQ 3
	PI_REQ_2	= 1^6,		!PI REQ 2
	PI_REQ_1	= 1^7,		!PI REQ 1

!READ REGISTER 102

	RDATA		= 1^0,		!DATA CYCLE
	RIO_DATA	= 1^1,		!I/O DATA CYCLE
	RCOM_ADR	= 1^2,		!COM/ADR CYCLE
	RBAD_DATA	= 1^3,		!BAD DATA CYCLE
	RIO_BUSY	= 1^4,		!I/O BUSY
	RMEM_BUSY	= 1^5,		!MEM BUSY
	RRESET		= 1^6,		!RESET
	RAC_LO		= 1^7,		!AC LO

!READ REGISTER 103

	RDATA3		= 1^0,		!KS10 BUS DATA BIT 3 
	RDATA2		= 1^1,		!KS10 BUS DATA BIT 2 
	RDATA1		= 1^2,		!KS10 BUS DATA BIT 1 
	RDATA0		= 1^3,		!KS10 BUS DATA BIT 0 
	PAR_LEFT	= 1^4,		!PARITY LEFT
	PAR_RIGHT	= 1^5,		!PARITY RIGHT
	ADPT4_PE	= 1^6,		!UNIBUS ADAPTER 4 PARITY ERR
	ADPT1_PE	= 1^7,		!UNIBUS ADAPTER 1 PARITY ERR

!READ REGISTER 300

	CONTINUE_H	= 1^0,		!CONTINUE
	EXECUTE_B	= 1^1,		!EXECUTE
	RUN_1		= 1^2,		!RUN
	HALT_LOOP	= 1^3,		!DPM HALT LOOP
	KLINIK_LEN	= 1^4,		!KLINIK LENGTH (SW)
	KLINIK_BIT	= 1^5,		!KLINIK BIT # (SW)
	CTY_CHAR_LEN	= 1^6,		!CTY CHARACTER LENGTH (SW)
	CTY_BIT		= 1^7,		!CTY BIT # (SW)

!READ REGISTER 301

	DATA_ACK	= 1^0,		!DATA ACK
	BOOT		= 1^1,		!BOOT (SW)
	CONS_ENB	= 1^2,		!CONSOLE ENABLE (SW)
	PE_1		= 1^3,		!PE(1)
	BUSREQ		= 1^4,		!BUS REQUEST
	NEXM		= 1^6,		!NEXM
	TEN_INT		= 1^7,		!10 INTERRUPT

!READ REGISTER 302

	KLINIK_CARR	= 1^0,		!KLINIK CARRIER
	TERM_CARR	= 1^1,		!TERMINAL CARRIER
	REM_DIAG_ENB	= 1^2,		!REMOTE DIAG ENB
	REM_DIAG_PRO	= 1^3,		!REMOTE DIAG PROT

!READ REGISTER 303

	RAM_ERR		= 1^0,		!RAM ERROR
	DP_CLK_ENBL	= 1^1,		!DPE/M CLK ENABLE
	CR_CLK_ENB	= 1^2,		!CRA/M CLK ENABLE
	R_CLK_ENB0	= 1^3;		!R CLK ENB (0) H

! END OF 'REGBIT.R36'