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.TOC	"XBLT"

;HERE FROM EXTEND, ARX CONTAINS AC2
.IF/XADDR

XBLT:	AR_AC1,SR_XBLT(SRC)		;[262] IN CASE OF INTERRUPT
	BR/AR,BRX/ARX,MQ_AR,		;SRC ADDR TO BR, DST TO BRX
		AR_AC0,SKP AD0,J/XBLT3	;GET LENGTH, TEST DIRECTION
=0
XBLT3:	SKP AR NE,MQ_AR,J/XBLT4
	AR_MQ-1,ARX_ARX-1,		;DECR SRC & DST ADDR'S FOR DOWN
		VMA/AD,LOAD AR		;GET FIRST WORD

;HERE IS MAIN LOOP FOR XBLT, DOWNWARDS

XBLTDN:	MQ_AR,AR_MEM,SR_XBLT(DST)	;WAIT FOR SOURCE WORD
	VMA_ARX,STORE,SR_XBLT(SRC)	;STORE IT IN DESTINATION
	MEM_AR,AR_MQ,SKP INTRPT		;WAIT, CHECK FOR INTRPT
=0	BR/AR,BRX/ARX,			;PUT DECREMENTED ADDR'S IN BR,X
		AR_AC0+1,SKP CRY0,J/XBLTD1	;COUNT OFF LENGTH
	BR/AR,BRX/ARX,AR_AC0+1,J/PGFAC0	;CLEANUP AND TAKE INTERRUPT
=0
XBLTD1:	AC0_AR,AR_MQ-1,ARX_ARX-1,	;STORE NEW LENGTH, GET NEXT ADDR
		VMA/AD,LOAD AR,J/XBLTDN	; AND READ SRC WORD
	AC0_AR,AR_ARX,ARX/MQ,		;DONE!  PUT ALL AWAY
		I FETCH
XBLTX:	AC2_AR,AR_ARX,J/STRAC1

;HERE FOR UPWARD BLT, TESTING FOR NON-ZERO LENGTH

=0
XBLT4:	I FETCH,SR_0,J/NOP		;DO NOTHING IF AC =0
	VMA_BR,LOAD AR,			;ELSE START RIGHT IN
		SR_XBLT(DST),J/XBLTU1

;HERE IS MAIN LOOP FOR XBLT, UPWARDS

XBLTUP:	MEM_AR,AR_MQ-1,SKP AD NE	;COUNT EXHAUSTED?
=0	AC0_AR,ARX_BR+1,AR_BRX+1,	;YES.  GET FINAL ADDRESSES
		I FETCH,J/XBLTX		; READY TO STORE
	AC0_AR,MQ_AR,AR_BR+1,ARX_BRX+1,
		VMA/AD,LOAD AR		;GET SOURCE WORD
	BR/AR,BRX/ARX,SR_XBLT(DST)	;MUST BE SAVED PRIOR TO MBWAIT
XBLTU1:	AR_MEM,SKP INTRPT		;WAIT FOR SRC, TEST INTRPT
=0	VMA_ARX,STORE,			;COPY TO DST
		SR_XBLT(SRC),J/XBLTUP	;LOOP
	AR_BR LONG,SR_0,J/XBLTPF	;TAKE INTERRUPT

.ENDIF/XADDR

.TOC	"BLT"
; ENTER WITH 0,E IN AR

;IN THE LOOP, ARX CONTAINS THE CURRENT DESTINATION ADDRESS,
; BRX CONTAINS THE TERMINAL ADDRESS, AND BR CONTAINS THE DIFFERENCE
; BETWEEN THE SOURCE AND DESTINATION ADDRESSES.

;UNLIKE EARLIER -10 PROCESSORS, THIS CODE CHECKS FOR THE CASE IN WHICH
; THE DESTINATION ADDRESS IN RH(AC) IS GREATER THAN E, AND RATHER THAN
; STOPPING AFTER ONE WORD, COPIES DOWNWARD (EFFECTIVELY DECREMENTING
; AC BY 1,,1 ON EACH STEP, RATHER THAN INCREMENTING).

;THIS CODE ALSO PROVIDES A GUARANTEED RESULT IN AC ON COMPLETION OF
; THE TRANSFER (EXCEPT IN THE CASE AC IS PART OF BUT NOT THE LAST WORD
; OF THE DESTINATION BLOCK).  WHEN AC IS NOT PART OF THE DESTINATION
; BLOCK, IT IS LEFT CONTAINING THE ADDRESSES OF THE FIRST WORD FOLLOWING
; THE SOURCE BLOCK (IN THE LH), AND THE FIRST WORD FOLLOWING THE DEST-
; INATION BLOCK (IN THE RH).  IF AC IS THE LAST WORD OF THE DESTINATION
; BLOCK, IT WILL BE A COPY OF THE LAST WORD OF THE SOURCE BLOCK.

;IN ADDITION, A SPECIAL-CASE CHECK IS MADE FOR THE CASE IN WHICH EACH
; WORD STORED IS USED AS THE SOURCE OF THE NEXT TRANSFER.  IN THIS CASE,
; ONLY ONE READ NEED BE PERFORMED, AND THAT DATA MAY BE STORED FOR EACH
; TRANSFER.  THUS THE COMMON USE OF BLT TO CLEAR CORE IS SPEEDED UP.

;BLT:	ARX_AR,MQ_AR,ARR_AC0,ARL_ARL	;END TO ARX & MQ, DEST TO AR
BLT1:	BR/AR,ARX_AR,BRX/ARX,		;DST TO BR & ARX, END TO BRX
		AR_AC0			;SRC TO ARL
.IFNOT/BLT.PXCT
	ARR_ARL,ARL_BRL			;SRC TO ARR (SAME SECTION AS E)
	AR_AR-BR			;SRC-DST TO ARR
.IF/BLT.PXCT
	ARR_ARL,ARL_BRL.M,SKP P!S XCT	;SRC TO ARR (SAME SECTION AS E)
=0	AR_AR-BR,J/BLT2			;SRC-DST TO ARR
	AR_AR-BR,J/BLTPXCT		;TREAT PXCT OF BLT SPECIAL
.ENDIF/BLT.PXCT
.IF/BACK.BLT
	BR/AR,SKP ARX LE BRX		;SRC-DST TO BR. UP OR DOWN?
=00	AR_MQ-1,CALL,J/BLTAC		;DOWN, READY WITH E-1
	AR_MQ+1,CALL,J/BLTAC		;UP, PUT E+1 IN AR FOR AC
DOWN:	LOAD VMA(EA)_ARX+BR,J/DN1	;DOWN, START THE LOOP
.IFNOT/BACK.BLT
=0*
BLT2:	BR/AR,AR_MQ+1,CALL,J/BLTAC	;SRC-DST TO BR, E+1 IN AR
.ENDIF/BACK.BLT
	SKP BR EQ -1,J/UP		;IS THIS CORE CLEARING CASE?


;HERE TO SETUP FINAL AC

BLTAC:	ARL_ARR,AR_AR+BR		;FINAL DEST TO LH, SRC TO RH
	AR_AR SWAP,SR_BLT(SRC)
ACSETU:	AC0_AR,RETURN2			;[334] Used below as well

;HERE FOR UPWARD BLT (AC RH .LE. E)
=0
UP:	LOAD VMA(EA)_ARX+BR,J/UP1	;NOT CLEAR CORE
	SKP P!S XCT,LOAD VMA(EA)_ARX+BR	;DO NOT OPTIMIZE UNDER EXT ADDR

;USE EVEN LOC'NS OF THIS BLOCK OF 4 IN SPECIAL "CLEAR CORE" CASE

=00	AR_MEM,CALL,SR_BLT(DST),J/UP2	;GET THE WORD TO STORE IN ALL
UP1:	AR_MEM,CALL,SR_BLT(DST),J/UP2	;GET SOURCE WORD
	CALL,SR_BLT(DST),J/UP2		;HERE TO STORE SAME SRC AGAIN
	LOAD VMA(EA)_ARX+BR,J/UP1	;HERE TO GET NEXT SRC

UP2:	STORE VMA(EA)_ARX,SKP INTRPT	;OK, GET DST ADDRESS
=0
UP3:	SKP ARX LT BRX,J/UP4		;CHECK FOR LAST TRANSFER
	MEM_AR,J/BLTPF			;FINISH THIS, GO SERVE INTRPT
=0
UP4:	FIN STORE,I FETCH,J/NOP		;THAT'S ALL, FOLKS
	MEM_AR,ARX_ARX+1,		;STORE DST,
		SR_BLT(SRC),RETURN2	; CONTINUE

;BLT CONTINUED - HERE FOR DOWNWARD BLT (AC RH .GT. E)
.IF/BACK.BLT

DN1:	AR_MEM,SR_BLT(DST)		;WAIT FOR SOURCE DATA
	VMA_ARX,STORE,SKP INTRPT	;OK, START DST REF
=0	SKP ARX LE BRX,J/DN3		;CHECK FOR END CONDITION
	MEM_AR,J/BLTPF			;FINISH STORE, TAKE INTRPT
=0
DN3:	MEM_AR,ARX_ARX-1,		;NOT END, LOOP
		SR_BLT(SRC),J/DOWN
	FIN STORE,I FETCH,J/NOP		;END
.ENDIF/BACK.BLT

.TOC "EXTENDED ADDRESSING CODE FOR PXCT OF BLT"

;THIS MUST BE SEPERATE CODE TO MAKE PXCT WORK NOTE THAT PXCT ONLY CAN
;BE USED IN SECTION 0 AND IN FACT WILL EVENTUALLY BE REMOVED FROM THERE
;HOPEFULLY THIS CODE CAN GO AWAY THE SPEC IS THAT PXCT OF BLT IS NOT DEFINED
;AND WILL NOT BE USED ON EXTENDED ADDRESSING MACHINES.

.IF/BLT.PXCT
=0*
BLTPXCT:BR/AR,AR_MQ+1,CALL,J/BLTPX1	;SRC-DST TO BR, E+1 IN AR
UPPX:	VMA_ARX+BR,LOAD AR,J/UP1PX	;NOT CLEAR CORE
					;CORE CLEARING NOT LEGAL


;HERE TO SETUP FINAL AC

BLTPX1:	ARL_ARR,AR_AR+BR		;FINAL DEST TO LH, SRC TO RH
	AR_AR SWAP,SR_BLT(PXCT SRC),
		J/ACSETU		;[334] Use common return above

;USE EVEN LOC'NS OF THIS BLOCK OF 4 IN SPECIAL "CLEAR CORE" CASE

=00
=01
UP1PX:	AR_MEM,CALL,SR_BLT(PXCT DST),J/UP2PX	;GET SOURCE WORD
	CALL,SR_BLT(PXCT DST),J/UP2PX	;HERE TO STORE SAME SRC AGAIN
	VMA_ARX+BR,LOAD AR,J/UP1PX	;HERE TO GET NEXT SRC

UP2PX:	VMA_ARX,STORE,SKP INTRPT	;OK, GET DST ADDRESS
=0
UP3PX:	SKP ARX LT BRX,J/UP4PX		;CHECK FOR LAST TRANSFER
	MEM_AR,J/BLTPF			;FINISH THIS, GO SERVE INTRPT
=0
UP4PX:	FIN STORE,I FETCH,J/NOP		;THAT'S ALL, FOLKS
	MEM_AR,ARX_ARX+1,		;STORE DST,
		SR_BLT(PXCT SRC),RETURN2	; CONTINUE
.ENDIF/BLT.PXCT