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5-1-documentation/tgha.doc
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TGHA.DOC -- REVISION 2(6)
OCTOBER 1981
COPYRIGHT (C) 1982 BY
DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASS.
THIS SOFTWARE IS FURNISHED UNDER A LICENSE FOR USE ONLY ON A
SINGLE COMPUTER SYSTEM AND MAY BE COPIED ONLY WITH THE INCLUSION
OF THE ABOVE COPYRIGHT NOTICE. THIS SOFTWARE, OR ANY OTHER
COPIES THEREOF, MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE
TO ANY OTHER PERSON EXCEPT FOR USE ON SUCH SYSTEM AND TO ONE WHO
AGREES TO THESE LICENSE TERMS. TITLE TO AND OWNERSHIP OF THE
SOFTWARE SHALL AT ALL TIMES REMAIN IN DIGITAL EQUIPMENT
CORPORATION.
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT
NOTICE AND SHOULD NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL
EQUIPMENT CORPORATION.
DIGITAL EQUIPMENT CORPORATION ASSUMES NO RESPONSIBILITY FOR THE
USE OR RELIABILITY OF ITS SOFTWARE IN EQUIPMENT WHICH IS NOT
SUPPLIED BY DIGITAL EQUIPMENT CORPORATION.
1.0 SUMMARY
TGHA - THE GREAT HEURISTIC ALGORITHM
TGHA IS THE PROGRAM THAT HAS THE RESPONSIBILITY OF KEEPING THE
MF20 MEMORIES IN A VIABLE CONDITION VIA MF20 MAINTAINENCE FEATURES.
1.1 TGHA SOURCES WILL NOT BE AVAILABLE TO CUSTOMERS.
1.2 NOTE THAT THIS DOCUMENT APPLIES TO BOTH TOPS10 AND TOPS20 UNLESS
OTHERWISE SPECIFIED.
2.0 EXTERNAL CHANGES
TGHA PHASE 2 HAS SOME ADDITION FEATURES.
2.1 TGHA PHASE 2 WILL NOT INTERRUPT THE SYSTEM ON EVERY CORRECTABLE
ERROR FROM AN MF20. TGHA PHASE 2 WILL INSTEAD INTERRUPT THE SYSTEM ONLY
WHEN PUTTING OR CHANGING THE USE OF A SPARE BIT.
2.2 TGHA PHASE 2 WILL MAKE SYSERR ENTRIES INDICATING NEW HARD FAILURES.
ALSO, SERIOUS ERRORS WILL BE INDICATED ON THE CTY.
2.3 THE KNOWN ERROR LIST IS NOW SUPPORTED IN THE HISTORY LIST FILE:
TOPS10 - HISTRY.LST
TOPS20 - HISTORY.LST
2.4 IF THE MEMORY BOOT PORTION OF KLI DOES NOT CONFIGURE A BLOCK OF MF20
MEMORY DUE TO A TRIPLE BIT ERROR, TGHA PHASE 2 WILL INDICATE WHAT MEMORY
AND HOW MUCH MEMORY WAS NOT CONFIGURED. THE MESSAGE WILL APPEAR ON THE
CTY, IN THE TGHA TRACE FILE, AND THE SYSERR FILE.
2.5 IF THERE IS ONLY CORE ON A SYSTEM, TGHA WILL BE RUN BY THE MONITOR,
BUT THE "TGHA IS RUNNING..." MESSAGE WILL NOT APPEAR. IF THE MF20 IS
INSTALLED, BUT NOT ON LINE, THE MESSAGE WILL APPEAR, AND "NO MF20 FOUND
ON THE SYSTEM" WILL BE ENTERED IN THE TRACE FILE.
3.0 KNOWN BUGS AND DEFICIENCIES
3.1 IF THE MEMORY BOOT PORTION OF KLI FINDS A PARITY ERROR, KLI WILL USE
THE SPARE BIT AND CONFIGURE THE BLOCK. TGHA PHASE 2, UPON FINDING THAT
A SPARE BIT WAS SET INTO USE BY KLI, WILL NEVER USE THAT SPARE BIT FOR
ANY OTHER PURPOSE. UPON FINDING SUCH A CONDITION, TGHA PHASE 2 WILL PUT
AN APPROPRIATE MESSAGE IN ON THE CTY, IN THE TRACE FILE, AND IN SYSERR.
3.2 IF A PARITY ERROR EVER OCCURS DURING SWAPPING IN OF A SPARE BIT, THE
SPARE BIT WILL THEN BE FLAGGED AS IF KLI HAD SET THE SPARE BIT INTO USE
(SEE PREVIOUS PARAGRAPH). SIMILAR CTY, TRACE FILE AND SYSERR ENTRIES
WILL BE MADE.
3.3 NOTE: TGHA PHASE 2 WILL NOT SEND THE "TGHA IS RUNNING." MESSAGE ONTO
THE CTY. THE ONLY REGULAR MESSAGE IS
"TGHA 2(3) RUNNING FIRST TIME."
INDICATING THAT TGHA IS RUNNING FOR THE FIRST TIME SINCE MONITOR RELOAD.
3.4 ON TOPS10, VERSION 7.01, THE USE OF THE SPARE BIT IS AFFECTED BY THE
NETWORK. IF THE NETWORK IS UP, THE MONITOR WILL NOT LET TGHA CHANGE THE
CURRENT USE OF THE SPARE BITS. ON A SYSTEM WITH A NETWORK, BUT THE
NETWORK IS NOT UP, THE MONITOR WILL, IN THIS CASE, ALLOW TGHA TO CHANGE
THE CURRENT USE OF THE SPARE BITS.
IN THIS SITUATION, TGHA WILL STILL MAKE KNOWN ERROR ENTRIES IN
THE NORMAL MANNER. CORRECTIVE ACTION WILL CONSIST OF USING THE ICE
(IGNORE CORRECTABLE ERROR) BITS ONLY. THE RESON FOR THIS IS THAT THE
MECHANISM FOR CHANGING THE USE OF THE SPARE BIT WILL PUT ALL FRONT ENDS
INTO SECONDARY PROTOCOL. THE NETWORK INTERFACE ON TOPS10, VERSION
7.01, WILL NOT PROPERLY RECOVER, CRASHING THE NODE. IF THE SYSTEM IS
STANDALONE OR THE NETWORK NODE IS NOT LOADED, CHANGING THE USE OF THE
SPARE BIT WILL NOT AFFECT THE NETWORK, THEREFORE THE MONITOR WILL ALLOW
TGHA TO TAKE NORMAL CORRECTIVE ACTION.
4.0 INSTALLATION INSTRUCTIONS
IF TGHA PHASE 1 HAS BEEN PREVIOUSLY INSTALLED ON THE SYSTEM, REPLACE
TGHA.EXE WITH TGHA.EXE FOR PHASE 2. NOTE THAT TGHA PHASE 2 DATA AND
TRACE FILES NAMES ARE NOW TGHAV2.DAT AND TGHAV2.TRA RESPECTIVELY. THE
OLD FILES TGHA.DAT AND TGHA.TRA ARE NOT USED BY TGHA PHASE 2 AND ARE NO
LONGER OF ANY USE. THEY SHOULD NOT BE RENAMED TO PRESERVE THE DATABASE.
THE DATABASES FOR PHASE 1 AND PHASE 2 ARE NOT COMPATIBLE.
---
4.1 INSTALLATION ON TOPS10
4.1.1 OPR.ATO
FOR TGHA TO RUN PROPERLY ON TOPS10, THE FOLLOWING ENTRY MUST BE MADE
IN OPR.ATO AFTER DAEMON IS STARTED::
:SLOG
:DEF TGHA=
R TGHA
SINCE TGHA MAY MAKES ENTRIES IN THE SYSERR FILE VIA DAEMON, DAEMON MUST
BE RUNNING BEFORE TGHA IS STARTED.
4.1.2 CORE LOCKING
TGHA WILL OCCASIONALLY LOCK ITSELF IN CORE.
5.0 INTERNAL CHANGES
THE MAJOR FEATURES TO BE ADDED IN TGHA PHASE 2 ARE THE KNOWN ERROR
DETERMINATION ALGORITHM AND THE CORRECTIVE ACTION ALGORITHM. SYSERR
ENTRIES ARE NOW SUPPORTED ALSO ALONG WITH ADDITIONAL CTY NOTATIONS.
6.0 SUGGESTIONS AND AN OVERVIEW OF TGHA PHASE 2
TGHA IS RUN:
1) BY THE MONITOR AT INITIAL SYSTEM START UP
2) BY THE MONITOR IN RESPONSE TO MF20 ERRORS
3) BY FIELD SERVICE TO OBTAIN LIST FILES
6.1 TGHA FILE REQUIREMENTS
THE TGHA PHASE 2 FILE SYSTEM FOR BOTH TOPS10 AND TOPS20 INCLUDES
THE FOLLOWING FILES:
FILE PURPOSE CREATION MECHANISM
---- ------- -------------------
TGHA.EXE TGHA EXECUTION FILE MONITOR TAPE
TGHA.HLP TGHA HELP FILE MONITOR TAPE
TGHAV2.DOC TGHA OVERVIEW FILE MONITOR TAPE
TGHAV2.DAT TGHA HISTORY/DATA FILE TGHA.EXE WHEN FIRST RUN
TGHA.TRA TGHA TRACE FILE TGHA.EXE WHEN FIRST RUN
TGHA.BAD A BAD COPY OF TGHAV2.DAT TGHA.EXE WHEN THE DATABASE GETS
CONFUSED
TGHA.EXE MUST RESIDE IN THE AREA:
----
TOPS10: [1,4]
TOPS20: PS:<SYSTEM>
WHEN THE MONITOR FIRST STARTS UP ON A SYSTEM RELOAD, IT LOOKS
FOR TGHA IN THE APPROPRIATE AREA. IF IT IS NOT THERE, TGHA CANNOT BE RUN
BY THE MONITOR. IF TGHA.EXE IS NOT FOUND, THE MONITOR WILL THROW AWAY
THE ERROR DATA THAT MIGHT HAVE BEEN COLLECTED BY TGHA. TGHAV2.DAT AND
TGHAV2.TRA WILL BE CREATED AUTOMAGICALLY BY TGHA WHEN NECESSARY.
TGHAV2.DAT IS NOT LIKE THE SYSERR DATA FILE. TGHAV2.DAT WILL NOT GROW
AS ERRORS ARE INCURRED. TGHA WILL PURGE OLD DATA AS ITS DATABASES FILL
UP. THE ONLY WAY THAT TGHAV2.DAT WILL GROW IS IF NEW HARDWARE IS
BROUGHT ON LINE. IE. A STORAGE MODULE IS SWAPPED OR A NEW CONTROLLER
IS ADDED TO THE SYSTEM. TGHA REQUIRES ALL OF ITS HISTORY DATA THAT IT
HAS COLLECTED OVER TIME TO REMAIN INTACT SO THAT IT CAN MAKE AS CORRECT
DECISIONS ABOUT CORRECTIVE ACTION AS POSSIBLE.
***TGHAV2.DAT SHOULD NOT BE DELETED. IT CONTAINS IMPORTANT HISTORY
INFORMATION.
6.2 INITIAL SYSTEM START UP
AT INITIAL SYSTEM START UP, THE MONITOR RUNS TGHA IN START UP
MODE. IN THIS MODE, TGHA WILL FIRST ENABLE SINGLE BIT ERROR REPORTING
THROUGHOUT MF20 MEMORY. TGHA WILL THEN EITHER BUILD THE HISTORY FILE IF
IT DOES NOT ALREADY EXIST, OR VERIFY THAT IT KNOWS ABOUT ALL OF THE MF20
HARDWARE THAT IS ON LINE. IF THE HISTORY FILE EXISTS AND NEW MF20
HARDWARE APPEARS, TGHA WILL ADD THIS NEW HARDWARE TO ITS HISTORY FILE.
ONCE THE INITIAL START UP INITIALIZATION IS COMPLETE, TGHA THEN LOOKS
FOR ANY MF20 ERRORS THAT HAVE OCCURRED SINCE THE INITIAL SYSTEM START UP.
6.3 MF20 ERRORS
FOR TOPS10, WHEN AN MF20 CORRECTABLE ERROR OCCURS, THE MONITOR WAKES UP
THE SYSTEM TGHA. UPON THE SYSTEM TGHA. FOR TOPS20, WHEN AN MF20
CORRECTABLE ERROR OCCURS, THE MONITOR CALLS TGHA WITH A JOB NUMBER OF 0.
TGHA THEN GETS THE DATA FOR THE MF20 ERROR FROM THE MONITOR. THIS IS
CALLED A CHRONOLOGICAL ERROR. THEY ARE STORED UP IN A LIST IN THE
HISTORY DATABASE. THERE IS A SEPARATE CHRONOLOGICAL ERROR LIST FOR EACH
MODULE.
ONLY WHEN THE CHRONOLOGICAL ERROR LIST IS FULL DOES TGHA GO OFF
AND ATTEMPT TO RESOLVE A KNOWN FROM THIS LIST.
6.4 KNOWN ERROR DETERMINATION
KNOWN ERROR DETERMINATION IS DONE STATISTICALLY USING THE CHI
SQUARED GOODNESS OF FIT FORMULA. STARTING WITH THE FIRST CHRONOLOGICAL
ERROR IN THE STORAGE MODULE, THE FORMULA IS USED TO TEST THE
DISTRIBUTION OF THE OTHER ERRORS IN THE CHRONOLOGICAL ERROR LIST FOR
EACH TYPE OF POSSIBLE HARDWARE ERROR.
FOR INSTANCE, THE FIRST HARDWARE FAILURE CONSIDERED IS A FULL
MUX FAILURE. A TABLE IS BUILT BY SCANNING ALL OF THE OTHER ERRORS IN
THE STORAGE MODULE AND TALLYING ONLY THOSE ERRORS THAT ARE COVERED BY
THE SPECIFIC TYPE OF HARDWARE ERROR BEING CONSIDERED, IN THIS CASE, A
FULL MUX FAILURE. THE TABLE FOR A FULL MUX FAILURE IS DISTRIBUTED BY
BLOCK AND SUBBLOCK NUMBER. THIS TRANSLATES INTO A DISTRIBUTION BY CHIP
SINCE THERE ARE 16 CHIPS INVOLVED IN A FULL MUX FAILURE. IF THE THE
DISTRIBUTION IS EVEN ENOUGH, THE CHI 2'D GOODNESS OF FIT TEST WILL
SUCCEED, AND A KNOWN ERROR IS DECLARED.
THIS CONTINUES UNTIL EITHER THE HARDWARE ERROR TYPE IS FOUND OR
ALL OF THE ERROR TYPES HAVE BEEN TRIED.
THE LAST TYPE OF HARDWARE ERROR CONSIDERED IS A CELL ERROR.
IF THERE ARE MORE THAN A MINIMUM NUMBER OF ERRORS OF THE SAME CELL
(TYPICALLY 5), THEN A CELL ERROR IS DECLARED.
AFTER AN ERROR TYPE HAS BEEN FOUND, ALL OF THE CHRONOLOGICAL
ERRORS THAT ARE INFLUENCED BY THE KNOWN ERROR TYPE ARE ELIMINATED FROM
THE CHRONOLOGICAL ERROR LIST. THIS PROCEDURE CONTINUES FOR EACH
REMAINING ERROR IN THE CHRONOLOGICAL ERROR LIST.
AFTER THE KNOWN ERROR ROUTINE HAS BEEN RUN, THE CORRECTIVE
ACTION ROUTINE IS CALLED.
6.5 CORRECTIVE ACTION
THE GOAL OF THE CORRECTIVE ACTION ROUTINES IS TO DETERMINE THE
OPTIMUM CORRECTIVE ACTION GIVEN THE CURRENT KNOWN ERRORS. THIS IS DONE
ON A PER GROUP BASIS.
FIRST, THE WORST ERROR IN THE GROUP IS FOUND. THIS IS THE ERROR
THAT AFFECT THE MOST AMOUNT OF MEMORY. ONCE THE WORST ERROR HAS BEEN
FOUND, THE APPLICABLE SPARE BITS ARE USED TO COVER IT. IF THERE IS MORE
THAN ONE KNOWN ERROR IN THE GROUP, A SCAN IS DONE TO SET ALL ICE
(INHIBIT CORRECTABLE ERROR REPORTING) BITS WITHIN THE SCOPE OF THE WORST
ERROR. THIS PROCEDURE IS REPEATED UNTIL ALL KNOWN ERRORS FOR THE GROUP
HAVE BEEN ANALYZED.
NOTE: THERE IS ONE EXCEPTION TO THE PREVIOUS PROCEDURE. IF THE MEMORY
BOOT PORTION OF KLI HAS (DURING THE DBE SCAN - DOUBLE BIT ERROR) USED A
SPARE BIT TO HANDLE A DOUBLE BIT ERROR, TGHA WILL NOT CHANGE THE USE OF
THAT SPECIFIC SPARE BIT. IF TGHA WERE TO ATTEMPT TO USE SUCH A SPARE
BIT FOR ANOTHER PURPOSE, THE POSSIBILITY OF PARITY ERRORS RESULTING
WOULD BE TOO GREAT TO RISK.
ALSO, IF A PARITY ERROR OCCURS DURING THE SETTING OF A SPARE
BIT, TGHA WILL SET THE SAME CONSIDERATIONS ON THAT SPARE BIT AS IF KLI
HAD SET IT.
ON THE OCCURRENCE OF THE PREVIOUS CONDITIONS, APPROPRIATE SYSERR
ENTRIES WILL BE MADE.
6.6 PARITY ERRORS
PARITY ERRORS ARE HANDLED LIKE PARITY ERRORS ALWAYS HAVE BEEN.
IE. IF THE MONITOR SUCCESSFULLY CONTINUES AFTER THE PARITY ERROR, IT
WILL ATTEMPT TO TAKE THE PAGE OF MEMORY WITH THE PARITY ERROR OFFLINE.
THE MONITOR THEN RUNS TGHA IF THE PAGE WAS SUCCESSFULLY REMOVED. THE
MONITOR MAY NOT BE ABLE TO TAKE THE PAGE WITH THE PARITY ERROR OFF LINE
IF ,FOR INSTANCE, THE PAGE WAS PART OF THE RESIDENT MONITOR. TGHA WILL
ENTER PARITY ERRORS IN ITS TRACE FILE, NOT THE HISTORY FILE DATABASE.
TGHA WILL MAKE AN ENTRY IN THE TRACE FILE AND SYSERR INDICATING PHYSICAL
ADDRESS, BLOCK OF MEMORY, AND THE ORIENTATION OF THE 4 STORAGE MODULES
CONTAINING THE ERROR.
6.7 MAKING LIST FILES
************************************************************************
NOTE:
IN ORDER TO RUN TGHA MANUALLY, THE USER MUST HAVE THE MINIMUM OF
MAINTAINENCE CAPABILITIES AND BE ENABLED. THIS IS REQUIRED BECAUSE TGHA
LOOKS AT THE MF20 MEMORY TO DETERMINE THE CURRENT CONFIGURATION.
************************************************************************
TGHA CAN ALSO BE RUN BY FIELD SERVICE PERSONNEL. IN THIS MODE,
ON TOPS10, TGHA KNOWS THAT IT IS NOT THE SYSTEM TGHA. ON TOPS20 TGHA
KNOWS THAT IT IS NOT RUN BY A JOB NUMBER OF 0. THEREFORE, TGHA DOES NOT
AUTOMATICALLY LOOK FOR MF20 ERRORS.
TGHA WILL RESPOND WITH A PROMPT OF:
TGHA>
IF "HELP"<CR> IS TYPED, THE FOLLOWING TEXT WILL BE PRINTED
TGHA HELP - COMMAND PURPOSE
EXIT EXIT FROM TGHA.
HELP TYPE THIS TEXT.
HISTORY DUMP HISTORY FILE.
TRACE DUMP TRACE FILE.
TGHA>
THE HISTORY AND TRACE DUMP FILES WILL BE CREATED IN THE AREA
FROM WHICH TGHA HAS BEEN RUN. THEY WILL BE HISTRY.LST FOR TOPS10 AND
HISTORY.LST FOR TOPS20 AND TRACE.LST RESPECTIVELY. THE HISTORY AND
TRACE DUMP FILES WILL BE CREATED IN THE AREA FROM WHICH TGHA HAS BEEN
RUN.
THESE FILES ARE LISTABLE VERSIONS OF THE TGHA DATABASE AND THE
TRACE FILE. ALTHOUGH TGHAV2.TRA MAY LOOK READABLE, REMEMBER THAT IT IS
THE EQUIVALENT OF A RING BUFFER. IE. THE OLDEST DATA IS OVER WRITTEN
WHEN THE FILE BECOMES LARGE ENOUGH. THIS PREVENTS THE TRACE FILE FROM
BECOMING USELESSLY LARGE. TRACE.LST IS IN CHRONOLOGICAL ORDER, THE
OLDEST ENTRIES FIRST.
WHEN TGHA IS RUN BY FIELD SERVICE, THE ONLY FUNCTIONS AVAILABLE
ARE THE DUMPING OF THE LIST FILES. NO CHANGES IN THE MEMORY
CONFIGURATION OR THE USE OF THE SPARE BITS CAN BE DONE BY TGHA IN USER
MODE.
6.8 HISTORY FILE
THE HISTORY FILE IS MADE UP OF 3 DIFFERENT TYPES OF PAGES. THEY
ARE THE DIRECTORY PAGE, GROUP PAGES, AND STORAGE MODULE PAGES. THE
SEQUENCE STARTS OUT WITH ONE DIRECTORY PAGE. THIS PAGE CONTAINS
CONFIGURATION INFORMATION ABOUT ALL OF THE MF20'S ON THE SYSTEM. THE
NEXT PAGE IS A GROUP PAGE FOLLOWED BY FOUR STORAGE MODULE PAGES. THE
PATTERN OF A GROUP AND FOUR SUCCEEDING STORAGE MODULE PAGES IS REPEATED
FOR EACH GROUP CURRENTLY ON LINE IN MF20'S. A STORAGE MODULE PAGE FOR
EACH STORAGE MODULE THAT HAS GONE AWAY IS THEN LISTED.
6.8.1 DIRECTORY PAGE
THE FIRST PAGE OF THE HISTORY FILE CONTAINS THE CURRENT
CONFIGURATION OF THE MF20 MEMORY, INCLUDING THE LOCATION OF EACH STORAGE
MODULE BY SERIAL NUMBER. NOTE THAT THE SERIAL NUMBER IN THE HISTORY
FILE IS IN THE SAME FORMAT AS THE STICKER ON THE STORAGE MODULE ITSELF.
THE LOCATION OF THE STORAGE MODULES IN MF20 MEMORY IS DOCUMENTED
IN THE HISTORY LIST FILE FOR ARCHIVAL AND FIELD SERVICE REASONS. THE
ERRORS LOGGED IN THE HISTORY FILE ARE DEPENDENT UPON THE ORIENTATION OF
THE STORAGE MODULES. IF THEY ARE MOVED, THE ERROR CORRECTIONS IN THE
MF20 MAY HAVE DIFFERENT CHARACTERISTICS. IF FIELD SERVICE WISHES TO
REPLACE A STORAGE MODULE, THE EXACT LOCATION BY SERIAL NUMBER IS
THEREFORE DOCUMENTED.
6.8.2 GROUP PAGE
THE GROUP PAGE CONTAINS INFORMATION SPECIFIC TO THE CONFIGURATION OF THE
GROUP. THE LAST TIME THE GROUP WAS USED IN THIS CONFIGURATION MAY BE
USEFUL IF GROUPS OF STORAGE MODULES ARE REMOVED AND PUT BACK INTO THE
MEMORY LATER. THE TIME OF THE LAST CHANGE TO THE GROUP IS USEFUL WHEN
DETERMINING WHERE THE MOST RECENT ERRORS HAVE OCCURRED IN THE MF20.
LET IT BE NOTED HERE THAT THE CHRONOLOGICAL LIST OF ERRORS IN
THE HISTORY FILE AND THE ENTRIES IN THE TRACE FILE ARE TAGGED WITH THE
DATE AND TIME. THIS IS REQUIRED WHEN CORRELATING CORRECTIVE ACTION WITH
MF20.
THE GROUP PAGE ALSO CONTAINS A MAP OF THE CURRENT STATE OF THE BIT
SUBSTITUTION RAM. THE BIT SUBSTITUTION RAM IS USED TO DIRECT BIT
REPLACEMENT WITH THE SPARE BIT RAMS.
THE VALUE OF THE SPARE BIT RAM CONTAINS 4 FIELDS THAT HAVE THE FOLLOWING
MEANING:
FIELD BITS MEANING
400 EITHER KLI USED THIS SPARE BIT TO COVER A PARITY
ERROR OR A PARITY OCCURRED DURING A BIT SWAP.
374 THE OCTAL VALUE OF THE BIT BEING REPLACED *
2 SET - CORRECTABLE ERROR REPORTING IS DISABLED
CLEARED - CORRECTABLE ERROR REPORTING IS ENABLED
1 BIT SUB RAM VALUE PARITY BIT
* TO FIND THE VALUE OF THE BIT BEING REPLACED, THIS FIELD MUST
BE SHIFTED TO THE RIGHT BY 2 PLACES, AND THE DECIMAL
EQUIVALENT VALUE OF THE OCTAL DIGITS IS THE WORD BIT BEING
REPLACED.
BIT SUBSTITUTION RAM EXAMPLES:
-----------------------------
VALUE MEANING
256 - THE SPARE BIT IS BEING REPLACED IE NOT USED.
THE SPARE BIT IS IN DECIMAL BIT POSITION 43
- CORRECTABLE ERROR REPORTING IS DISABLED FOR
THIS BIT SUB RAM ADDRESS
255 - THE SPARE BIT IS NOT IN USE (SAME AS PREVIOUS EXAMPLE)
- CORRECTABLE ERROR REPORTING IS ENABLED
652 - THE 400 BIT ON INDICATES THAT THIS USE OF
THIS SPARE BIT PREVENTS A PARITY ERROR
FROM OCCURRING. TGHA WILL NOT CHANGE THIS
VALUE. THE BITSUB RAM DATA REQUIRES ODD
PARITY. THE 400 BIT IS IN THE TGHA DATABASE
ONLY, AND IS NOT USED IN THE ACTUAL BITSWAP
PROCESS.
- BIT 42 (THE PARITY BIT - REFER TO THE MF20.FMT
SECTION) OF THE MF20 DATA PATH IS BEING
SWAPPED OUT.
THE ACTUAL SPARE BIT ADDRESS IN SBUS DIAG FUNCTION 7 IS 7 BITS
WIDE. THE ADDRESS IN THE GROUP PAGE ACCOUNTS FOR ONLY THE LOWER 5 BITS.
THE HIGH ORDER 2 BITS IS THE GROUP NUMBER WITHIN THE CONTROLLER. THE
GROUP FIELD IS DETERMINED FROM THE GROUP POSITION IN THE MF20
CONTROLLER, AND NOT THE GROUP DATABASE. THEREFORE THE GROUP PORTION OF
THE FIELD IS NOT, AND INDEED CANNOT BE KEPT WITHIN THE SPARE BIT RAM
ADDRESS TABLE. THIS PORTION OF THE SBUS DIAG FUNCTION IS FILLED IN AT
EXECUTION TIME.
6.8.3 STORAGE MODULE PAGE
A STORAGE MODULE PAGE CONTAINS INFORMATION RELATING SPECIFICLY TO THE
STORAGE MODULE. THE SERIAL NUMBER APPEARS IN THE SAME FORMAT AS THE
STICKER ON THE MODULE ITSELF. THIS IS CRITICAL FOR FIELD RETURNS, WHICH
REQUIRE THAT THIS PAGE BE ATTACHED TO THE STORAGE MODULE IF IT IS TO BE
RETURNED TO THE FACTORY FOR REPAIRS. THE LAST TIME THE MODULE WAS USED
CAN BE USEFUL IN TRACKING MODULE SWAPS MADE IN THE MF20 AND FIELD
RETURNS.
THE KNOWN ERROR LIST CONTAINS THE ERROR INFORMATION RELATED TO
THE KNOWN ERRORS RESOLVED FROM CHRONOLOGICAL ERRORS BY TGHA. MOST OF
THE INFORMATION IN EACH ENTRY IS USED BY TGHA TO DETERMINE OVERLAP OF
ERRORS. THIS OVERLAP IS IMPORTANT WHEN CONSIDERING THE OPTIMUM USE OF
THE SPARE BITS.
THE STORAGE MODULE CHIP LOCATION IS INCLUDED TO FACILITATE
MODULE REPAIR.
THE TIME OF RESOLUTION OF THE ERROR MAY GIVE AN INDICATION OF
THE RATE OF DETERIORATION OF FAILURE OF THE MODULE.
THE CURRENT CHRONOLOGICAL ERROR LIST FOR THE STORAGE MODULE WILL
INCLUDE ANY ERRORS THAT HAVE NOT BEEN RESOLVED INTO KNOWN ERRORS YET.
THERE MAY BE INCLUDED IN THIS LIST, ANY SOFT ERRORS THAT HAVE OCCURRED.
THESE SOFT ERRORS WILL BE REMOVED FROM THE LIST SOMETIME AFTER A MINIMUM
DEFAULT (ABOUT 1 WEEK).
6.8.4 UNUSED STORAGE MODULES
ANY STORAGE MODULES THAT ARE IN THE TGHA HISTORY FILE, YET ARE
NOT PRESENTLY IN USE THEN FOLLOW IN A SIMILAR MANNER. THE INCLUSION OF
THE UNUSED STORAGE MODULES IN THE HISTORY FILE IS REQUIRED FOR THE CASE
WHEN FIELD SERVICE HAS REPLACED A STORAGE MODULE, RELOADED THE SYSTEM,
AND WANTS A COPY OF THE HISTORY FILE FOR THAT STORAGE MODULE SO THAT THE
ERROR DATA CAN BE INCLUDED WITH THE MODULE WHEN THE MODULE IS RETURNED
FOR REPAIRS.
SINCE THESE STORAGE MODULES ARE NO LONGER PART OF ANY CONFIGURED
GROUP, NO GROUP INFORMATION IS GIVEN.
6.9 TRACE FILE
THE TRACE FILE CONTAINS DATED ENTRIES INDICATING WHAT CORRECTIVE
ACTION HAS BEEN TAKEN BY TGHA. IF THE TGHA SOFTWARE RUNS INTO CONFUSION
OR A DATABASE GETS FULL, ENTRIES INTO THE TRACE FILE WILL ALSO REFLECT
THE DIFFICULTY. SERIOUS MF20 HARDWARE ERRORS WILL ALSO BE ENTERED IN
THE TRACE FILE.
AN EXPLANATION OF THE VARIOUS TYPES OF ENTRIES IN THE TRACE FILE FOLLOWS.
6.9.1 THIS ENTRY INDICATES THAT A SPARE BIT IS GOING TO BE SWAPPED AS
CORRECTIVE ACTION FOR AN ERROR.
11-Oct-78 15:50:12 - IN CONTROLLER 10, GROUP 0, VECTOR 3,THE SPARE BIT IS GOING TO BE CHANGED TO 124 (OCTAL).
ONCE THE SPARE BIT SWAP HAS COMPLETED, THE RESULTS OF THE BITSWAP ARE
INDICATED.
11-Oct-78 15:50:12 - BIT SUBSTITUTION - EVERYTHING COMPLETED NORMALLY
6.9.2 WHEN CORRECTABLE ERROR REPORTING IS DISABLED FOR A SPARE BIT
SUBSTITUTION RAM ADDRESS, THE FOLLOWING ENTRY IS MADE:
11-Oct-78 15:50:13 - IN CONTROLLER 10, GROUP 0, VECTOR 3, THE ICE BIT IS GOING TO BE SET.
6.9.3 A PARITY ERROR IS LOGGED IN THE TRACE FILE AS FOLLOWS:
**********
11-OCT-78 19:20:02
* PARITY ERROR AT ADDRESS 1001475, BLOCK 0
* STORAGE MODULE SERIAL NUMBERS BY FIELD: 0 = 7460209 1 = 7460108 2 = 7460117 3 = 7460200
**********
6.9.4 A SERIOUS MF20 HARDWARE FAILURE IS INDICATED AS FOLLOWS:
************************************************************************
*11-OCT-78 19:20:02
* TGHA HAS TEMPORARILY CORRECTED A SERIOUS MOS MEMORY FAILURE.
*** CALL FIELD SERVICE TO REPORT THIS CONDITION ***
************************************************************************
THIS MESSAGE ALSO APPEARS ON THE CTY. ALTHOUGH THE ERROR HAS
BEEN CORRECTED USING THE SPARE BITS, THE PROBABILITY OF A PARITY ERROR
DUE TO FURTHER HARDWARE DEGRADATION HAS RISEN TO AN UNCOMFORTABLE STATE.
THE MF20 DIAGNOSTICS SHOULD BE RUN AND THE OFFENDING STORAGE MODULE
REPLACED.
6.9.5 IF THE MEMORY BOOT PORTION OF KLI USES A SPARE BIT TO PREVENT A
PARITY ERROR, THE FOLLOWING ENTRY WILL BE MADE IN THE TRACE FILE:
*****
5-AUG-79 13:20:29
THE MEMORY BOOT IN KLI HAS USED THE SPARE BIT TO PREVENT A PARITY ERROR.
THIS CONDITION SHOULD BE CORRECTED AS SOON AS POSSIBLE.
CONTROLLER GROUP BLOCK WORD (BITS 33-35)
10 0 1 5
*****
6.9.6 IF KLI HAS NOT CONFIGURED A BLOCK OF MF20 MEMORY BECAUSE OF AN
ERROR THAT CANNOT BE REPAIRED USING THE SPARE BIT, THE BLOCK WILL NOT BE
CONFIGURED. THIS MESSAGE ALSO APPEARS ON THE CTY. AN ENTRY WILL BE
MADE IN THE TRACE FILE AS FOLLOWS:
************************************************************************
*5-AUG-79 13:40:51
* THE FOLLOWING BLOCKS ARE MARKED AS BAD
* AND ARE NOT ON LINE:
* CONTROLLER GROUP BLOCK
* 10 1 3
* 10 2 1
* THIS CONSISTS OF 128K OF MEMORY THAT IS OFF LINE.
*** CALL FIELD SERVICE TO REPORT THIS CONDITION ***
************************************************************************
6.9.7 IF TGHA FINDS THAT THERE IS NO DATABASE AND THAT AN MF20
CONTROLLER WAS LAST INITIALIZED BY TGHA, TGHA WILL OUTPUT THE FOLLOWING
MESSAGE:
*****
15-AUG-1979 15:10:20
* MF20 CONTROLLER 10 WAS LAST INITIALIZED BY TGHA AND
* TGHA HAS LOST ITS DATABASE. REFER TO TRACE OR SYSERR ENTRY
* DOCUMENTATION IN TGHA.DOC FOR FURTHER DETAILS AND RECOVERY INSTRUCTIONS.
*****
IN THIS SITUATION, TGHA CANNOT DETERMINE WHETHER ANY SPARE BITS
IN USE WERE SET BY THE MEMORY BOOT IN KLI OR TGHA. THIS INFORMATION WAS
STORED IN THE TGHA DATABASE, WHICH WENT AWAY FOR SOME REASON. TGHA MUST
THEREFORE ASSUME THAT ALL SPARE BITS IN USE WERE SET BY KLI TO PREVENT
PARITY ERRORS. THIS MEANS THAT THESE SPARE BITS WILL NOT BE AVAILABLE
FOR CORRECTION OF FURTHER HARDWARE FAILURES IN THE MF20 MEMORY.THIS IS
NOT AN IDEAL SITUATION FOR TGHA TO BE IN, AND WILL NOT RECTIFY ITS SELF
AUTOMATICALLY.
ALTHOUGH THIS SITUATION IS NOT IMMEDIATELY CRITICAL, IT DEGRADES
THE PERFORMANCE OF TGHA. THE RECOVERY PROCEDURE CAN BE DEFERRED TO A
CONVENIENT TIME, LIKE A FIELD SERVICE PM OR A SCHEDULED SYSTEM RELOAD.
***** RECOVERY PROCEDURE *****
(1) DELETE TGHAV2.DAT FORM PS:<SYSTEM>
(2) BRING THE SYSTEM DOWN
(3) RECONFIGURE THE MEMORY SYSTEM BY USING THE 'FORCE'
OPTION IN THE MEMORY CONFIGURATION PORTION OF KLI.
(4) REBOOT THE SYSTEM
THIS IS THE -ONLY- TIME THAT THE TGHA DATABASE FILE (TGHAV2.DAT)
SHOULD BE EXPLICITELY DELETED. ALTHOUGH THIS DESTROYS ALL OF THE KNOWN
ERROR HISTORY, THE KNOWN ERRORS WILL BE RESOLVED BY TGHA IN THE SAME
MANNER AS BEFORE.
THE PROBABILITY OF THIS SITUATION ARISING IS VERY LOW. THIS
DRASTIC ACTION IS EXPLAINED ONLY TO COVER THIS SITUATION.
6.9.8 THE SOFTWARE STATE OF THE MEMORY INDICATES WHETHER KLI OR TGHA WAS
THE LAST PROGRAM TO MAKE ANY CHANGES IN THE BIT SUB RAM. ALTHOUGH THE
SOFTWARE BITS IN SBUS FUNCTION WERE DESIGNED FOR THIS PURPOSE, CONFLICTS
MADE THEM IMPRACTICAL. THE INFORMATION IS FLAGGED IN A WORD IN THE
BITSUB RAM INSTEAD OF USING THE SOFTWARE STATE BITS. IF, WHEN TGHA GOES
TO CHECK THE STATE OF THE SOFTWARE STATE WORD IN THE BITSUB RAM, TGHA
FINDS THAT THE DATA IS NOT OF THE FORMAT THAT EITHER KLI OR TGHA USES,
THE FOLLOWING MESSAGE WILL BE PUT OUT:
*****
17-AUG-1979 13:02:59
IN CONTROLLER 10 THE BITSUB RAM STATE WORD WAS GARBAGE.
ASSUMING A DBE SCAN WAS DONE LAST. SEE TGHA.DOC FOR FURTHER DETAILS.
*****
THIS IS A VERY STRANGE STATE SINCE THE SPARE BIT SUB RAM ADDRESS
USED FOR THE SOFTWARE STATE WORD IS NOT IN THE ADDRESS SPACE USED FOR
SWAPPING OF MEMORY BITS. IT IS SUGGESTED THAT THE MF20 DIAGNOSTICS BE
RUN AT THE NEXT CONVENIENT TIME.
6.10 SYSERR
SYSERR ENTRIES ARE MADE BY TGHA. THEY HAVE THE FOLLOWING FORMAT:
6.10.1 THIS ERROR IS USED TO INDICATE A NEW KNOWN ERROR:
A NEW MF20 KNOWN ERROR HAS BEEN DECLARED. DATA:
STORAGE MODULE SERIAL NUMBER: 838009
BLOCK: 1, SUBBLOCK: 0, BIT IN FIELD (10): 11, ROW: 71, COLUMN: 24, E NUMBER 192, ERROR TYPE: CHIP
6.10.2 A SERIOUS MF20 HARDWARE FAILURE IS INDICATED AS FOLLOWS:
************************************************************************
*11-OCT-78 19:20:02
* TGHA HAS TEMPORARILY CORRECTED A SERIOUS MOS MEMORY FAILURE.
*** CALL FIELD SERVICE TO REPORT THIS CONDITION ***
************************************************************************
ALTHOUGH THE ERROR HAS BEEN CORRECTED USING THE SPARE BITS,
THE PROBABILITY OF A PARITY ERROR DUE TO FURTHER HARDWARE DEGRADATION
HAS RISEN TO AN UNCOMFORTABLE STATE. THE MF20 DIAGNOSTICS SHOULD BE
RUN AND THE OFFENDING STORAGE MODULE REPLACED.
6.10.3 IF THE MEMORY BOOT PORTION OF KLI USES A SPARE BIT TO PREVENT
A PARITY ERROR, THE FOLLOWING ENTRY WILL BE MADE IN SYSERR:
*****
5-AUG-79 13:20:29
THE MEMORY BOOT IN KLI HAS USED THE SPARE BIT TO PREVENT A PARITY ERROR.
THIS CONDITION SHOULD BE CORRECTED AS SOON AS POSSIBLE.
CONTROLLER GROUP BLOCK WORD (BITS 33-35)
10 0 1 5
*****
6.10.4 IF KLI HAS NOT CONFIGURED A BLOCK OF MF20 MEMORY BECAUSE OF AN
ERROR THAT CANNOT BE REPAIRED USING THE SPARE BIT, THE BLOCK WILL NOT BE
CONFIGURED. AN ENTRY WILL BE MADE IN SYSERR FILE AS FOLLOWS:
************************************************************************
*5-AUG-79 13:40:51
* THE FOLLOWING BLOCKS ARE MARKED AS BAD
* AND ARE NOT ON LINE:
* CONTROLLER GROUP BLOCK
* 10 1 3
* 10 2 1
* THIS CONSISTS OF 128K OF MEMORY THAT IS OFF LINE.
*** CALL FIELD SERVICE TO REPORT THIS CONDITION ***
************************************************************************
6.10.5 IF TGHA FINDS THAT THERE IS NO DATABASE AND THAT AN MF20
CONTROLLER WAS LAST INITIALIZED BY TGHA, TGHA WILL OUTPUT THE FOLLOWING
MESSAGE:
*****
15-AUG-1979 15:10:20
* MF20 CONTROLLER 10 WAS LAST INITIALIZED BY TGHA AND
* TGHA HAS LOST ITS DATABASE. REFER TO TRACE OR SYSERR ENTRY
* DOCUMENTATION IN TGHA.DOC FOR FURTHER DETAILS AND RECOVERY INSTRUCTIONS.
*****
REFER TO SECTION 6.9.7 FOR FURTHER EXPLANATION.
6.10.6 THE SOFTWARE STATE OF THE MEMORY INDICATES WHETHER KLI OR TGHA WAS
THE LAST PROGRAM TO MAKE ANY CHANGES IN THE BIT SUB RAM. ALTHOUGH THE
SOFTWARE BITS IN SBUS FUNCTION WAS DESIGNED FOR THIS PURPOSE, CONFLICTS
MADE THEM IMPRACTICAL. THE INFORMATION IS FLAGGED IN A WORD IN THE
BITSUB RAM INSTEAD OF USING THE SOFTWARE STATE BITS. IF, WHEN TGHA GOES
TO CHECK THE STATE OF THE SOFTWARE STATE WORD IN THE BITSUB RAM, TGHA
FINDS THAT THE DATA IS NOT OF THE FORMAT THAT EITHER KLI OR TGHA USES,
THE FOLLOWING MESSAGE WILL BE PUT OUT:
*****
17-AUG-1979 13:02:59
IN CONTROLLER 10 THE BITSUB RAM STATE WORD WAS GARBAGE.
ASSUMING A DBE SCAN WAS DONE LAST. SEE TGHA.DOC FOR FURTHER DETAILS.
*****
THIS IS A VERY STRANGE STATE SINCE THE SPARE BIT SUB RAM ADDRESS
USED FOR THE SOFTWARE STATE WORD IS NOT IN THE ADDRESS SPACE USED FOR
SWAPPING OF MEMORY BITS. IT IS SUGGESTED THAT THE MF20 DIAGNOSTICS BE
RUN AT THE NEXT CONVENIENT TIME.
7.0 MF20.FMT
*** MF20 MEMORY CONTROLLER SBUS DIAGNOSTIC FUNCTIONS ***
FUNCTION 00 00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E) 1* < CONTROLLER NUMBER > !CLEAR* *
TO MEM 2* 0 ! 1 ! ? * ? ! ? ! 0-5 * ! ! * ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E) 3* ! < FUNCTION NUMBER > *
TO MEM 4* ! ! * ! ! * ! ! * ! ! * ! 0 ! 0 * 0 ! 0 ! 0 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E+1) 5*CONTR!CORR !INCMP* <PARITY ERRORS> *INTERLEAVE ! <LAST WORD REQUESTS > *<LAST TYPE>! < ERROR ADDRESS *
FROM MEM 6* ERR ! ERR !CYCLE*READ !WRITE! ADR * 1 ! 1 ! RQ0 * RQ1 ! RQ2 ! RQ3 * RD ! WR ! 14 * 15 ! 16 ! 17 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E+1) 7* ERROR ADDRESS (CONTINUED) > *
FROM MEM 8* 18 ! 19 ! 20 * 21 ! 22 ! 23 * 24 ! 25 ! 26 * 27 ! 28 ! 29 * 30 ! 31 ! 32 * 33 ! 34 ! 35 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
FUNCTION 01 00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E) 1* < CONTROLLER NUMBER > ! *<GROUP LOOPBACK >* *
TO MEM 2* 0 ! 1 ! ? * ? ! ? ! * ! ! * ! ! *ENABL! GN2 ! GN1 * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E) 3* ! < STATUS > !LD EN! ! < FUNCTION NUMBER > *
TO MEM 4* ! ! * ! ! * !DSABL! SF2 * SF1 !25-27! * ! 0 ! 0 * 0 ! 0 ! 1 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E+1) 5* ! <MEM CONTROLLER TYPE> * <LPBK GRP SEL> * *
FROM MEM 6* ! ! * ! ! * ! ! 0 * 1 ! 0 ! 1 * 0 ! 1 ! 2 * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E+1) 7* ! < STATUS > ! *
FROM MEM 8* ! ! * ! ! * !DSABL! SF2 * SF1 ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
SF2 & SF1 ARE SOFTWARE FLAGS DO NOT EFFECT THE HARDWARE, NOR DOES THE HARDWARE AFFECT THEM EXCEPT TO CLEAR THEM ON POWER-UP. THEIR
COMBINED MEANINGS ARE: 0/CONTROLLER WAS JUST POWERED UP; 1/ALL RAMS BUT ADRESP ARE LOADED, CRUDE PATCHING IS DONE AND BITSUB RAM
SAYS WHICH BLOCKS MAY BE USED; 2/SAME AS 1 BUT CONTROLLER IS CONFIGURED; 3/SAME AS 2 EXCEPT THAT TGHA HAS FINISHED ITS WORK.
FUNCTION 02 00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E) 1* < CONTROLLER NUMBER > ! * < SM PROM SELECT > !<PROM BYTE>* *
TO MEM 2* 0 ! 1 ! ? * ? ! ? ! * ! ! * GN2 ! GN1 ! FN2 * FN1 ! 2 ! 1 * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E) 3* ! < DIAG MIXER INPUT SELECT > ! ! < FUNCTION NUMBER > *
TO MEM 4* ! ! * ! ! 2 * 3 ! 4 ! 5 * 6 ! ! * ! 0 ! 0 * 0 ! 1 ! 0 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E+1) 5* !<ERROR WD#>! < SELECTED DIAG DATA OR PROM DATA > * *
FROM MEM 6* ! ! * ! ! 2 * 1 ! 0 ! 1 * 2 ! 3 ! 4 * 5 ! 6 ! 7 * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E+1) 7* ! < MOS ADDRESS (SINGLE STEP ONLY) > !<CTL RAM PAR ERR>! *
FROM MEM 8* ! ! 0 * 1 ! 2 ! 3 * 4 ! 5 ! 6 * 7 ! TIM ! SUB * ADR ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
NOTE: BITS 23-27 ARE ONLY USED DURING SINGLE STEP DIAGNOSTIC TESTS. THE LEFTMOST 1 BIT SELECTS THE CORRESPONDING MIXER INPUT
FOR READING DIAGNOSTIC SIGNALS. IF 23-27 ARE 0 THEN THE DATA RETURNED IS THE SELECTED SM PROM WORD. NOTE ALSO THAT
BITS 26-27 ARE USED TO SELECT THE ADDRESS WHICH IS SENT BACK IN THE MOS ADDRESS FIELD.
*** MF20 MEMORY CONTROLLER SBUS DIAGNOSTIC FUNCTIONS ***
FUNCTION 03 00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E) 1* < CONTROLLER NUMBER > ! !FAST * !<FIXED VAL LOGIC RAMS >!LD EN*LD EN! *
TO MEM 2* 0 ! 1 ! ? * ? ! ? ! * ! ! BUS * !ACKN !D VLD*RDA34!RDA35! 10 *11-13! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E) 3* ! < FIXED VALUE LOGIC RAM LOAD ADDRESS > ! ! < FUNCTION NUMBER > *
TO MEM 4* ! ! 0 * 1 ! 2 ! 3 * 4 ! 5 ! 6 * 7 ! ! * ! 0 ! 0 * 0 ! 1 ! 1 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E+1) 5* !FAST * !<FIXED VAL LOGIC RAMS >! *
FROM MEM 6* ! ! * ! ! * ! ! BUS * !ACKN !D VLD*RDA34!RDA35! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E+1) 7* *
FROM MEM 8* ! ! * ! ! * ! ! * ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
NOTES: THE ACKN RAM (BIT 10) USES ADR BITS 1-7 ONLY.
THE FAST-BUS BIT IS DISCONNECTED INTERNALLY AND IS LEFT IN ONLY FOR DIAGNOSTIC COMPATABILITY.
FUNCTION 04 00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E) 1* < CONTROLLER NUMBER > !PORT * * < SINGLE STEP CLOCK CONTROL *
TO MEM 2* 0 ! 1 ! ? * ? ! ? !LPBK * ! ! *A COM!B COM!D VLD* ! !SSCLK*SSMOD! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E) 3* SS CLK CTL > *REFR !LD EN! * < REFRESH INTERVAL (GATED CLOCK/16) > ! < FUNCTION NUMBER > *
TO MEM 4* ! !RNOW *ALLOW!24-30! * 1 ! 2 ! 3 * 4 ! 5 ! 6 * 7 ! 0 ! 0 * 1 ! 0 ! 0 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E+1) 5* * < SS CLOCK CONTROL ECHO > ! *
FROM MEM 6* ! ! * ! ! * ! ! *A COM!B COM! * ! ! *SSMOD! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E+1) 7* *REFR ! ! < REFRESH INTERVAL COUNTER > ! *
FROM MEM 8* ! ! *ALLOW! ! 0 * 1 ! 2 ! 3 * 4 ! 5 ! 6 * 7 ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
NOTE: IF PORT LOOPBACK IS SET (BIT 5) THE CONTROLLER WILL JUST ECHO ANYTHING SENT OUT BY AN SBUS DIAG AS LONG AS THE PROPER
CONTROLLER NUMBER IS GIVEN. ONLY AN SBUS RESET CAN CLEAR THIS CONDITION.
FUNCTION 05 00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E) 1* < CONTROLLER NUMBER > ! * < SINGLE STEP SIMULATED REQUEST BITS > ! *LD EN! *
TO MEM 2* 0 ! 1 ! ? * ? ! ? ! *ST A !ST B ! RQ0 * RQ1 ! RQ2 ! RQ3 * RD ! WR ! * SS ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E) 3* ! < SINGLE STEP REQUEST SIMULATED ADDRESS BITS > ! < FUNCTION NUMBER > *
TO MEM 4* ! ! 14 * 15 ! 16 ! 17 * 18 ! 19 ! 20 * 21 ! ! 34 * 35 ! 0 ! 0 * 1 ! 0 ! 1 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E+1) 5* *
FROM MEM 6* ! ! * ! ! * ! ! * ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E+1) 7* * < SS MOS RAS > ! *
FROM MEM 8* ! ! * ! ! * 0 ! 1 ! 2 * 3 ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
*** MF20 MEMORY CONTROLLER SBUS DIAGNOSTIC FUNCTIONS ***
FUNCTION 06 00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E) 1* < CONTROLLER NUMBER > ! ! < DIAGNOSTIC DATA TO SY OR WP BOARD > *LD EN! *
TO MEM 2* 0 ! 1 ! ? * ? ! ? ! * ! 32 ! 16 * 8 ! 4 ! 2 * 1 !MISC !MISC *07-14! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E) 3* !<ECC DIAG SUBFCN>! ! < FUNCTION NUMBER > *
TO MEM 4* ! ! * ! ! * ! 4 ! 2 * 1 ! ! * ! 0 ! 0 * 1 ! 1 ! 0 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E+1) 5* ! < DIAGNOSTIC DATA FROM SY OR WP BOARD > * *
FROM MEM 6* ! ! * ! ! * ! 32 ! 16 * 8 ! 4 ! 2 * 1 !MISC !MISC * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E+1) 7* * < SS MOS CAS > ! *
FROM MEM 8* ! ! * ! ! * 0 ! 1 ! 2 * 3 ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
NOTE: SBDIAG FCN 6 DOES DIFFERENT THINGS DEPENDING ON THE SUBFUNCTION CODE IN BITS 25-27:
6.0 READ THE ECC REGISTER ON THE SYN BOARD.
6.1 READ THE SYNDROME BUFFER ON THE SYN BOARD. THIS FUNCTION IS ALSO NORMALLY USED BY MONITOR.
6.2 SEL DIAG BITS 07-13 IN PLACE OF MOS BITS 36-42, FORCE ZEROS ON 00-35, RUN THRU A CORRECTION PASS, AND RETURN 00-35.
*** PLEASE NOTE THAT FCN 6.2 RETURNS THE ENTIRE WORD, NOT JUST BITS 7-14. ***
6.3 UNUSED
6.4 WR ECC COMPLEMENT REG IF BIT 15 SET, THEN READ IT BACK.
6.5 WR ECC COMPLEMENT REG IF BIT 15 SET, THEN ENABLE IT TO BE SENT TO MEM IN PLACE OF D36-42 ON NEXT WR TO MEM.
6.6 READ D36-43 MIXER.
6.7 ENABLE LATCHING OF D36-43 MIXER AFTER NEXT WRITE.
7 8 9 10 11 12 13 14 7 8 9 10 11 12 13 14
+-----+-----*-----+-----+-----*-----+-----+-----* +-----+-----*-----+-----+-----*-----+-----+-----*
SUBFUNCTION ! < MEM BITS 36-43 LATCHED ON LAST RD ERROR > * SUBFUNCTION ! < ECC BITS TO BE COMPLEMENTED ON WR > ! PAR *
6.0 !ECC32!ECC16*ECC8 !ECC4 !ECC2 *ECC1 !E PAR!SPARE* 6.4 ! 32 ! 16 * 8 ! 4 ! 2 * 1 !E PAR! CTL *
+-----+-----*-----+-----+-----*-----+-----+-----* +-----+-----*-----+-----+-----*-----+-----+-----*
+-----+-----*-----+-----+-----*-----+-----+-----* +-----+-----*-----+-----+-----*-----+-----+-----*
SUBFUNCTION ! <SYNDROME LATCHED ON LAST RD ERR> !<ERR TYPE >* SUBFUNCTION ! <BITS 36-43 AS WRITTEN TO MEM AFTER FCN 6.7 > *
6.1 ! 32 ! 16 * 8 ! 4 ! 2 * 1 ! CORR! DBL * 6.6 !ECC32!ECC16*ECC8 !ECC4 !ECC2 *ECC1 !E PAR!SPARE*
+-----+-----*-----+-----+-----*-----+-----+-----* +-----+-----*-----+-----+-----*-----+-----+-----*
FUNCTION 07 00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E) 1* < CONTROLLER NUMBER > ! ! < BIT SUBSTITUTION RAM DATA (BIT NUMBERS) > *LD EN! *
TO MEM 2* 0 ! 1 ! ? * ? ! ? ! * ! 32 ! 16 * 8 ! 4 ! 2 * 1 ! ICE ! PAR *07-14! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E) 3* * < BIT SUBSTITUTION RAM LOAD ADDRESS > ! ! < FUNCTION NUMBER > *
TO MEM 4* ! ! * GN2 ! GN1 ! BN2 * BN1 ! 33 ! 34 * 35 ! ! * ! 0 ! 0 * 1 ! 1 ! 1 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E+1) 5* ! < BIT SUBSTITUTION RAM DATA ECHO > * *
FROM MEM 6* ! ! * ! ! * ! 32 ! 16 * 8 ! 4 ! 2 * 1 ! ICE ! PAR * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E+1) 7* * < SS MOS WR EN > ! *
FROM MEM 8* ! ! * ! ! * 0 ! 1 ! 2 * 3 ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
"ICE" MEANS IGNORE CORRECTABLE ERROR (IE DON'T SET CORR ERR FLAG)
*** MF20 MEMORY CONTROLLER SBUS DIAGNOSTIC FUNCTIONS ***
FUNCTION 10 00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E) 1* < CONTROLLER NUMBER > ! ! < VOLTAGE MARGINS > ! < V MARGIN ENABLES > *LD EN! *
TO MEM 2* 0 ! 1 ! ? * ? ! ? ! * !12.60!5.25 *-2.10!-5.46! 12 * 5 ! -2 !-5.2 *07-14! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E) 3* !CORR * CLR ! ! < FUNCTION NUMBER > *
TO MEM 4* ! ! * ! ! * ! ! DIS *DCBAD! ! * ! 0 ! 1 * 0 ! 0 ! 0 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E+1) 5* ! < VOLTAGE MARGINS > ! < V MARGINS ENABLED > * *
FROM MEM 6* ! ! * ! ! * !12.60!5.25 *-2.10!-5.46! 12 * 5 ! -2 !-5.2 * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E+1) 7* !CORR * DC ! *
FROM MEM 8* ! ! * ! ! * ! ! DIS * BAD ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
NOTE: THE VOLTAGES GIVEN ABOVE APPLY FOR ONES IN BITS 7-10 WHERE ENABLED BY BITS 11-14. THE VOLTAGES CORRESPONDING TO ZEROS
IN BITS 7-10 ARE 11.40, 4.75, -1.90, AND -4.94. MORE THAN ONE MARGIN MAY BE SET CONCURRENTLY.
FUNCTION 11 00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E) 1* < CONTROLLER NUMBER > ! ! < TIMING RAM LOAD ADR... *
TO MEM 2* 0 ! 1 ! ? * ? ! ? ! * ! ! * ! ! * ! 0 ! 1 * 2 ! 3 ! 4 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E) 3* ...ADR > !LD EN* < TIMING RAM DATA > ! ! < FUNCTION NUMBER > *
TO MEM 4* 5 ! 6 !21-30* RAS ! CAS ! PAR *WR EN!2ND A!D RDY*B CLR! ! * ! 0 ! 1 * 0 ! 0 ! 1 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E+1) 5* *
FROM MEM 6* ! ! * ! ! * ! ! * ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E+1) 7* * < TIMING RAM DATA ECHO > ! ! 4K *-DSEL! *
FROM MEM 8* ! ! * RAS ! CAS ! PAR *WR EN!2ND A!D RDY*B CLR! ! EN *CYCEN! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
FUNCTION 12 00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E) 1* < CONTROLLER NUMBER > ! ! < ADDRESS RESPONSE RAM DATA > *LD EN! *
TO MEM 2* 0 ! 1 ! ? * ? ! ? ! * ! ! PAR *TYPE ! GN2 ! GN1 * BN2 ! BN1 !DESEL*08-14! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E) 3* ! < ADDRESS RESPONSE RAM LOAD ADDRESS > ! ! < FUNCTION NUMBER > *
TO MEM 4* ! ! 14 * 15 ! 16 ! 17 * 18 ! 19 ! 20 * 21 ! ! * ! 0 ! 1 * 0 ! 1 ! 0 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
LH(E+1) 5* ! < ADDRESS RESPONSE RAM ECHO > * *
FROM MEM 6* ! ! * ! ! * ! ! PAR *TYPE ! GN2 ! GN1 * BN2 ! BN1 !DESEL* ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
RH(E+1) 7* *
FROM MEM 8* ! ! * ! ! * ! ! * ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
NOTE: "DESEL" (BIT 14) IS "BOX DESELECTED ON 1".
*** MF20 STORAGE ORGANIZATION ***
--------------------------------------------------------------------------------------------------------------------------------
MF20 STORAGE IS COMPOSED OF GROUPS, FIELDS, BLOCKS, & SUBBLOCKS. KL10 BIT NUMBER VS. "FIELD" LOCATION
A GROUP IS A SET OF FOUR STORAGE BOARDS. A FIELD IS ONE BOARD (11 BITS) ----------------------------------------
WIDE. 4 FIELDS USED IN PARALLEL GIVE A 44-BIT WORD: 36 DATA BITS, 6 ECC
(ERROR CHECK & CORRECT) BITS, ONE 43-BIT PARITY BIT, AND ONE SPARE BIT. KL10 BIT BIT IN SYNDROME
A BIT'S GROUP AND FIELD NUMBERS UNIQUELY PICK THE BIT'S STORAGE BOARD. BIT USE FIELD FIELD (NOTE 1)
A GROUP HAS 1 TO 4 BLOCKS (USUALLY 4) NUMBERED FROM 0. A BLOCK'S SIZE ---- ------ ----- ------ --------
IS 4 TIMES RAM SIZE. ITS START ADDRESS IS PROGRAMMABLE (SBDIAG FCN 12). 00 DATA 0 02 014
EACH BLOCK HAS 4 SUBBLOCKS. SUBBLOCKS ARE THE BASIC MF20 STORAGE UNIT, 01 DATA 1 02 024
ARE 1 WORD (44 BITS) WIDE, AND ARE SELECTED BY ADDRESS 34-35. EVERY 4TH 02 DATA 0 03 030
WORD OF A BLOCK'S MEMORY BELONGS TO A GIVEN SUBBLOCK. THERE IS 1 SPARE 03 DATA 1 03 034
BIT RAM PER SUBBLOCK. DURING A MEMORY CYCLE ALL OF THE BLOCK'S FIELDS 04 DATA 0 04 044
AND SUBBLOCKS ARE ALWAYS CYCLED, WITH THE 4 XBUS REQUEST BITS SPECIFYING 05 DATA 1 04 050
WHICH SUBBLOCK'S WORDS ARE ACTUALLY TO BE USED. 06 DATA 0 05 054
07 DATA 1 05 060
TABLE OF SLOT NUMBERS VS. GROUP, FIELD, AND BIT. 08 DATA 0 06 064
-------------------------------------------------------- 09 DATA 1 06 070
10 DATA 0 07 074
SLOT GROUP FIELD BITS 11 DATA 1 07 104
---- ----- ----- -------------------------------- 12 DATA 0 08 110
8 2 0 36,38,00,02,04,06,08,10,12,14,16 13 DATA 1 08 114
9 1 0 SAME 14 DATA 0 09 120
10 0 0 SAME 15 DATA 1 09 124
11 2 1 37,39,01,03,05,07,09,11,13,15,17 16 DATA 0 10 130
12 1 1 SAME 17 DATA 1 10 134
13 0 1 SAME 18 DATA 2 02 140
14 2 2 40,42,18,20,22,24,26,28,30,32,34 19 DATA 3 02 144
15 1 2 SAME 20 DATA 2 03 150
16 0 2 SAME 21 DATA 3 03 154
17 2 3 41,43,19,21,23,25,27,29,31,33,35 22 DATA 2 04 160
18 1 3 SAME 23 DATA 3 04 164
19 0 3 SAME 24 DATA 2 05 170
25 DATA 3 05 174
------------------------------------------------------------------------ 26 DATA 2 06 204
27 DATA 3 06 210
CALCULATING A FAILED RAM "E" NUMBER 28 DATA 2 07 214
----------------------------------- 29 DATA 3 07 220
30 DATA 2 08 224
TO CALCULATE THE "E" NUMBER OF A RAM ON AN M8579 BOARD YOU NEED 31 DATA 3 08 230
THE BLOCK NUMBER (BN), WORD NUMBER (WN), AND BIT-IN-FIELD NUMBER (BIFN). 32 DATA 2 09 234
USE ERROR ADDRESS BITS 14-21 IN AN SBDIAG FUNCTION 12 TO READ THE 33 DATA 3 09 240
ADDRESS RESPONSE RAM. BITS 12-13 OF THE SBDIAG ECHO ARE BN. ERROR 34 DATA 2 10 244
ADDRESS BITS 34-35 ARE WN. BIFN CAN BE DERIVED FROM THE TABLE ON THE 35 DATA 3 10 250
RIGHT USING EITHER THE SYNDROME (FROM FUNCTION 6.1) OR KNOWN ERROR DATA 36 ECC32 0 00 200
PATTERN. USE BIFN TO SELECT A NUMBER FROM THE TABLE BELOW AND PLUG THAT 37 ECC16 1 00 100
NUMBER INTO THE FORMULA TO GET THE ACTUAL "E" NUMBER. 38 ECC8 0 01 040
39 ECC4 1 01 020
BIFN: 0 1 2 3 4 5 6 7 8 9 10 40 ECC2 2 00 010
TABLE: 19. 38. 57. 76. 96. 116. 149. 167. 188. 204. 224. 41 ECC1 3 00 004
42 ECCPAR 2 01 000
FORMULA: E# = TABLE(BIFN) - (4 * WN) - BN 43 SPARE 3 01 (NOTE 2)
NOTE 1: THE SYNDROME IS A SIX BIT NUMBER AND IS SHOWN HERE OCTALLY GROUPED AS IT WOULD APPEAR IN AN SBDIAG FUNCTION 6.1 ECHO
IN BITS 07-12. NOTE THAT THE 43-BIT PARITY BIT IS NOT INCLUDED IN THIS LIST.
NOTE 2: THE SPARE BIT HAS NO ASSOCIATED SYNDROME. IF THE SPARE BIT HAPPENS TO BE REPLACING THE BIT WHICH YOUR SYNDROME
POINTS TO, THEN THE ERROR IS IN THE SPARE BIT AND NOT THE BIT WHICH THE SYNDROME POINTS TO.
MF20 ARRAY BOARD PROM DATA. M8579 MF20 STORAGE ARRAY BOARD E NUMBER LAYOUT
------------------------------------------------------------------------ ----------------------------------------------------
EVERY MF20 STORAGE ARRAY BOARD HAS ASSOCIATED WITH IT A SERIAL THE M8579 STORAGE BOARDS DO NOT HAVE ANY E NUMBERS
NUMBER AND OTHER RELATED DATA. THERE IS ONE 32-BIT PROM "WORD" PER ETCHED ON THEM, MAKING IT DIFFICULT TO LOCATE A
BOARD WHICH IS READ USING FUNCTION 2. WHICH WORD YOU GET DEPENDS UPON SPECIFIC DIP. USE THE MAP BELOW TO LOCATE MOS RAM
BITS 9-12. FOUR SBDIAGS ARE NECESSARY TO READ THE ENTIRE WORD BY DIPS OR DC008 MUX DIPS. EXAMPLE: THE E NUMBER FOR
VARYING THE BYTE NUMBER IN BITS 13 & 14. THE LAYOUT OF A PROM WORD IS BLOCK (BLK) 2, SUBBLOCK (SBLK) 1, BIT 18 WOULD BE
AS FOLLOWS: 51. USE BLK & SBLK TO FIND THE ROW. USING THE BIT
NUMBER, LOOK IN THE LOWER TABLE TO FIND THE COLUMN.
PROM BYTE: 0 1 2 3 THE MAP IS ORIENTED AS IF YOU HELD THE BOARD WITH
PROM BIT: 01234567012345670123456701234567 THE COMPONENT SIDE UP AND THE CONNECTOR EDGE TOWARDS
CONTENT: YYYYWWWWWW###########PPABNNSSMMM YOU. NOTE THAT THE ROW OF MUX CHIPS IS STAGGERED.
YYYY IS THE 4 BIT YEAR NUMBER WHICH IS THE BCD EQUIVALENT OF THE BLK SBLK MOS RAM AND MUX CHIP E NUMBERS
LAST DIGIT OF THE CALENDAR YEAR. --- ---- -------------------------------------------
WWWWWW IS THE 6 BIT WEEK NUMBER. 0 0 224 204 188 167 149 116 96 76 57 38 19
1 0 223 203 187 166 148 115 95 75 56 37 18
##...## IS AN 11 BIT SERIAL NUMBER WHICH IS RESTARTED FROM 1 EACH WEEK. 2 0 222 202 186 165 147 114 94 74 55 36 17
3 0 221 201 185 164 146 113 93 73 54 35 16
PP IS A MOS RAM POPULATION CODE: 00 - MOS RAM BLOCK 0 EXISTS 0 1 220 200 184 163 145 112 92 72 53 34 15
01 - BLOCKS 0 & 1 EXIST 1 1 219 199 183 162 144 111 91 71 52 33 14
10 - BLOCKS 0, 1, & 2 EXIST 2 1 218 198 182 161 143 110 90 70 51 32 13
11 - BOARD IS FULLY POPULATED 3 1 217 197 181 160 142 109 89 69 50 31 12
0 2 216 196 180 159 141 108 88 68 49 30 11
A PARITY BIT SUCH THAT BYTES 0-2 OF THE WORD HAVE EVEN PARITY. 1 2 215 195 179 158 140 107 87 67 48 29 10
2 2 214 194 178 157 139 106 86 66 47 28 9
B ANOTHER PARITY BIT SUCH THAT BYTE 3 HAS ODD PARITY. 3 2 213 193 177 156 138 105 85 65 46 27 8
0 3 212 192 176 155 137 104 84 64 45 26 7
NN IS THE 2 BIT "TIMING NUMBER". THIS NUMBER DETERMINES WHICH 1 3 211 191 175 154 136 103 83 63 44 25 6
DISTINCT TIMING IS TO BE USED WITH THE RAMS ON THIS BOARD. 2 3 210 190 174 153 135 102 82 62 43 24 5
3 3 209 189 173 152 134 101 81 61 42 23 4
SS IS THE MOS RAM SIZE CODE: 11 - INDICATES 4K RAMS MUX ==> 207 205 171 169 131 98 79 59 40 20 2
10 - 16K RAMS
01 - 32K RAMS FIELD KL10 BIT NUMBERS AS POSITIONED IN FIELD
00 - 64K RAMS ----- -------------------------------------------
0 16 14 12 10 08 06 04 02 00 38 36
MMM IS THE 3 BIT MOS RAM MANUFACTURER CODE: 1 17 15 13 11 09 07 05 03 01 39 37
2 34 32 30 28 26 24 22 20 18 42 40
000 - MOSTEK 100 - MOTOROLA 3 35 33 31 29 27 25 23 21 19 43 41
001 - INTEL 101 - T.I.
010 - FUJITSU 110 - OTHER (DEC, DEC PART NUMBER, ETC.)
011 - HITACHI 111 - UNASSIGNED ====================================================
THERE ARE ACTUALLY 8 PROM WORDS PER ARRAY BOARD, OF WHICH ONLY
ONE IS ALLOWED OUT BY THE STATE OF THE 3 JUMPERS. IF NO JUMPER IS CUT CONTROL BOARD SLOT NUMBERS & BASIC FUNCTIONS
THEN WORD 0 IS SELECTED, IF ALL ARE CUT THEN WORD 7 IS SELECTED. THESE ----------------------------------------------------
JUMPERS ARE CUT IN RELATION TO THE MANUFACTURER OF THE MOS RAMS ON THE
BOARD. NOTE ALSO THAT THE SERIAL NUMBER IS ALSO PRINTED ON THE BOARD IN NUMBER NAME SLOT FUNCTION
THE FORM:
YWW#### M8574 WRP 04 XBUS DATA/WR PATH/ECC GEN/SPARE OUT
M8576 CTL 05 XBUS & CYC CTL/WD & GRP SEL/PROM RD
**** PLEASE MAKE SURE WHEN AN ARRAY BOARD IS SENT IN FOR REPAIR THAT THE M8575 SYN 06 SPARE IN/CHK/CORR/ADR 14-21/V MARG
**** ERROR TYPEOUT SHOWING THE SERIAL NUMBER IS ATTACHED TO THE BOARD. M8577 ADT 07 MOS ADR/TIMING/REFRESH/BLK SEL/ERR
*** MF20 ERROR CORRECTION CODE (ECC) CALCULATION ***
CALCULATION OF THE ECC IS BASED UPON BIT CHANGES FROM A DATA WORD OF ALL ZEROS. THE ECC FOR ALL ZEROS IS DEFINED TO BE
11 111 11 (OR 376 AS IT WOULD APPEAR IN BITS 07-13 OF AN SBDIAG FUNC 6.0). TO CALCULATE WHAT THE ECC SHOULD BE FOR ANY GIVEN WORD:
TAKE EACH "1" BIT FROM THE DATA WORD, GET THE SYNDROME FOR THAT BIT FROM THE TABLE BELOW, AND XOR IT INTO THE PREVIOUS ECC.
INITIALLY THE ECC IS THE ECC FOR A DATA WORD OF ZERO.
IF THERE ARE MORE ONES THAN ZEROS IN THE WORD THEN DO THE SAME AS ABOVE ONLY APPLY THE SYNDROMES FOR EACH "0" BIT AND USE
THE INITIAL ECC VALUE OF 10 101 11 (256 OCTAL). NOTE THAT THE FOLLOWING RELATION ALWAYS HOLDS:
ECC(X)=120.XOR.ECC(.NOT.X)
WHICH MEANS THAT THE ECC FOR THE COMPLEMENT OF A WORD DIFFERS FROM THE ECC OF THE WORD BY 120 OCTAL.
*** SYNDROME & 43-BIT PARITY TABLE ***
BIT FCN 6 SYN SYN SYN SYN SYN SYN 43B
# OCTAL 32 16 8 4 2 1 PAR
--- ----- --- --- --- --- --- --- ---
00 016 0 0 0 0 1 1 1 EXAMPLE: CALCULATE THE ECC & 43-BIT PARITY FOR A DATA WORD OF 3
01 026 0 0 0 1 0 1 1
02 032 0 0 0 1 1 0 1 376 IS ECC FOR ZERO
03 034 0 0 0 1 1 1 0 250 IS SYNDROME & 43B PAR FOR BIT 35
04 046 0 0 1 0 0 1 1 244 IS SYNDROME & 43B PAR FOR BIT 34
05 052 0 0 1 0 1 0 1 --- .XOR. ALL OF THE ABOVE
06 054 0 0 1 0 1 1 0 362 IS THE ECC FOR 3
07 062 0 0 1 1 0 0 1
08 064 0 0 1 1 0 1 0
09 070 0 0 1 1 1 0 0
10 076 0 0 1 1 1 1 1
11 106 0 1 0 0 0 1 1 ANOTHER METHOD FOR COMPUTING THE ECC IS AS FOLLOWS: FOR EACH OF THE 7
12 112 0 1 0 0 1 0 1 ECC BITS TAKE THE DATA WORD, .AND. IT WITH THE APPROPRIATE MASK BELOW,
13 114 0 1 0 0 1 1 0 AND COMPUTE THE RESULT'S ODD PARITY. THAT BIT IS ONE OF THE ECC BITS.
14 122 0 1 0 1 0 0 1
15 124 0 1 0 1 0 1 0 000000 001777 ECC 32
16 130 0 1 0 1 1 0 0 000177 776000 ECC 16
17 136 0 1 0 1 1 1 1 037600 776007 ECC 8
18 142 0 1 1 0 0 0 1 343617 036170 ECC 4
19 144 0 1 1 0 0 1 0 554663 146631 ECC 2
20 150 0 1 1 0 1 0 0 665325 253252 ECC 1
21 156 0 1 1 0 1 1 1 732351 455514 43B PAR
22 160 0 1 1 1 0 0 0
23 166 0 1 1 1 0 1 1
24 172 0 1 1 1 1 0 1
25 174 0 1 1 1 1 1 0
26 206 1 0 0 0 0 1 1
27 212 1 0 0 0 1 0 1 BITS 03, 09, 10, 13, 15, 25, AND 32 (040624 002010) FORM A SET WHICH IS
28 214 1 0 0 0 1 1 0 ONE OF MANY POSSIBLE "INDEPENDENT" BIT SETS. BY VARYING THE VALUES OF
29 222 1 0 0 1 0 0 1 THESE 7 BITS ONE CAN GENERATE ALL 128 ECC CODES, THOUGH NOT IN ANY
30 224 1 0 0 1 0 1 0 SPECIAL ORDER. ADDING BIT 35 ALLOWS PLAYING WITH THE SPARE BIT BUT DOES
31 230 1 0 0 1 1 0 0 NOT ALTER THE INDEPENDENCE OF THIS BIT SET.
32 236 1 0 0 1 1 1 1
33 242 1 0 1 0 0 0 1
34 244 1 0 1 0 0 1 0 NOTE THAT THE OCTAL NUMBER 200,,2217 (33555599 DECIMAL) IS A SMALL,
35 250 1 0 1 0 1 0 0 RELATIVELY EASY TO REMEMBER NUMBER WHICH PRODUCES AN ALL ZEROS ECC.
-- -- -- -- -- -- --
10 15 18 19 20 20 20 <== SUM OF SYNDROME ONE BITS
*** MF20 ERROR DETECTION AND CORRECTION ***
---------------------------------------------
HOW MF20 ERROR CORRECTION WORKS. AN EXAMPLE OF ERROR CORRECTION.
-------------------------------- -------------------------------
WHEN A WRITE IS DONE THE MF20 CALCULATES AN ECC BASED UPON THE WRITE A 3 TO MEMORY, ASSUME THAT BIT 27 IS STUCK
DATA IT GOT FROM THE CPU. THE DATA AND THE ECC ARE THEN PUT IN MEMORY. HIGH IN MEMORY. AS SHOWN ON THE PREVIOUS PAGE
WHEN A READ IS DONE THE MF20 GETS THE DATA AND THE OLD ECC FROM MEMORY. THE ECC FOR 3 IS 362, THEREFORE:
IT THEN COMPUTES A NEW ECC ON THE DATA AND XOR'S THE OLD AND NEW ECC'S 3<362> GOES TO MEMORY.
WHICH RESULTS IN A SYNDROME. OBVIOUSLY IF THERE WAS NO ERROR IN MEMORY ON THE READ BIT 27 IS STUCK HIGH SO THAT WE SEE:
THE OLD AND NEW ECC'S WILL BE THE SAME, AND THE SYNDROME WILL BE ZERO 403<362> FROM MEMORY.
SINCE XOR'ING EQUAL VALUES PRODUCES 0. WE CALCULATE THE NEW ECC:
374 IS ECC FOR 0 (LESS 43B PAR BIT)
NOW, WHEN THERE IS AN ERROR IN ONE BIT THE NEW SYNDROME WILL 250 IS SYNDROME FOR BIT 35
DIFFER FROM WHAT IT WOULD HAVE BEEN BY A VALUE EQUAL TO THE SYNDROME OF 244 IS SYNDROME FOR BIT 34
THE BAD BIT. THUS XOR'ING THE NEW SYNDROME WITH THE OLD ONE FROM MEMORY 210 IS SYNDROME FOR BIT 27
WILL RESULT IN A SYNDROME EQUAL TO THAT OF THE BAD BIT. THE SYNDROME --- XOR THE WHOLE MESS TOGETHER
MAPPED TO A BIT WHICH, IN TURN, IS USED TO COMPLEMENT (IE CORRECT) THE 170 IS THE NEW ECC.
BAD BIT. SEE EXAMPLE ON RIGHT AT TOP. WE NOW CALCULATE THE SYNDROME:
360 IS THE OLD ECC (LESS 43B PAR BIT)
WHEN ONE BIT IS BAD ON A READ THEN, OBVIOUSLY, THE PARITY OF THE 170 IS THE NEW ECC
43-BIT WORD FROM MEMORY WILL BE BAD. BAD PARITY IS WHAT CAUSES THE MF20 --- XOR
TO RECOGNIZE A CORRECTABLE ERROR. THE MF20 THEN GOES OFF AND COMPUTES 210 IS THE SYNDROME
THE SYNDROME. IF THE SYNDROME IS THAT OF ONE OF THE ECC BITS THEN THE THE HARDWARE MAPS THE SYNDROME TO THE PROPER BIT
MAPPED CORRECTION BIT GOES NOWHERE SINCE WE DON'T SEND THE ECC BACK TO AND CHANGES THE BIT:
THE CPU. 403 IS DATA FROM MEMORY
400 IS THE MAPPED BIT
IF THERE IS NO PARITY ERROR AND THE SYNDROME IS ZERO THEN THERE --- XOR
IS NO CORRECTION NECESSARY. HOWEVER A DOUBLE BIT (UNCORRECTABLE) ERROR 3 IS WHAT GOES BACK TO THE CPU.
GIVES GOOD PARITY (SINCE 2 BITS ARE BAD) AND A NONZERO SYNDROME. THIS HOCUS-POCUS-PRESTO-CHANGO, THE ERROR IS GONE!
IS HOW AN MF20 RECOGNIZES AN DOUBLE BIT ERROR. WHEN A DOUBLE BIT ERROR
IS DETECTED THE MF20 SHIPS THE DATA, AS IS, TO THE CPU WHILE FORCING BAD ----------------------------------------------------
XBUS PARITY. SEE THE TABLE ON THE RIGHT AT THE BOTTOM FOR A CONCISE
LIST OF ERROR CONDITIONS. SYNDROME PARITY MEANING & ACTION TAKEN BY MF20
-------- ------ ------------------------------
SOFTWARE DOUBLE BIT ERROR CORRECTION.
------------------------------------- ZERO OK EVERY THING IS OK. TAKE DATA
AS IT IS.
WHEN A DOUBLE BIT ERROR OCCURS ALL IS NOT LOST. WE MAY BE ABLE
TO RECOVER THE DATA USING A SOFTWARE ALGORITHM PROVIDED THAT AT LEAST ZERO BAD 43-BIT PARITY BIT IS BAD.
ONE OF THE BAD BITS IS A HARD FAILURE. (1) GET THE WORD AND ITS USE THE DATA AS IT IS.
SYNDROME. (2) WRITE THE WORD'S COMPLEMENT TO THE FAILED LOCATION. (3)
EQUIVALENCE THE MEMORY WORD WITH THE ORIGINAL WORD. (4) IF THE RESULT IS 1,2,4,8, BAD AN ECC BIT IS BAD. USE THE
ZERO OR HAS MORE THAN 2 BITS SET, PUNT. (5) IF EXACTLY TWO BITS ARE SET 16,32 DATA AS IT IS.
IN THE EQUIVALENCE THEN XOR IT INTO THE ORIGINAL WORD AND YOU'RE DONE.
(6) IF THERE IS ONE BIT SET IN THE EQUIVALENCE THEN GET ITS BIT NUMBER. NOT 0 OR BAD A DATA BIT IS BAD. CORRECT IT
(7) USE THE ORIGINAL SYNDROME TO FIND THE LINE IN THE TABLE ON THE NEXT 1,2, ETC AND SEND BACK CORRECTED WORD.
PAGE WHERE YOU WILL LOOK. (8) FIND THE BIT PAIR CONTAINING THE BIT. (9)
IF NOT FOUND, PUNT. (10) CORRECT THE BITS IN THE ORIGINAL WORD INDICATED NOT 0 OK THIS IS A NON-CORRECTABLE
BY THE BIT PAIR AND YOU'RE DONE. ERROR. PUT DATA ON XBUS AS
IT IS PLUS BAD PARITY.
THIS ALGORITHM BECOMES MORE COMPLICATED WHEN THE ECC & SPARE ARE
TAKEN INTO CONSIDERATION TOO. HOWEVER THE ESSENTIAL IDEA REMAINS THE
SAME. WHILE SOFTWARE CORRECTION OF DOUBLE BIT ERRORS IS NOT IMPLEMENTED
THE BASIC ALGORITHM IS INCLUDED HERE SHOULD THE NEED FOR IT ARISE.
THIS IS THE TABLE OF SYNDROMES VS. ALL POSSIBLE BIT PAIRS WHICH COULD CAUSE A DOUBLE
BIT ERROR WITH THAT SYNDROME. THE SYNDROME IS THE OCTAL NUMBER ON THE LEFT. REMEMBER THAT
IT IS ONLY 6 BITS BUT IS SHOWN ALIGNED AS IT IS IN AN SBUS DIAG FUNCTION 6.1. ALL THE BIT
PAIRS WHICH WOULD RESULT IN A GIVEN SYNDROME ARE ON THE LINE TO THE RIGHT OF THE SYNDROME.
THESE PAIRS ARE DECIMAL KL10 BIT NUMBERS WITH THE LOWER NUMBER OF THE PAIR TO THE LEFT OF THE
COMMA. THE PAIRS ARE IN ORDER BY THE LOWER NUMBER. THE TABLE CONTINUES ON THE NEXT PAGE.
SYN BIT PAIRS WHICH COULD CAUSE A DBE WITH THE GIVEN SYNDROME
--- ---------------------------------------------------------
374 15,35 16,34 17,33 18,32 19,31 20,30 21,29 22,28 23,27 24,26 25,36
370 14,35 16,33 17,34 18,31 19,32 20,29 21,30 22,27 23,28 24,36 25,26
364 14,34 15,33 17,35 18,30 19,29 20,32 21,31 22,26 23,36 24,28 25,27
360 14,33 15,34 16,35 18,29 19,30 20,31 21,32 22,36 23,26 24,27 25,28
354 11,35 12,34 13,33 18,28 19,27 20,26 21,36 22,32 23,31 24,30 25,29
350 12,33 13,34 18,27 19,28 20,36 21,26 22,31 23,32 24,29 25,30 35,37
344 11,33 13,35 18,26 19,36 20,28 21,27 22,30 23,29 24,32 25,31 34,37
340 11,34 12,35 18,36 19,26 20,27 21,28 22,29 23,30 24,31 25,32 33,37
334 11,31 12,30 13,29 14,28 15,27 16,26 17,36 23,35 24,34 25,33 32,37
330 11,32 12,29 13,30 14,27 15,28 16,36 17,26 22,35 24,33 25,34 31,37
324 11,29 12,32 13,31 14,26 15,36 16,28 17,27 22,34 23,33 25,35 30,37
320 11,30 12,31 13,32 14,36 15,26 16,27 17,28 22,33 23,34 24,35 29,37
314 11,27 12,26 13,36 14,32 15,31 16,30 17,29 19,35 20,34 21,33 28,37
310 11,28 12,36 13,26 14,31 15,32 16,29 17,30 18,35 20,33 21,34 27,37
304 11,36 12,28 13,27 14,30 15,29 16,32 17,31 18,34 19,33 21,35 26,37
300 11,26 12,27 13,28 14,29 15,30 16,31 17,32 18,33 19,34 20,35 36,37
274 01,35 02,34 03,33 04,31 05,30 06,29 07,28 08,27 09,26 10,36 32,38
270 02,33 03,34 04,32 05,29 06,30 07,27 08,28 09,36 10,26 31,38 35,39
264 01,33 03,35 04,29 05,32 06,31 07,26 08,36 09,28 10,27 30,38 34,39
260 01,34 02,35 04,30 05,31 06,32 07,36 08,26 09,27 10,28 29,38 33,39
254 00,33 04,27 05,26 06,36 07,32 08,31 09,30 10,29 28,38 34,40 35,41
250 00,34 04,28 05,36 06,26 07,31 08,32 09,29 10,30 27,38 33,40 35,42
244 00,35 04,36 05,28 06,27 07,30 08,29 09,32 10,31 26,38 33,41 34,42
240 04,26 05,27 06,28 07,29 08,30 09,31 10,32 33,42 34,41 35,40 36,38
234 00,29 01,27 02,26 03,36 08,35 09,34 10,33 28,39 30,40 31,41 32,42
230 00,30 01,28 02,36 03,26 07,35 09,33 10,34 27,39 29,40 31,42 32,41
224 00,31 01,36 02,28 03,27 07,34 08,33 10,35 26,39 29,41 30,42 32,40
220 00,32 01,26 02,27 03,28 07,33 08,34 09,35 29,42 30,41 31,40 36,39
214 00,36 01,31 02,30 03,29 04,35 05,34 06,33 26,40 27,41 28,42 32,39
210 00,26 01,32 02,29 03,30 05,33 06,34 27,42 28,41 31,39 35,38 36,40
204 00,27 01,29 02,32 03,31 04,33 06,35 26,42 28,40 30,39 34,38 36,41
200 00,28 01,30 02,31 03,32 04,34 05,35 26,41 27,40 29,39 33,38 36,42
SYN BIT PAIRS WHICH COULD CAUSE A DBE WITH THE GIVEN SYNDROME (CONTINUED FROM PREVIOUS PAGE)
--- -----------------------------------------------------------------------------------------
174 00,22 01,20 02,19 03,18 04,16 05,15 06,14 07,13 08,12 09,11 10,37 17,38 21,39 23,40 24,41 25,42
170 00,23 01,21 02,18 03,19 04,17 05,14 06,15 07,12 08,13 09,37 10,11 16,38 20,39 22,40 24,42 25,41
164 00,24 01,18 02,21 03,20 04,14 05,17 06,16 07,11 08,37 09,13 10,12 15,38 19,39 22,41 23,42 25,40
160 00,25 01,19 02,20 03,21 04,15 05,16 06,17 07,37 08,11 09,12 10,13 14,38 18,39 22,42 23,41 24,40
154 00,18 01,24 02,23 03,22 04,12 05,11 06,37 07,17 08,16 09,15 10,14 13,38 19,40 20,41 21,42 25,39
150 00,19 01,25 02,22 03,23 04,13 05,37 06,11 07,16 08,17 09,14 10,15 12,38 18,40 20,42 21,41 24,39
144 00,20 01,22 02,25 03,24 04,37 05,13 06,12 07,15 08,14 09,17 10,16 11,38 18,41 19,42 21,40 23,39
140 00,21 01,23 02,24 03,25 04,11 05,12 06,13 07,14 08,15 09,16 10,17 18,42 19,41 20,40 22,39 37,38
134 00,14 01,12 02,11 03,37 04,24 05,23 06,22 07,21 08,20 09,19 10,18 13,39 15,40 16,41 17,42 25,38
130 00,15 01,13 02,37 03,11 04,25 05,22 06,23 07,20 08,21 09,18 10,19 12,39 14,40 16,42 17,41 24,38
124 00,16 01,37 02,13 03,12 04,22 05,25 06,24 07,19 08,18 09,21 10,20 11,39 14,41 15,42 17,40 23,38
120 00,17 01,11 02,12 03,13 04,23 05,24 06,25 07,18 08,19 09,20 10,21 14,42 15,41 16,40 22,38 37,39
114 00,37 01,16 02,15 03,14 04,20 05,19 06,18 07,25 08,24 09,23 10,22 11,40 12,41 13,42 17,39 21,38
110 00,11 01,17 02,14 03,15 04,21 05,18 06,19 07,24 08,25 09,22 10,23 12,42 13,41 16,39 20,38 37,40
104 00,12 01,14 02,17 03,16 04,18 05,21 06,20 07,23 08,22 09,25 10,24 11,42 13,40 15,39 19,38 37,41
100 00,13 01,15 02,16 03,17 04,19 05,20 06,21 07,22 08,23 09,24 10,25 11,41 12,40 14,39 18,38 37,42
074 00,07 01,05 02,04 03,38 06,39 08,40 09,41 10,42 11,24 12,23 13,22 14,21 15,20 16,19 17,18 25,37 30,35 31,34 32,33
070 00,08 01,06 02,38 03,04 05,39 07,40 09,42 10,41 11,25 12,22 13,23 14,20 15,21 16,18 17,19 24,37 29,35 31,33 32,34
064 00,09 01,38 02,06 03,05 04,39 07,41 08,42 10,40 11,22 12,25 13,24 14,19 15,18 16,21 17,20 23,37 29,34 30,33 32,35
060 00,10 01,04 02,05 03,06 07,42 08,41 09,40 11,23 12,24 13,25 14,18 15,19 16,20 17,21 22,37 29,33 30,34 31,35 38,39
054 00,38 01,09 02,08 03,07 04,40 05,41 06,42 10,39 11,20 12,19 13,18 14,25 15,24 16,23 17,22 21,37 26,35 27,34 28,33
050 00,04 01,10 02,07 03,08 05,42 06,41 09,39 11,21 12,18 13,19 14,24 15,25 16,22 17,23 20,37 27,33 28,34 35,36 38,40
044 00,05 01,07 02,10 03,09 04,42 06,40 08,39 11,18 12,21 13,20 14,23 15,22 16,25 17,24 19,37 26,33 28,35 34,36 38,41
040 00,06 01,08 02,09 03,10 04,41 05,40 07,39 11,19 12,20 13,21 14,22 15,23 16,24 17,25 18,37 26,34 27,35 33,36 38,42
034 00,39 01,40 02,41 03,42 04,09 05,08 06,07 10,38 11,16 12,15 13,14 17,37 18,25 19,24 20,23 21,22 26,31 27,30 28,29 32,36
030 00,01 02,42 03,41 04,10 05,07 06,08 09,38 11,17 12,14 13,15 16,37 18,24 19,25 20,22 21,23 26,32 27,29 28,30 31,36 39,40
024 00,02 01,42 03,40 04,07 05,10 06,09 08,38 11,14 12,17 13,16 15,37 18,23 19,22 20,25 21,24 26,29 27,32 28,31 30,36 39,41
020 00,03 01,41 02,40 04,08 05,09 06,10 07,38 11,15 12,16 13,17 14,37 18,22 19,23 20,24 21,25 26,30 27,31 28,32 29,36 39,42
014 00,42 01,02 03,39 04,05 06,38 07,10 08,09 11,12 13,37 14,17 15,16 18,21 19,20 22,25 23,24 26,27 28,36 29,32 30,31 34,35 40,41
010 00,41 01,03 02,39 04,06 05,38 07,09 08,10 11,13 12,37 14,16 15,17 18,20 19,21 22,24 23,25 26,28 27,36 29,31 30,32 33,35 40,42
004 00,40 01,39 02,03 04,38 05,06 07,08 09,10 11,37 12,13 14,15 16,17 18,19 20,21 22,23 24,25 26,36 27,28 29,30 31,32 33,34 41,42
000 A ZERO SYNDROME NEVER CAUSES A DOUBLE BIT ERROR.
MISCELLANEOUS KL10 I/O INSTRUCTIONS RELATING TO THE MEMORY SYSTEM.
------------------------------------------------------------------
00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
APRID *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
700000 * < MICROCODE OPTIONS > * < MICROCODE VERSION NUMBER > *
LH(E) *KLPAG!XADDR!UNSTD* ! ! * ! !TRCKS* ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
* < HARDWARE OPTIONS > * < PROCESSOR SERIAL NUMBER > *
RH(E) *50 HZ!CACHE!CHANL* XADR!MSTR ! * ! ! * ! ! * ! ! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
CONO APR, *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
700200 * ! I/O ! SELECTED FLAGS * < SELECT FLAG > ! * PI LEVEL *
E * !RESET! EN * DIS ! CLR ! SET * SBUS! NXM ! IOPF*MBPAR!C DIR!ADR P*POWER!SWEEP! * 4 ! 2 ! 1 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
CONI APR, *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
700240 * * < ENABLED FLAGS > ! *
LH(E) * ! ! * ! ! * SBUS! NXM ! IOPF*MBPAR!C DIR!ADR P*POWER!SWEEP! * ! ! *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
* !SWEEP! * SBUS! ! I/O * MB !CACHE! ADDR*POWER!SWEEP! INT * PI LEVEL *
RH(E) * ! BUSY! * ! ! * ERR ! NXM ! PGF * PAR ! DIR ! PAR * FAIL! DONE! REQ * 4 ! 2 ! 1 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
00/18 01/19 02/20 03/21 04/22 05/23 06/24 07/25 08/26 09/27 10/28 11/29 12/30 13/31 14/32 15/33 16/34 17/35
RDERA *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
700400 * WORD NO !SWEEP* CHAN! DATA SRC *WRITE! ! PHYSICAL ADDRESS *
LH(E) * ! ! REF * REF ! ! * REF ! JUNK! JUNK* ! ! * ! ! 14 * 15 ! 16 ! 17 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
* < PHYSICAL ADDRESS OF FIRST WORD OF TRANSFER > *
RH(E) * 18 ! 19 ! 20 * 21 ! 22 ! 23 * 24 ! 25 ! 26 * 27 ! 28 ! 29 * 30 ! 31 ! 32 * 33 ! 34 ! 35 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
DATA SRC WRITE = 0 WRITE = 1
00 MEMORY (READ, RPW) CHANNEL (STORE STATUS)
01 CHANNEL (DATA STORE)
10 EBOX STORE FROM AR
11 READ FROM CACHE WRITEBACK FROM CACHE
(PG REFILL OR CHAN READ)
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
CONO PI, *-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
700600 * WRITE EVEN PAR * ! DROP!CLEAR* REQ ! TURN CHAN * TURN SYS ! < SELECT CHANNEL > *
E * ADDR! DATA! DIR * ! INT ! SYS * INT ! ON ! OFF * OFF ! ON ! 1 * 2 ! 3 ! 4 * 5 ! 6 ! 7 *
*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*-----+-----+-----*
[END OF TGHA.DOC]