Trailing-Edge
-
PDP-10 Archives
-
BB-P363B-SM_1985
-
mcb/cex/cexint.m11
There are no other files named cexint.m11 in the archive.
.TITLE CEXINT - Comm/Exec Device Interrupt Handler
.IDENT /003160/
.ENABL LC
;
; COPYRIGHT (c) 1980, 1981, 1982
; DIGITAL EQUIPMENT CORPORATION
; Maynard, Massachusetts
;
; This software is furnished under a license and may be used
; and copied only in accordance with the terms of such license
; and with the inclusion of the above copyright notice. This
; software or any other copies thereof may not be provided or
; otherwise made available to any other person. No title to
; and ownership of the software is hereby transferred.
;
; The information in this software is subject to change
; without notice and should not be construed as a commitment
; by DIGITAL EQUIPMENT CORPORATION.
;
; DIGITAL assumes no responsibility for the use or reliability
; of its software on equipment which is not supplied by
; DIGITAL.
;
;++
; FACILITY: MCB Communications Executive
;
; FUNCTIONAL ABSTRACT:
;
; This module contains the routines to handle processor
; exceptions, device interrupts, and process synchronization
; requests.
;
; ENVIRONMENT: RSX kernel mode with EIS
;
; AUTHOR: Alan D. Peckham, CREATION DATE: 21-MAR-80
;
; MODIFIED BY:
;
; Alan D. Peckham, 8-Jul-80: VERSION 3.0
; 01 - Globalize references to I/O page.
; 02 - Remove LIX requirement from $SYNCH.
; 03 - Add "active SYNCH block" flag support and diagnostic crash.
; 04 - Update CRSH$S contexts.
; 05 - Add processor exception handlers.
; 06 - Have exception routine funnel through INTR in CEXSGE.
; Add power failure handler with check for DTE "magic finger".
; 07 - Rename SS$ODD to SS$NXM.
; 08 - Rename SS$OVR to SS$STK.
; Eliminate direct access to PS.
; Change support for X.PRI in $INTCE.
; 09 - Handle parity errors.
; 10 - Save MMU registers in proper order in $EX250.
; Pop resume address off of stack if CE$SYN error detected.
; Alan D. Peckham, 10-Dec-80: VERSION 3.1
; 11 - Alter input conditions for $SYNCH routine.
; Change interrupt handler to use interrupt priority blocks.
; 12 - Do checking to catch a under-prioritized device.
; 13 - Fix test polarity in deciding a priority violation.
; Add mapped DDM data base support.
; Alan D. Peckham, 30-Jan-80: VERSION 3.2
; 14 - Priority violation test was not fixed in $INTCE.
; Fix offset bug in $EX30, $EX34.
; Support new SYNCH block in $SYNCH.
; 15 - Fix bugs in $EX30, $EX34 to back up PC before fetching instruction.
; Catch RSX in user mode before checking for active CEX in TESTM.
; 16 - Add support for interrupts serviced statistics in $INTCE.
;--
.SBTTL DECLARATIONS
;
; INCLUDE FILES:
;
.MCALL CRSH$S
.GLOBL $DQLM1,$DQLM2,$DRLM1,$DRLM2,$HEADR,$INTX1,$STACK,$STKDP
.GLOBL $EMTRP,$ILINS,$IOTRP,$SGFLT,$TRACE,$TRP04,$TRTRP
.GLOBL KISAR5,SR0,SR1,SR2,V$$CTR,$STOP
;
; MACROS:
;
.MACRO CEXGO$ sts,cnt
CALL CEXG'cnt
sts
.ENDM CEXGO$
.MACRO CEXSV$
.ENDM CEXSV$
.MACRO TESTM adr
JSR R5,TESTM
.WORD adr
.ENDM TESTM
;
; EQUATED SYMBOLS:
;
; None
;
; OWN STORAGE:
;
.GLOBL .DTERG ; Master DTE that can "finger" us.
.GLOBL .INTCB ; Interrupt priority block list.
.GLOBL .INTC4 ; Priority 4 block
.GLOBL .INTC5 ; Priority 5 block
.GLOBL .INTC6 ; Priority 6 block
.GLOBL .INTC7 ; Priority 7 block
;
; VALIDATION DECLARATIONS:
;
.IIF NE,<X.PDB-4>,.ERROR X.PDB; must follow dispatch JSR
.IIF NE,<X.DSP-X.PDB-2>,.ERROR X.DSP; must follow X.PDT word
.SBTTL $EX10 - Illegal Instruction Exception
;++
; FUNCTIONAL DESCRIPTION:
;
; None
;
; CALLING SEQUENCE:
;
; None
;
; INPUT PARAMETERS:
;
; None
;
; IMPLICIT INPUTS:
;
; None
;
; OUTPUT PARAMETERS:
;
; None
;
; IMPLICIT OUTPUTS:
;
; None
;
; CONDITION CODES:
;
; None
;
; SIDE EFFECTS:
;
; None
;--
.PSECT $CODE$,I,RO
$EX10:: TESTM $ILINS ;;; check if RSX should handle it.
CEXSV$ ;;;
CEXGO$ SS$INS,1 ;;;
.SBTTL $EX114 - Parity Error Exception
;++
; FUNCTIONAL DESCRIPTION:
;
; None
;
; CALLING SEQUENCE:
;
; None
;
; INPUT PARAMETERS:
;
; None
;
; IMPLICIT INPUTS:
;
; None
;
; OUTPUT PARAMETERS:
;
; None
;
; IMPLICIT OUTPUTS:
;
; None
;
; CONDITION CODES:
;
; None
;
; SIDE EFFECTS:
;
; None
;--
.PSECT $CODE$,I,RO
$EX114::CEXSV$ ;;;
PUSH$S R0
MOV #$PARTB+2+<15.*2>,R0 ;;;
10$: PUSH$S @-(R0) ;;;
CMP #$PARTB+2,R0 ;;;
BLO 10$ ;;;
MOV <15.*2>(SP),R0 ;;;
MOV @$PARTB+2+<15.*2>,<15.*2>(SP) ;;;
CEXGO$ SS$MPE,21 ;;;
.SBTTL $EX14 - Breakpoint or T-bit Exception
;++
; FUNCTIONAL DESCRIPTION:
;
; None
;
; CALLING SEQUENCE:
;
; None
;
; INPUT PARAMETERS:
;
; None
;
; IMPLICIT INPUTS:
;
; None
;
; OUTPUT PARAMETERS:
;
; None
;
; IMPLICIT OUTPUTS:
;
; None
;
; CONDITION CODES:
;
; None
;
; SIDE EFFECTS:
;
; None
;--
.PSECT $CODE$,I,RO
$EX14:: TESTM $TRACE ;;; check if RSX should handle it.
CEXSV$ ;;;
CEXGO$ SS$BPT,1 ;;;
.SBTTL $EX20 - IOT Instruction Exception
;++
; FUNCTIONAL DESCRIPTION:
;
; None
;
; CALLING SEQUENCE:
;
; None
;
; INPUT PARAMETERS:
;
; None
;
; IMPLICIT INPUTS:
;
; None
;
; OUTPUT PARAMETERS:
;
; None
;
; IMPLICIT OUTPUTS:
;
; None
;
; CONDITION CODES:
;
; None
;
; SIDE EFFECTS:
;
; None
;--
.PSECT $CODE$,I,RO
$EX20:: TESTM $IOTRP ;;; check if RSX should handle it.
CEXSV$ ;;;
CEXGO$ SS$IOT,1 ;;;
.SBTTL $EX24 - Power failure Exception
;++
; FUNCTIONAL DESCRIPTION:
;
; None
;
; CALLING SEQUENCE:
;
; None
;
; INPUT PARAMETERS:
;
; None
;
; IMPLICIT INPUTS:
;
; None
;
; OUTPUT PARAMETERS:
;
; None
;
; IMPLICIT OUTPUTS:
;
; None
;
; CONDITION CODES:
;
; None
;
; SIDE EFFECTS:
;
; None
;--
.PSECT $CODE$,I,RO
$EX24:: CEXSV$ ;;;
PUSH$S @#4 ;;; Save NXM trap address
MOV #80$,@#4 ;;; and set up our own.
TST @.DTERG ;;; If the boot RAM is not there
POP$S @#4 ;;; then
BCS 10$ ;;; we have been fingered.
CEXGO$ SS$PWF,1 ;;;
10$: CEXGO$ SS$DTE,1 ;;;
80$: INC 2(SP) ;;; Set his carry
RTI ;;; and let him continue.
.SBTTL $EX250 - Segment Fault Exception
;++
; FUNCTIONAL DESCRIPTION:
;
; None
;
; CALLING SEQUENCE:
;
; None
;
; INPUT PARAMETERS:
;
; None
;
; IMPLICIT INPUTS:
;
; None
;
; OUTPUT PARAMETERS:
;
; None
;
; IMPLICIT OUTPUTS:
;
; None
;
; CONDITION CODES:
;
; None
;
; SIDE EFFECTS:
;
; None
;--
.PSECT $CODE$,I,RO
$EX250::TESTM $SGFLT ;;;
CEXSV$ ;;;
PUSH$S <@#SR2,@#SR1,@#SR0> ;;;
BIC #160000,@#SR0 ;;; Unfreeze the segment unit.
CEXGO$ SS$MMU,4 ;;;
.SBTTL $EX30 - EMT Instruction Exception
;++
; FUNCTIONAL DESCRIPTION:
;
; None
;
; CALLING SEQUENCE:
;
; None
;
; INPUT PARAMETERS:
;
; None
;
; IMPLICIT INPUTS:
;
; None
;
; OUTPUT PARAMETERS:
;
; None
;
; IMPLICIT OUTPUTS:
;
; None
;
; CONDITION CODES:
;
; None
;
; SIDE EFFECTS:
;
; None
;--
.PSECT $CODE$,I,RO
$EX30:: TESTM $EMTRP ;;; check if RSX should handle it.
CEXSV$ ;;;
MOV (SP),-(SP) ;;; Back up PC
SUB #2,(SP) ;;; to
MFPI @(SP)+ ;;; get EMT instruction,
CLRB 1(SP) ;;; isolate the number,
ASL (SP) ;;; and turn into offset.
CEXGO$ SS$EMT,2 ;;;
.SBTTL $EX34 - TRAP Instruction Exception
;++
; FUNCTIONAL DESCRIPTION:
;
; None
;
; CALLING SEQUENCE:
;
; None
;
; INPUT PARAMETERS:
;
; None
;
; IMPLICIT INPUTS:
;
; None
;
; OUTPUT PARAMETERS:
;
; None
;
; IMPLICIT OUTPUTS:
;
; None
;
; CONDITION CODES:
;
; None
;
; SIDE EFFECTS:
;
; None
;--
.PSECT $CODE$,I,RO
$EX34:: TST .CEXDP ;;; If in RSX
BPL 10$ ;;; then
JMP $TRTRP ;;; let RSX handle it.
10$: CEXSV$ ;;;
MOV (SP),-(SP) ;;; Back up PC
SUB #2,(SP) ;;; to
MFPI @(SP)+ ;;; get TRAP instruction,
CLRB 1(SP) ;;; isolate the number,
ASL (SP) ;;; and turn into offset.
CEXGO$ SS$TRP,2 ;;;
.SBTTL $EX4 - Odd Address or Stack Overflow Exception
;++
; FUNCTIONAL DESCRIPTION:
;
; None
;
; CALLING SEQUENCE:
;
; None
;
; INPUT PARAMETERS:
;
; None
;
; IMPLICIT INPUTS:
;
; None
;
; OUTPUT PARAMETERS:
;
; None
;
; IMPLICIT OUTPUTS:
;
; None
;
; CONDITION CODES:
;
; None
;
; SIDE EFFECTS:
;
; None
;--
.PSECT $CODE$,I,RO
$EX4:: CMP #V$$CTR+4,SP ;;;
BHI 10$ ;;;
TESTM $TRP04 ;;; check if RSX should handle it.
CEXSV$ ;;;
CEXGO$ SS$NXM,1 ;;;
10$: MOV SP,.USRSP ;;; Save SP position
POP$S $STACK-4 ;;; PC
POP$S $STACK-2 ;;; and PS.
MOV #$STACK-4,SP ;;; Set up provisional SP
CEXSV$ ;;; and enter exception mode.
PUSH$S .USRSP ;;;
CEXGO$ SS$STK,2 ;;;
.SBTTL $INTCE - Dispatch an interrupt
;++
; FUNCTIONAL DESCRIPTION:
;
; Transfer an interrupt to a process interrupt handler.
; This is done by:
;
; 1) Doing RSX-related processing and saving context that
; will be modified.
; 2) Recording that an interrupt is being processed.
; 3) Setting device priority, line table address, mapping to
; the process, and dispatching to the handler.
;
; After handler processing, context must be restored and
; control must be passed to RSX for rescheduling.
;
; CALLING SEQUENCE:
;
; JSR R5,$INTCE
; .WORD ^C<priority>
; .WORD <line table address>
; .WORD <mapping bias>
; .WORD <dispatch address>
;
; INPUT PARAMETERS:
;
; None
;
; IMPLICIT INPUTS:
;
; PS = priority 7.
;
; OUTPUT PARAMETERS:
;
; None
;
; IMPLICIT OUTPUTS:
;
; None
;
; CONDITION CODES:
;
; None
;
; SIDE EFFECTS:
;
; None
;--
.PSECT $CODE$,I,RO
$INTCE::DEC @#$STKDP ;;; If switching to system state
BNE 10$ ;;; then
MOV SP,@$HEADR ;;; save current stack position.
.IF NDF,M$$MGE
MOV #$STACK,SP ;;; Load system stack pointer.
.ENDC
10$: PUSH$S #$INTX1 ;;; Set to exit to RSX
CALL $CEXSV ;;; and become the Comm/Exec.
.IF NE,D$$BUG
TST 2(R4) ;;; If priority block already active
BNE 100$ ;;; then make notification.
.IFTF
MOV .INTCB,(R4)+ ;;; Push on priority block,
MOV R4,.INTCB
MOV (R5)+,(R4)+ ;;; set the process descriptor,
INC (R4)+ ;;; (update the interrupt counter)
BNE 20$
DEC -2(R4)
20$: MTPS (R4) ;;; and drop priority.
MOV (R5),R4 ;; Get dispatch address
MOV -(R5),R5 ;; and recover process descriptor.
PUSH$S @#KISAR5 ;; Save
SMAP$S ;; mapping registers,
MOV (R5),@#KISAR5 ;; map to process,
MAP$ Z.DAT+0(R5) ;; map to data base,
MOV Z.DAT+2(R5),R5 ;; get data base address,
CALL (R4) ;; and give him the interrupt.
MAP$S ;; Restore
POP$S @#KISAR5 ;; mapping registers,
MOV .INTCB,R4 ;; remove priority block,
.IFT
CLR (R4)
.IFTF
MOV -(R4),.INTCB
90$: JMP $CEXXT ;; Schedule the Comm/Exec if necessary.
.IFT
100$: CALL 101$ ;;; Make notification
BR 90$ ;;; and drop out.
101$: CRSH$S IPR ;;; Bad interrupt priority.
.ENDC
.SBTTL $INTDS - Inhibit Interrupts for given Priority
;++
; FUNCTIONAL DESCRIPTION:
;
;
;
; CALLING SEQUENCE:
;
; CALL $INTDS
;
; INPUT PARAMETERS:
;
; R0 = address of interrupt vector for device
; to inhibit interrupts from.
;
; IMPLICIT INPUTS:
;
; None
;
; OUTPUT PARAMETERS:
;
; None
;
; IMPLICIT OUTPUTS:
;
; None
;
; CONDITION CODES:
;
; None
;
; SIDE EFFECTS:
;
; None
;--
.PSECT $CODE$,I,RO
$INTDS::PLVL$ ; Crash if not at process level.
MFPS -(SP) ; Get current PS
.IF NE,D$$BUG
.IFTF
MOV (R0),R0
MOV 2(R0),R0
BISB 10(R0),(SP) ; raise to device priority,
MTPS (SP)+
RETURN ; and go away.
.IFT
.ENDC
.SBTTL $INTEN - Allow Interrupts for given Priority
;++
; FUNCTIONAL DESCRIPTION:
;
;
;
; CALLING SEQUENCE:
;
; CALL $INTEN
;
; INPUT PARAMETERS:
;
; R0 = address of interrupt vector for device
; to allow interrupts from.
;
; IMPLICIT INPUTS:
;
; None
;
; OUTPUT PARAMETERS:
;
; None
;
; IMPLICIT OUTPUTS:
;
; None
;
; CONDITION CODES:
;
; None
;
; SIDE EFFECTS:
;
; None
;--
.PSECT $CODE$,I,RO
$INTEN::PLVL$ ; Crash if not at process level.
MFPS -(SP) ; Get current PS
.IF NE,D$$BUG
.IFTF
BICB #7*40,(SP) ; drop priority to 0
MTPS (SP)+
RETURN ; and go away.
.IFT
.ENDC
.SBTTL $SYNCH - Synchronize with process
;++
; FUNCTIONAL DESCRIPTION:
;
; This routine is provided to interrupt handler routines to
; allow them to suspend processing until their associated
; process context can be set up. This is done by saving the
; return address in the provided SYNCH block and scheduling
; it to be run after the current process has completed
; processing.
;
; CALLING SEQUENCE:
;
; CALL $SYNCH
;
; INPUT PARAMETERS:
;
; R4 = address of synch block containing:
; S.DSP = Routine to call on SYNCHronizing.
;
; IMPLICIT INPUTS:
;
; PS = device priority.
;
; OUTPUT PARAMETERS:
;
; None
;
; IMPLICIT OUTPUTS:
;
; None
;
; CONDITION CODES:
;
; None
;
; SIDE EFFECTS:
;
; None
;--
.PSECT $CODE$,I,RO
$SYNCH::ILVL$ ; Crash if not at interrupt level.
.IF NE,D$$BUG
TST S.PDB(R4) ; If SYNCH block is active
BNE 100$ ; then crash about it,
.IFTF
MOV @.INTCB,S.PDB(R4) ; otherwise set PDB
CLR (R4) ; Reset the link pointer.
DSABL$ ; No interrupts, please!
MOV R4,@.SYNQH+2 ;;; Link to last block
MOV R4,.SYNQH+2 ;;; and make this the last block.
ENABL$ ;;; reenable interrupts
INC .CEXRQ ; indicate scheduling requested
RETURN ; and go away.
.IFT
100$: CRSH$S SYN ; and say SYNCH block already active.
.ENDC
.SBTTL CEXSV - Spring an Interrupt SIGNAL
;++
; FUNCTIONAL DESCRIPTION:
;
; None
;
; CALLING SEQUENCE:
;
; None
;
; INPUT PARAMETERS:
;
; None
;
; IMPLICIT INPUTS:
;
; None
;
; OUTPUT PARAMETERS:
;
; None
;
; IMPLICIT OUTPUTS:
;
; None
;
; CONDITION CODES:
;
; None
;
; SIDE EFFECTS:
;
; None
;--
.PSECT $CODE$,I,RO
.IRP n,<1,2,21,3,4>
CEXG'n: PUSH$S <@(SP)+,#n>
JMP CEXGO
.ENDM
CEXGO: CALL $IGNAL ;; Signal the exception,
ASL (SP) ;; remove
ADD (SP)+,SP ;; the parameters
RTT ;; and dismiss the exception.
.SBTTL TESTM - Test if in EXEC Mode
;++
; FUNCTIONAL DESCRIPTION:
;
; None
;
; CALLING SEQUENCE:
;
; None
;
; INPUT PARAMETERS:
;
; None
;
; IMPLICIT INPUTS:
;
; None
;
; OUTPUT PARAMETERS:
;
; None
;
; IMPLICIT OUTPUTS:
;
; None
;
; CONDITION CODES:
;
; None
;
; SIDE EFFECTS:
;
; None
;--
.PSECT $CODE$,I,RO
TESTM: MOV (R5)+,-(SP) ;; PICK UP EXEC TRAP ROUTINE ADDRESS
TST @#$STKDP ;; ALLOW EXEC TO HANDLE TRAP?
BGT 80$ ;; IF GT YES, TRAP WAS IN USER MODE
BLT 70$ ;; IF LT NO, BAD STACK DEPTH
TST .CEXDP ;; If in RSX
BPL 70$ ;; then
CMP 4(SP),#$DRLM1 ;; TRAP OCCUR IN DIRECTIVE DISPATCHER?
BLO 10$ ;; IF LO NO
CMP 4(SP),#$DRLM2 ;; TRAP OCCUR IN DIRECTIVE DISPATCHER?
BLOS 80$ ;; IF LO YES, PASS TRAP TO EXEC
10$: CMP 4(SP),#$DQLM1 ;; TRAP OCCUR IN QIO DIRECTIVE?
BLO 70$ ;; IF LO NO
CMP 4(SP),#$DQLM2 ;; TRAP OCCUR IN QIO DIRECTIVE?
BLOS 80$ ;; IF LOS YES, ALLOW EXEC TO HANDLE TRAP
70$: MOV R5,(SP) ;; SET TO XDT ADDRESS
80$: MOV (SP)+,R5 ;; SET RETURN ADDRESS
RTS R5 ;; PROCESS TRAP
.END