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PDP-10 Archives
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decuslib20-02
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decus/20-0027/line.mac
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TITLE LINE CONTROL
SUBTTL DON WITCRAFT 4-14-66
IFN DCS680,<PASS2
END>
;LINE CONTROL
LNMSK=LN-1 ;MASK FOR LR
LR: 0 ;LINE REGISTER
;LINE REGISTER INSTRUCTIONS
INTERNAL TTINCR,TTCL,TTRL,TTSLC,TTSL,TTI1,TTI,TTO1,TTO,TT
TTINCR: AOS AC0,LR ;INCREMENT LINE REGISTER
ANDI AC0,177 ;MODULO 128
MOVEM AC0,LR
POPJ PDP,
TTCL: SETZM LR ;CLEAR LINE REGISTER
POPJ PDP,
TTRL: MOVE AC,LR ;READ LINE REGISTER
POPJ PDP,
TTSLC: SETZM LR ;CLEAR LINE REGISTER AND
TTSL: ANDI AC,177 ;SET LINE REGISTER
ORM AC,LR
SETZM AC ;CLEAR AC
TT: POPJ PDP,
IFN INLINE,<EXTERNAL FETCHY,STOREY>
IFE INLINE,<IFE PACK,<EXTERNAL FETPNT>
IFN PACK,<EXTERNAL CORE>
EXTERNAL DFF,IF>
TTI1: PUSHJ PDP,TTINCR
TTI: ADDI RUNTIM,^D9 ;INCREMENT RUN TIME
PUSHJ PDP,TTIO ;GET LINE FLAGS
MOVE MA,PC
FETCH ;GET STATUS WORD
TRNE MB,4000 ;STATUS BIT 0=0?
AOJA MB,TTI3 ;NO. INCREMENT STATUS WORD
TTI2: LSH MB,-1 ;YES, SHIFT STATUS RIGHT ONE BIT
PUSHJ PDP,TTIO ;AND READ COMPLEMENT OF LINE
TLNN AC2,LBIT ;STATE INTO BIT 0.
TRC MB,4000
STORE
TTI4: ADDI PC,2 ;SKIP STATUS AND ASSEMBLY WORD
POPJ PDP,
TTI3: STORE ;STORE INCREMENTED STATUS
ANDI MB,7
CAIE MB,4 ;ARE STATUS BITS 9,10,11=4?
JRST TTI4 ;NO
AOS MA ;YES. FETCH ASSEMBLY WORD
FETCH
PUSHJ PDP,TTIO
TRO MB,10000 ;READ LBIT,SET LRWB,CLEAR LWB
TLO AC2,LRWB
TLZ AC2,LWB
MOVEM AC2,LFLAG(AC1)
JRST TTI2
EXTERNAL ROT
TTO1: PUSHJ PDP,TTINCR
TTO: TRZ AC,10000 ;CLEAR LINK
PUSHJ PDP,ROT ;ROTATE OUTPUT BIT INTO LINK
PUSHJ PDP,TTIO
TLZ AC2,LBIT ;READ LINK INTO LBIT
TRNE AC,10000
TLO AC2,LBIT
TLO AC2,LRWB+LWB ;SET LRWB AND LWB
MOVEM AC2,LFLAG(AC1)
POPJ PDP,
TTIO: MOVE AC0,LR ;FETCH LINE BIT BUFFER
MOVE AC1,LTABLE(AC0)
OR FLAGS,DFLAG(AC1)
MOVE AC2,LFLAG(AC1) ;GET LINE FLAGS
POPJ PDP,
;C8 DATA BLOCK
ENTRY C8DATA
C8DATA: EXP ^D1135*4 ;1135 MICROSEC,8 BIT, 110 BAUD
Z
XWD C8ACTI,C8FLG
Z
;C8 IOTS
INTERNAL TT8ON,T8SKP,TT8OFF
TT8ON: TRZ FLAGS,C8FLG ;CLEAR CLOCK FLAG
TLO FLAGS,C8ACTIV ;ACTIVATE C8
POPJ PDP,
T8SKP: TRNE FLAGS,C8FLG ;CLOCK FLAG ON?
AOS PC ;YES
POPJ PDP,
TT8OFF: TLZA FLAGS,C8ACTIV
TT5OFF: TLZA FLAGS,C5ACTIV
TRZA FLAGS,C8FLG
TRZ FLAGS,C5FLG
POPJ PDP,
;C5 DATA BLOCK
ENTRY C5DATA
C5DATA: EXP ^D2500*4 ;2500 MICROSECS,5 BIT,55 BAUD
Z
XWD C5ACTIV,C5FLG
Z
;C5 IOTS
INTERNAL TT5ON,T5SKP,TT5OFF
TT5ON: TRZ FLAGS,C5FLG
TLO FLAGS,C5ACTIV
POPJ PDP,
T5SKP: TRNE FLAGS,C5FLG
AOS PC
POPJ PDP,
;680 LINE SIMULATION DEVICE CONTROL
;PHYSICAL CHARACTERISTICS
;EACH LINE OF THE 680 HAS A LINE BIT REGISTER, LBIT,
;WHICH HOLDS THE LINE VALUE DURING ONE BAUD TIME. IF NO
;INPUT OCCURS, LBIT=1; OTHERWISE, IT HAS THE VALUE OF THE BIT.
;THE TTI IOT HAS AN ASSOCIATED STATUS WORD AND ASSEMBLY WORD
;IN THE TWO LOCATIONS FOLLOWING THE TTI.
; X/ TTI
; X+1/ STATUS WORD
; X+2/ ASSEMBLY WORD
;IF BIT 0 OF THE STATUS WORD IS 0, THE STATUS IS SHIFTED RIGHT
;ONE BIT AND THE COMPLEMENT OF LBIT IS READ INTO BIT 0.
;IF BIT 0 OF THE STATUS IS 1, THE STATUS IS INCREMENTED
;MODULO 8. THEN, IF BITS 9, 10, AND 11 ARE =4, THE ASSEMBLY
;WORD IS READ, SHIFTED RIGHT 1 AND LBIT IS READ INTO BIT 0.
;OTHERWISE, NO-OP.
;THE TTO CLEARS THE LINK, ROTATES AC RIGHT 1 AND READS THE
;LINK INTO LBIT.
;SIMULATION
;EACH SIMULATED LINE HAS THREE DATA BLOCKS; L'N'DATA,LI'N'CD,
;AND LO'N'CD. THE LATTER TWO ARE STANDARD FILE DATA BLOCKS
;FOR INPUT AND OUTPUT RESPECTIVELY.
;THE FORMAT OF L'N'DATA IS
;DRATE: EXP BIT TIME IN QUARTER MICROSECONDS
;DTIME: Z
;DFLAG: XWD L'N'ACTI,0 ;LINES ARE ACTIVATED BY A TTI
; ;OR A TTO. ONCE ACTIVATED THEY
; ;RUN FREE. LINES ARE DISABLED BY
; ;CLEARING DFLAG. PRIOR TO RUNNING
; ;A PROGRAM WITH TTI OR TTO
; ;INSTRUCTIONS, SETUP LI'N'CD AND
; ;LO'N'CD AS FOR OTHER DEVICES.
;DDISP: EXP LTC ;DISPATCH LOCATION AT INTERRUPT TIME
;LIASS: Z ;LINE INPUT ASSEMBLY REGISTER
; ;A CHARACTER IS FETCHED FROM THE
; ;INPUT BUFFER, START/STOP BITS
; ;ARE ADDED (AS PER RH OF LFLAG)
; ;AND THIS CHARACTER IS LEFT JUSTIFIED
; ;IN LIASS.
;LOASS: Z ;LINE OUTPUT IS ASSEMBLED
; ;RIGHT JUSTIFIED HERE. START/STOP
; ;BITS ARE STRIPPED BEFORE STORING.
;LFLAG: EXP 3001 ;FOR 110 BAUD LINES. TWO START,
; ;8 INFORMATION BITS, 1 STOP BIT.
; LEFT HALF BITS:
LBIT=400000 ;LINE BUFFER REGISTER
LRWB=200000 ;A READ OR WRER.
TRO FLAGS,BRQFLG ;PUT IN BREAK REQUEST
POPJ PDP,
DRMXF3: TLOE FLAGS,DFBCHG ;HAS DFB BEEN EMPTIED YET?
TRO FLAGS,DREFLG+DRMDTE ;NO. TIMING ERROR.
LDB AC0,SECTOR(AC3)
MOVEM AC0,DFB
JRST DRMXF4
DRMDON: TRO FLAGS,DRCFLG ;SET DRUM COMPLETION FLAG
TRNN FLAGS,DRWC ;WRITING?
JRST DRMDO1 ;NO
PUSHJ PDP,DMOUT0 ;YES. WRITE INCORE BLOCK
TRNE AC0,IODERR ;PARITY ERROR?
TRO FLAGS,DREFLG+DRMPER ;YES
DRMDO1: TLZ FLAGS,DACTIV+DFBCHG ;DEACTIVATE DRUM
TRNE FLAGS,DREFLG ;ERROR FLAG ON?
POPJ PDP, ;YES
AOS DAR ;AND INCREMENT DAR.
POPJ PDP,
END