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;DCKAD
SEQ 0001
IDENTIFICATION
--------------
PRODUCT CODE: AH-?????-DD
DIAGNOSTIC CODE: DCKAD
PRODUCT NAME: DFKADB0 PDP10 KL10 BASIC INSTRUCTION
DIAGNOSTIC #4
VERSION: 0.2
DATE RELEASED: SEPT 1984
MAINTAINED BY: DIAGNOSTIC ENGINEERING
AUTHOR: JOHN A. KIRCHOFF
COPYRIGHT (C) 1975, 1984
DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASS.
THIS SOFTWARE IS FURNISHED UNDER A LICENSE FOR USE ONLY ON A
SINGLE COMPUTER SYSTEM AND MAY BE COPIED ONLY WITH THE INCLUSION
OF THE ABOVE COPYRIGHT NOTICE. THIS SOFTWARE, OR ANY OTHER
COPIES THEREOF, MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE
TO ANY OTHER PERSON EXCEPT FOR USE ON SUCH SYSTEM AND TO ONE WHO
AGREES TO THESE LICENSE TERMS. TITLE TO AND OWNERSHIP OF THE
SOFTWARE SHALL AT ALL TIMES REMAIN IN DIGITAL EQUIPMENT
CORPORATION.
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT
NOTICE AND SHOULD NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL
EQUIPMENT CORPORATION.
DIGITAL EQUIPMENT CORPORATION ASSUMES NO RESPONSIBILITY FOR THE
USE OR RELIABILITY OF ITS SOFTWARE IN EQUIPMENT WHICH IS NOT
SUPPLIED BY DIGITAL EQUIPMENT CORPORATION.
MAINDEC-10-DCKAD.TXT
PAGE 2 SEQ 0002
TABLE OF CONTENTS
-----------------
1.0 ABSTRACT
2.0 REQUIREMENTS
2.1 EQUIPMENT
2.2 STORAGE
2.3 PRELIMINARY PROGRAMS
3.0 PROGRAM PROCEDURES
3.1 LOADING PROCEDURE
3.2 STARTING PROCEDURE
3.3 OPERATING PROCEDURE
4.0 ERRORS
5.0 ITERATION COUNTER
6.0 CYCLE TIME
7.0 OPERATIONAL VARIATIONS
8.0 MISCELLANEOUS
9.0 LISTING
MAINDEC-10-DCKAD.TXT
PAGE 3 SEQ 0003
1.0 ABSTRACT
THIS DECSYSTEM KL10 BASIC INSTRUCTION DIAGNOSTIC IS
THE FOURTH IN A SERIES OF DECSYSTEM KL10 PROCESSOR
DIAGNOSTICS. THE DIAGNOSTIC TESTS INDEXED ADDRESSING,
INDIRECT ADDRESSING, INDEXED-INDIRECT ADDRESSING AND
ARITHMETIC FLAGS TESTS. THE DIAGNOSTIC ALSO PERFORMS
TESTS OF THE FOLLOWING INSTRUCTIONS: EXCH,MOVEM,JFCL,
ADDI,CAI, JRST,JSP, AOBJN, AOBJP,AOS, SOS,JUMPL, JUMPE,
JUMPN,JUMPG,AOJ,SOJ, ADDM,HRREM,MOVSM, XORM,ADDB,HLLOS,
MOVSS,HRLM,HRRS,HRRZM,SETZB,SETAB,XCT.
THE DIAGNOSTIC TESTS THE BASIC FUNCTIONALITY OF THE
PROCESSO R AND MICRO-CODE.
2.0 REQUIREMENTS
2.1 EQUIPMENT
A KL10 WITH A MINIMUM OF 32K OF MEMORY.
CONSOLE TELETYPE.
2.2 STORAGE
THE PROGRAM RUNS WITHIN 128K OF MEMORY.
2.3 PRELIMINARY PROGRAMS
CONSOLE FUNCTIONS WORKING PROPERLY.
PREVIOUS PROCESSOR DIAGNOSTICS.
MAINDEC-10-DCKAD.TXT
PAGE 4 SEQ 0004
3.0 PROGRAM PROCEDURES
3.1 LOADING PROCEDURE
LOAD VIA APPROPRIATE LOADING PROCEDURES.
3.2 STARTING PROCEDURE
STAND-ALONE STARTING ADDRESS IS 40000.
IF THE DIAGNOSTIC FAILS TO START CORRECTLY TRY STARTING AT THE
FIRST TEST INSTEAD OF AT THE BEGINNING OF THE CONTROL SEQUENCE.
(SEE LISTING).
3.3 OPERATING PROCEDURE
ONCE STARTED THE PROGRAM WILL CYCLE CONTINUALLY UNTIL STOPPED
OR AN ERROR OCCURS.
4.0 ERRORS
ERRORS ARE IN THE FORM OF HALT INSTRUCTIONS. THE LISTING
SHOULD BE CONSULTED TO DETERMINE THE CAUSE OF THE ERROR. A
NO OPERATION (JUMP) INSTRUCTION FOLLOWS EACH HALT. THIS
MAY BE USEFUL IN CONSTRUCTING A SCOPE LOOP TO CYCLE ON THE
FAILING INSTRUCTION.
5.0 ITERATION COUNTER
THE ITERATION COUNT OF THE PROGRAM CAN BE DETERMINED BY
EXAMINING LOCATION "PASCNT".
6.0 CYCLE TIME
THE CYCLE TIME OF THE PROGRAM IS IN THE MILLISECOND RANGE AND
IS THEREFORE SUITABLE FOR TAKING MARGINS, VIBRATION TESTS, ETC.
MAINDEC-10-DCKAD.TXT
PAGE 5 SEQ 0005
7.0 OPERATIONAL VARIATIONS
A. DIAGNOSTIC MONITOR
THE PROGRAM IS USABLE WITH THE DIAGNOSTIC MONITOR TO PROVIDE
RELIABILITY TESTS, ACCEPTANCE TESTS, AND / OR TO PROVIDE A
QUICK METHOD OF ISOLATION OF A FAULT TO A PARTICULAR AREA OF
THE PROCESSOR. CERTAIN PROCEDURES ARE USED WHEN THE PROGRAM
IS USED IN THIS MANNER. THEY ARE:
1. THE DIAGNOSTIC MONITOR TRANSFERS CONTROL TO THE PROGRAM
AND STARTS IT AT LOCATION 40002.
2. MONCTL - LOCATION 40064 IS USED AS THE DIAGNOSTIC
MONITOR CONTROL FLAG WORD.
B. USER MODE
THE PROGRAM WILL OPERATE IN USER MODE AND AS SUCH PROVIDES
ASSURANCE THAT THE PROCESSOR IS PERFORMING ALL FUNCTIONS
CORRECTLY. USER MODE STARTING ADDRESS IS 40000.
C. SYSTEM EXERCISER
STARTING ADDRESS IS 40003. NO DATA SWITCHES ARE USED BY
THIS PROGRAM.
8.0 MISCELLANEOUS
NONE
9.0 LISTING
HISTORY FILE FOR DCKAD SEQ 0006
----------------------
---------------------------------------------------------------
CODE: MAINDEC-10-DCKAD
TITLE: DECSYSTEM KC10 BASIC INSTRUCTION DIAGNOSTIC (4)
VERSION: 0.2
DATE: August 1982
REASON: Reassembled for changes to SPCCPU.KCM
---------------------------------------------------------------
CODE: MAINDEC-10-DCKAD
TITLE: DECSYSTEM KC10 BASIC INSTRUCTION DIAGNOSTIC (4)
VERSION: 0.1
DATE: March 1982
REASON: ORIGINAL RELEASE OF THIS PROGRAM FOR KC10.
NOTE: THIS PROGRAM WAS ADAPTED FROM 'DSKAD' -
AN ANALOGOUS PROGRAM FOR THE DECSYSTEM
2020 KS-10.
---------------------------------------------------------------
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 1
DFKADT MAC 2-Oct-84 09:47 *PARAM* CONSOLE DATA SWITCH ASSIGNMENTS, SEPT 18,1979 SEQ 0007
1 ;DFKAD
2
3 000000 MCNVER==0
4 000002 DECVER==2
5
6 XLIST
7 LIST
8 LALL
9
10 NAME \MCNVER,\DECVER^
11
12 TITLE DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2
13 ^
14
15 ;BYTE, BLOCK TRANSFER, JFFO AND OTHER BASIC MISCELLANEOUS INSTRUCTIONS
16
17 ;COPYRIGHT 1984
18 ;DIGITAL EQUIPMENT CORPORATION
19 ;MARLBORO, MASS. 01752
20
21 ;J. Kirchoff
22
23 000137 LOC 137
24 000137 000000 000002 MCNVER,,DECVER
25
26 NOSYM
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 2
DFKADT MAC 2-Oct-84 09:47 DIAGNOSTIC PARAMETERS SEQ 0008
27 SUBTTL DIAGNOSTIC PARAMETERS
28
29 ;Parameter definitions
30 000040 DEBUG=40
31 000001 EXCASB==1
32 000001 USRASB==1
33 000001 KI10=1
34 000001 KL10=1
35 000001 KL10PO=1
36 000001 PGMEND==1
37 000001 ERDIAG=1
38 000000 MEMMAP==0
39
40
41 ;SPECIAL FEATURE DEFINATIONS
42
43 030000 SADR1=BEGIN
44 030000 SADR2=BEGIN
45 030000 SADR3=BEGIN
46 030000 SADR4=BEGIN
47 254000 030000 SADR5=JRST BEGIN
48 254000 030000 SADR6=JRST BEGIN
49 254000 030000 SADR7=JRST BEGIN
50 254000 030000 SADR8=JRST BEGIN
51 254000 030000 SADR9=JRST BEGIN
52 254000 030000 SADR10=JRST BEGIN
53 254000 030000 SADR11=JRST BEGIN
54
55
56 ;SPECIAL FEATURE PARAMETERS
57
58 000000 PAREA0=0
59 000000 PAREA1=0
60 000000 PAREA2=0
61 444653 414400 PAREA3=SIXBIT/DFKAD/
62 546064 000000 PAREA4=SIXBIT/LPT/
63 000000 PAREA5=0
64 000000 PAREA6=0
65 001000 ITERAT==1000
66
67 ;Macros
68
69 ; Stop - used for scope loop, if instruction fails, change (jumpa .+1)
70 ; To a (jumpa .-x) to cycle on failing instruction
71
72 DEFINE STOP (A)<
73 HALT .+1 ;Test failed if program halts here
74 JUMPA .+1 ;To loop change this instruction>
75
76 ; Sflag - used to clear all flags then to set selected flag
77
78 DEFINE SFLAG (A)<
79 MOVSI 1,A
80 JFCL 17,.+1 ;Reset all flags
81 JRST 2,.+1(1) ;Set a flag>
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 1
PARAM KLM 18-Sep-79 17:16 *PARAM* CONSOLE DATA SWITCH ASSIGNMENTS, SEPT 18,1979 SEQ 0009
82 SUBTTL *PARAM* CONSOLE DATA SWITCH ASSIGNMENTS, SEPT 18,1979
83
84 DEFINE S,<; *********************************************************************>
85
86 ; **********************************************************************
87 ;*DATA SWITCHES (READ FROM CONSOLE IN EXEC MODE OR TYPED IN IN USER MODE)
88 ;*LEFT HALF SWITCHES ARE PRE-ASSIGNED FOR SUBROUTINE PACKAGE USE
89 ;*AND CONTROL LOOPING, PRINTING (TTY OR OTHER DEVICE) AND MISC. FUNCTIONS
90 ; **********************************************************************
91
92 400000 ABORT== 400000 ;ABORT PROGRAM ON PASS COMPLETION
93 200000 RSTART==200000 ;RESTART TEST, PRINT TOTALS
94 100000 TOTALS==100000 ;PRINT TOTALS, CONTINUE
95
96 040000 NOPNT== 040000 ;INHIBIT ALL PRINT/TYPE OUT (EXCEPT FORCED)
97 020000 PNTLPT==020000 ;PRINT ALL DATA ON LPT (LOGICAL DEVICE, USER MODE)
98 010000 DING== 010000 ;RING BELL ON ERROR
99
100 004000 LOOPER==004000 ;ENTER EXERCISE/CHECK LOOP ON ERROR
101 002000 ERSTOP==002000 ;HALT ON TEST ERROR
102 001000 PALERS==001000 ;PRINT ALL ERRORS
103
104 000400 RELIAB==000400 ;RELIABILITY MODE
105 000200 TXTINH==000200 ;INHIBIT ERROR TEXT
106 000100 INHPAG==000100 ;INHIBIT PAGING
107
108 000040 MODDVC==000040 ;MODIFY DEVICE CODE
109 000020 INHCSH==000020 ;INHIBIT CACHE
110 000010 OPRSEL==000010 ;OPERATOR SELECTION
111
112 000004 CHAIN== 000004 ;CHAIN CONTROL SWITCH
113
114 000002 KAHZ50==000002 ;KA10 50 HERTZ POWER
115
116 ;SWITCH 17 RESERVED !!!
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 2
PARAM KLM 18-Sep-79 17:16 *PARAM* PROGRAM/SUBROUTINE PARAMETERS, SEPT 18,1979 SEQ 0010
117 SUBTTL *PARAM* PROGRAM/SUBROUTINE PARAMETERS, SEPT 18,1979
118
119 ; **********************************************************************
120 ;*SPECIAL SUBPROGRAM LINKAGES
121 ; **********************************************************************
122
123 027772 FSELNK= 27772 ;FILE SELECT LINK
124 027773 FRDLNK= 27773 ;FILE READ LINK
125 027774 LDLNK= 27774 ;LOAD LINKAGE ADDRESS
126 027775 DDTLNK= 27775 ;DDT LINKAGE ADDRESS
127 027776 MODLNK= 27776 ;OPERATIONAL MODE CHECK LINKAGE ADDRESS
128 027777 SUBLNK= 27777 ;SUBROUTINE LINKAGE ADDRESS
129
130 ; **********************************************************************
131 ;*SPECIAL SUBROUTINE FATAL HALTS
132 ;*USED TO REPORT ERRORS THAT CAUSE THE SUBROUTINES TO BE UNUSABLE
133 ; **********************************************************************
134
135 ;ADDRESS TAG REASON
136 ;---------------------
137
138 ; 1010 NOEXEC ;PROGRAM NOT CODED FOR EXEC MODE OPERATION
139 ; 1011 PLERR ;FATAL PUSH LIST POINTER ERROR
140 ; 1012 PLERR1 ;INITIAL PUSH LIST POINTER ERROR
141 ; 1013 MUOERR ;MUUO WITH LUUO HANDLER WIPED OUT
142 ; 1014 DTEBER ;DTE20 INTERRUPT WITHOUT DOORBELL
143 ; 1015 DTECER ;DTE20 CLOCK INTERRUPT WITHOUT FLAG SET
144 ; 1016 CPIERR ;CPU INITIALIZATION ERROR
145 ; 1017 EOPERR ;END OF PROGRAM ERROR
146 ; 1020 LUOERR ;INTERRUPT WITH LUUO HANDLER WIPED OUT
147
148 ; **********************************************************************
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 3
PARAM KLM 18-Sep-79 17:16 *PARAM* PROGRAM/SUBROUTINE PARAMETERS, SEPT 18,1979 SEQ 0011
149 ; **********************************************************************
150 ;OPERATOR DEFINITIONS (NON-UUO'S)
151 ; **********************************************************************
152
153 260740 000000 OPDEF GO [PUSHJ P,] ;SUBROUTINE CALL
154 263740 000000 OPDEF RTN [POPJ P,] ;SUBROUTINE RETURN
155 261740 000000 OPDEF PUT [PUSH P,] ;PUT DATA ON PUSH LIST
156 262740 000000 OPDEF GET [POP P,] ;GET DATA FROM PUSH LIST
157 254000 000000 OPDEF PJRST [JRST ] ;JRST TO ROUTINE THAT RTN'S
158 254200 000000 OPDEF HALT [JRST 4,] ;DEFINITION FOR DDT
159 254100 000000 OPDEF JRSTF [JRST 2,] ;DEFINITION FOR DDT
160 254500 000000 OPDEF JEN [JRST 12,] ;DEFINITION FOR DDT
161
162 ; **********************************************************************
163 ;SUBROUTINE INITIALIZATION CALL
164 ; **********************************************************************
165
166 265000 030011 OPDEF PGMINT [JSP 0,SBINIT] ;SUBROUTINE INITIALIZATION
167
168 ; **********************************************************************
169 ;HALTING UUO'S (A MORE GRACEFUL HALT THAN SIMPLY USING THE HALT INSTRUCTION).
170 ; **********************************************************************
171
172 037640 000004 OPDEF FATAL [37B8!15B12!4] ;FATAL PROGRAMMING HALT
173 037600 000004 OPDEF ERRHLT [37B8!14B12!4] ;PROGRAM ERROR HALT
174
175 ; **********************************************************************
176 ;TERMINAL INPUT UUO'S
177 ;ALWAYS COME FROM THE CONSOLE TERMINAL IN EXEC MODE OR THE
178 ;CONTROLLING TERMINAL (REAL TERMINAL OR PTY) IN USER MODE.
179 ; **********************************************************************
180
181 037000 000003 OPDEF TTICHR [37B8!0B12!3] ;TTY, INPUT ANY CHARACTER
182 037040 000003 OPDEF TTIYES [37B8!1B12!3] ;TTY, NORMAL RETURN Y
183 037100 000003 OPDEF TTINO [37B8!2B12!3] ;TTY, NORMAL RETURN N
184 037140 000003 OPDEF TTIOCT [37B8!3B12!3] ;TTY, INPUT OCTAL WORD
185 037200 000003 OPDEF TTIDEC [37B8!4B12!3] ;TTY, INPUT DECIMAL WORD
186 037240 000003 OPDEF TTICNV [37B8!5B12!3] ;TTY, INPUT CONVERTABLE WORD
187 037300 000003 OPDEF TTLOOK [37B8!6B12!3] ;TTY, KEYBOARD CHECK
188 037340 000003 OPDEF TTALTM [37B8!7B12!3] ;TTY, ALT-MODE CHECK
189 037400 000003 OPDEF TTSIXB [37B8!10B12!3] ;TTY, INPUT SIXBIT WORD
190 037440 000003 OPDEF TTYINP [37B8!11B12!3] ;TTY, IMAGE MODE INPUT
191 037500 000003 OPDEF TTICLR [37B8!12B12!3] ;TTY, CLEAR INPUT
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 4
PARAM KLM 18-Sep-79 17:16 *PARAM* PROGRAM/SUBROUTINE PARAMETERS, SEPT 18,1979 SEQ 0012
192 ;TERMINAL OUTPUT UUO'S.
193
194 037000 000000 OPDEF PNTA [37B8!0B12!0] ;PRINT ASCII WORD
195 037000 000001 OPDEF PNTAF [37B8!0B12!1] ;PRINT ASCII WORD FORCED
196 037740 000000 OPDEF PNTAL [37B8!17B12!0] ;PRINT ASCIZ LINE
197 037740 000001 OPDEF PNTALF [37B8!17B12!1] ;PRINT ASCIZ LINE FORCED
198 037600 000003 OPDEF PSIXL [37B8!14B12!3] ;PRINT SIXBIT'Z LINE
199 037640 000003 OPDEF PSIXLF [37B8!15B12!3] ;PRINT SIXBIT'Z LINE FORCED
200 037000 000000 OPDEF PNTMSG [37B8!0B12!0] ;PRINT MESSAGE IMMEDIATE
201 037040 000000 OPDEF PNTMSF [37B8!1B12!0] ;PRINT MESSAGE IMMEDIATE FORCED
202 037100 000000 OPDEF PSIXM [37B8!2B12!0] ;PRINT SIXBIT'Z MSG IMMEDIATE
203 037200 000000 OPDEF PSIXMF [37B8!4B12!0] ;PRINT SIXBIT'Z MSG IMM FORCED
204 037000 000000 OPDEF PNTCI [37B8!0B12!0] ;PRINT CHARACTER IMMEDIATE
205 037040 000000 OPDEF PNTCIF [37B8!1B12!0] ;PRINT CHARACTER IMMEDIATE FORCED
206 037500 000000 OPDEF PNTCHR [37B8!12B12!0] ;PRINT CHARACTER
207 037500 000001 OPDEF PNTCHF [37B8!12B12!1] ;PRINT CHARACTER FORCED
208 037040 000000 OPDEF PNT1 [37B8!1B12!0] ;PRINT ONE OCTAL DIGIT
209 037040 000001 OPDEF PNT1F [37B8!1B12!1] ;PRINT 1 OCTAL DIGIT FORCED
210 037100 000000 OPDEF PNT2 [37B8!2B12!0] ;PRINT TWO OCTAL DIGITS
211 037100 000001 OPDEF PNT2F [37B8!2B12!1] ;PRINT 2 OCTAL DIGITS FORCED
212 037140 000000 OPDEF PNT3 [37B8!3B12!0] ;PRINT THREE OCTAL DIGITS
213 037140 000001 OPDEF PNT3F [37B8!3B12!1] ;PRINT THREE OCTAL DIGITS FORCED
214 037200 000000 OPDEF PNT4 [37B8!4B12!0] ;PRINT FOUR OCTAL DIGITS
215 037200 000001 OPDEF PNT4F [37B8!4B12!1] ;PRINT FOUR OCTAL DIGITS FORCED
216 037240 000000 OPDEF PNT5 [37B8!5B12!0] ;PRINT FIVE OCTAL DIGITS
217 037240 000001 OPDEF PNT5F [37B8!5B12!1] ;PRINT FIVE OCTAL DIGITS FORCED
218 037300 000000 OPDEF PNT6 [37B8!6B12!0] ;PRINT SIX OCTAL DIGITS
219 037300 000001 OPDEF PNT6F [37B8!6B12!1] ;PRINT SIX OCTAL DIGITS FORCED
220 037340 000000 OPDEF PNT7 [37B8!7B12!0] ;PRINT 7 OCTAL DIGITS
221 037340 000001 OPDEF PNT7F [37B8!7B12!1] ;PRINT 7 OCTAL DIGITS FORCED
222 037440 000000 OPDEF PNT11 [37B8!11B12!0] ;PRINT 11 OCTAL DIGITS
223 037440 000001 OPDEF PNT11F [37B8!11B12!1] ;PRINT 11 OCTAL DIGITS FORCED.
224 037400 000000 OPDEF PNTADR [37B8!10B12!0] ;PRINT PHYSICAL ADDRESS
225 037400 000001 OPDEF PNTADF [37B8!10B12!1] ;PRINT PHYSICAL ADDRESS FORCED
226 037600 000000 OPDEF PNTOCT [37B8!14B12!0] ;PRINT FULL WORD OCTAL
227 037600 000001 OPDEF PNTOTF [37B8!14B12!1] ;PRINT FULL WORD OCTAL FORCED
228 037540 000000 OPDEF PNTHW [37B8!13B12!0] ;PRINT OCTAL HALF WORDS, 6 SP 6
229 037540 000001 OPDEF PNTHWF [37B8!13B12!1] ;PRINT OCTAL HALF WORDS, 6 SP 6 FORCED
230 037700 000003 OPDEF PNTOCS [37B8!16B12!3] ;PRINT OCTAL, SUPPRESS LEADING 0'S
231 037740 000003 OPDEF PNTOCF [37B8!17B12!3] ;PRINT OCTAL, SUPPRESS LEADING 0'S FORCED
232 037640 000000 OPDEF PNTDEC [37B8!15B12!0] ;PRINT DECIMAL, SUPRESS LEADING 0'S
233 037640 000001 OPDEF PNTDCF [37B8!15B12!1] ;PRINT DECIMAL, SUPRESS LEADING 0'S FORCED
234 037700 000000 OPDEF PNTDS [37B8!16B12!0] ;PRINT DECIMAL, SPACES FOR LD 0'S
235 037700 000001 OPDEF PNTDSF [37B8!16B12!1] ;PRINT DECIMAL, SPACES FOR LD 0'S FORCED
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 5
PARAM KLM 18-Sep-79 17:16 *PARAM* PROGRAM/SUBROUTINE PARAMETERS, SEPT 18,1979 SEQ 0013
236 037200 000002 OPDEF PNTNM [37B8!4B12!2] ;PRINT PROGRAM NAME
237 037000 000002 OPDEF PNTSIX [37B8!0B12!2] ;PRINT SIXBIT WORD
238 037040 000002 OPDEF PNTSXF [37B8!1B12!2] ;PRINT SIXBIT WORD FORCED
239 037240 000002 OPDEF DROPDV [37B8!5B12!2] ;CLOSE LOGICAL FILE, USER MODE
240 037100 000002 OPDEF PNTCW [37B8!2B12!2] ;PRINT DF10 CONTROL WORD
241 037140 000002 OPDEF PNTCWF [37B8!3B12!2] ;PRINT DF10 CONTROL WORD FORCED
242 037000 030242 OPDEF PCRL [37B8!0B12!CRLF] ;PRINT CARRIAGE RETURN/LINE FEED
243 037040 030242 OPDEF PCRLF [37B8!1B12!CRLF] ;PRINT CARRIAGE RETURN/LINE FEED FORCED
244 037000 000040 OPDEF PSP [37B8!0B12!40] ;PRINT SPACE
245 037040 000040 OPDEF PSPF [37B8!1B12!40] ;PRINT SPACE FORCED
246 037000 030243 OPDEF PCRL2 [37B8!0B12!CRLF2] ;PRINT CARRIAGE RETURN/LINE FEED (TWICE)
247 037040 030243 OPDEF PCRL2F [37B8!1B12!CRLF2] ;PRINT CARRIAGE RETURN/LINE FEED (TWICE) FORCED
248 037040 000007 OPDEF PBELL [37B8!1B12!7] ;PRINT TTY BELL
249
250 037040 000026 OPDEF PFORCE [37B8!1B12!26] ;PRINT FORCE, CONTROL O OVERRIDE
251
252 DEFINE PMSG (ARG),<
253 PSIXM [SIXBIT\ARG'_\]>
254
255 DEFINE PMSGF (ARG),<
256 PSIXMF [SIXBIT\ARG'_\]>
257
258 ;SIXBTZ -- MACRO TO GENERATE SIXBIT DATA FOR PRINTING
259 ; CONSERVES CORE OVER ASCIZ
260
261 DEFINE SIXBTZ (ARG),< [SIXBIT\ARG'_\]>
262
263 ;CONSOLE SWITCH INPUT UUO.
264 ;READS CONSOLE SWITCHES IF IN EXEC MODE OR ASKS FOR THEM IF
265 ; USER MODE.
266
267 037400 000002 OPDEF SWITCH [37B8!10B12!2] ;INPUT CONSOLE SWITCHES
268
269 ;CLOCK INITIALIZATION UUO - TO SET DESIRED CLOCK OPERATION
270 ;EITHER IGNORE CLOCK, ONLY LET IT TICK OR CAUSE INTERRUPT TO OCCUR.
271
272 037540 000004 OPDEF CLOKOP [37B8!13B12!4] ;CLOCK OPERATION UUO - PDP-11 CLOCK
273 037200 000004 OPDEF MTROP [37B8!4B12!4] ;CLOCK OPERATION UUO - DK20 METER
274
275 ;KL10 ONLY CACHE OPERATION UUO'S
276
277 037040 000004 OPDEF CINVAL [37B8!1B12!4] ;CACHE INVALIDATE
278 037100 000004 OPDEF CFLUSH [37B8!2B12!4] ;CACHE FLUSH
279 037140 000004 OPDEF CWRTBI [37B8!3B12!4] ;CACHE WRITE-BACK & INVALIDATE
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 6
PARAM KLM 18-Sep-79 17:16 *PARAM* PROGRAM/SUBROUTINE PARAMETERS, SEPT 18,1979 SEQ 0014
280 ;END OF PASS/PROGRAM UUOS
281
282 ;PERFORMS THE END OF PASS FUNCTIONS. INCREMENT PASS COUNT,
283 ;DECREMENT ITERATION COUNT, CHECK IF FINISHED WITH THIS PROGRAM ETC.
284
285 037500 000004 OPDEF ENDUUO [37B8!12B12!4] ;UUO TO DISPLAY LIGHTS
286 037700 000004 OPDEF EOPUUO [37B8!16B12!4] ;END OF PROGRAM UUO
287
288 ;MEMORY MANAGEMENT UUO'S
289 ;UUO'S TO PERFORM VARIOUS MEMORY FUNCTIONS. MAPPING, ZEROING, PAGING,
290 ;ADDRESS CONVERSION, ETC...
291
292 037000 000004 OPDEF MAPMEM [37B8!0B12!4] ;MAP MEMORY
293 037500 000002 OPDEF MEMZRO [37B8!12B12!2] ;ZERO MEMORY
294 037440 000002 OPDEF MEMSEG [37B8!11B12!2] ;SETUP MEMORY SEGMENT
295 037540 000002 OPDEF MAPADR [37B8!13B12!2] ;VIRTUAL TO PHYSICAL ADR CONVERT
296 037640 000002 OPDEF MAPCNK [37B8!15B12!2] ;MAP MEMORY CHUNK
297 037600 000002 OPDEF MAPSET [37B8!14B12!2] ;SET KI10 EXEC PAGE MAP
298 037740 000002 OPDEF MAPPNT [37B8!17B12!2] ;PRINT MEMORY MAP
299
300 ;DEVICE CODE MODIFICATION UUO
301 ;ALLOWS THE MODIFICATION OF IOT'S TO ONE DEVICE TO BE CHANGED TO
302 ;IOT'S TO A DIFFERENT DEVICE CODE.
303
304 037340 000002 OPDEF MODPCU [37B8!7B12!2] ;MODIFY PERHIPERAL CODE, USER
305 037300 000002 OPDEF MODPCP [37B8!6B12!2] ;MODIFY PERHIPERAL CODE, PROGRAM
306
307 030000 IFNDEF MODDVL,<MODDVL==BEGIN>
308 030000 IFNDEF MODDVU,<MODDVU==BEGIN>
309
310 ;"DIAMON" FILE SELECTION AND READ UUOS
311
312 037240 000004 OPDEF FSELECT [37B8!5B12!4] ;FILE SELECTION
313 037300 000004 OPDEF FREAD [37B8!6B12!4] ;FILE READ - ASCII DATA
314 037340 000004 OPDEF FRD36 [37B8!7B12!4] ;FILE READ - 36 BIT DATA
315 037400 000004 OPDEF FRD8 [37B8!10B12!4] ;FILE READ - 8 BIT DATA
316
317 ;KI10 ONLY UUO FOR PRINTING MARGIN VALUES
318
319 037700 000002 OPDEF PNTMGN [37B8!16B12!2] ;PRINT MARGIN VALUE
320
321 XLIST
322 IFNDEF KLOLD,<LIST
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 7
PARAM KLM 18-Sep-79 17:16 ERROR HANDLING UUO DEFINITIONS, SEPT 18,1979 SEQ 0015
323 SUBTTL ERROR HANDLING UUO DEFINITIONS, SEPT 18,1979
324
325 ; **********************************************************************
326 ;ERROR HANDLER PARAMETERS
327 ; **********************************************************************
328
329 036000 000000 OPDEF ERUUO [36B8] ;ERROR CALL UUO
330 035000 000000 OPDEF ERLOOP [35B8] ;ERROR LOOP, CHECKS PC,REPT,REPT1,ERROR
331 035040 000000 OPDEF ERLP1 [35B8!1B12] ;ERROR LOOP IF PC'S MATCH
332 035100 000000 OPDEF ERLP2 [35B8!2B12] ;ERROR LOOP IF ANY ERROR
333 034000 000000 OPDEF REPTUO [34B8] ;REPEAT LOOP UUO
334
335 ;THE ERROR HANDLER MACROS
336
337 ;A MACRO TO REPORT AN ERROR AND LOOP
338
339 DEFINE ERROR (ADR,FORMAT,CORECT,ACTUAL,F,D,ERR)<
340 SALL
341 ERUUO FORMAT,[T,,[SIXBIT\F'_\]
342 CORECT,,ACTUAL
343 [SIXBIT\D'_\],,ERR]
344 XALL
345 ERLOOP ADR ;IF ERROR, LOOP TO ADR
346 >
347
348 ;A MACRO TO REPORT AN ERROR AND NOT LOOP
349
350 DEFINE ERROR1 (FORMAT,CORECT,ACTUAL,F,D,ERR)<
351 SALL
352 ERUUO FORMAT,[T,,[SIXBIT\F'_\]
353 CORECT,,ACTUAL
354 [SIXBIT\D'_\],,ERR]
355 XALL>
356
357 >;END OF KLOLD CONDITIONAL
358
359 XLIST
360 LIST
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 1
FIXED KLM 18-Sep-79 17:18 *FIXED* FIXED CONTROL AND DISPATCH STORAGE, SEPT 18,1979 SEQ 0016
361 SUBTTL *FIXED* FIXED CONTROL AND DISPATCH STORAGE, SEPT 18,1979
362
363 030000 LOC 30000
364
365 ; **********************************************************************
366 ;PROGRAM STARTING ADDRESSES
367 ;THESE ADDRESSES CALL VARIOUS SPECIAL START ROUTINES AND OR OPTIONS
368 ;NORMAL START ADDRESS IS 30000 ALL OTHERS ARE SPECIAL. INVOKED BECAUSE
369 ;OF END OF PASS, POWER FAILURE, DDT START, RE-ENTERING(TYPICALLY USER
370 ;MODE), OR ANY NUMBER OF SPECIAL FEATURE TESTS.
371 ; **********************************************************************
372
373 030000 254 00 1 00 027776 BEGIN: JRST @MODLNK ;STAND-ALONE START
374 030001 254 00 0 00 030674 $START: JRST START ;MODE CHECK STARTING ADDRESS
375
376 030002 254 00 1 00 027774 DIAGMN: JRST @LDLNK ;DIAGNOSTIC MONITOR START
377
378 030003 254 00 1 00 027774 SYSEXR: JRST @LDLNK ;SYSTEM EXERCISER START
379
380 030004 254 00 0 00 030000 SFSTRT: JRST SADR1 ;SPECIAL FEATURE START
381
382 030005 254 00 0 00 030000 PFSTRT: JRST SADR2 ;POWER FAIL RESTART
383
384 030006 254 00 0 00 030000 REENTR: JRST SADR3 ;REENTER START(USUALLY USER MODE ONLY)
385
386 030007 SRTDDT: ;COMMONLY MISTAKEN NAME FOR "DDTSRT"
387 030007 254 00 1 00 027775 DDTSRT: JRST @DDTLNK ;DDT START
388
389 030010 254 00 0 00 030715 BEGIN1: JRST STARTA ;LOOP START(END OF PASS COMES HERE)
390 030011 254 00 1 00 027777 SBINIT: JRST @SUBLNK ;PMGINT LINKAGE
391 030012 000000 000000 RETURN: 0 ;RETURN ADDRESS STORAGE
392
393 030013 254000 030000 START1: SADR7 ;OPTIONAL STARTING ADR/INSTRUCTIONS
394 030014 254000 030000 START2: SADR8 ; "
395 030015 254000 030000 START3: SADR9 ; "
396 030016 254000 030000 START4: SADR10 ; "
397 030017 254000 030000 START5: SADR11 ; "
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 2
FIXED KLM 18-Sep-79 17:18 *FIXED* FIXED CONTROL AND DISPATCH STORAGE, SEPT 18,1979 SEQ 0017
398 ; **********************************************************************
399 ;PROGRAM FIXED PARAMETER AREA
400 ; **********************************************************************
401
402 030020 444653 414400 PNTNAM: PAREA3 ;SIXBIT PROGRAM NAME
403 030021 546064 000000 PNTEXT: PAREA4 ;SIXBIT PROGRAM EXTENSION
404 030022 000000 000000 RANDBS: PAREA1 ;RANDOM BASE NUMBER
405 030023 000000 000000 SWTEXR: PAREA2 ;SYSTEM EXERCISER SWITCHES
406 030024 000000 001000 ITRCNT: ITERAT ;PROGRAM ITERATIONS
407 030025 000000 030701 $PNAME: PGMNAM ;POINTER TO PROGRAMS NAME
408 030026 000000 000002 $PVER: MCNVER,,DECVER ;MCN & DEC VERSION LEVEL
409 030027 000000 030000 $MODVL: MODDVL ;DEVICE CODE CHANGE LOWER LIMIT
410 030030 000000 030000 $MODVU: MODDVU ;DEVICE CODE CHANGE UPPER LIMIT
411 030031 777777 777777 $EMODE: IFNDEF EXCASB,<0> IFDEF EXCASB,<-1> ;EXEC ALLOWED
412 030032 777777 777777 $UMODE: IFNDEF USRASB,<0> IFDEF USRASB,<-1> ;USER ALLOWED
413 030033 000000 000000 $DSKUP: IFNDEF DSKUPD,<0> IFDEF DSKUPD,<-1> ;DISK UPDATE MODE
414 030034 777777 777777 $MMAP: IFNDEF MEMMAP,<0> IFDEF MEMMAP,<-1> ;ALLOW MEMORY RTNS
415 030035 000000 000000 PAREA7: PAREA5 ;OPTIONAL PARAMETER
416 030036 000000 000000 PAREA8: PAREA6 ;OPTIONAL PARAMETER
417
418 ; **********************************************************************
419 ;PROGRAM VARIABLE PARAMETER AREA
420 ; **********************************************************************
421
422 030037 000000 000000 USER: 0 ; 0 = EXEC, -1 = USER MODE FLAG
423 030040 000000 000000 KAIFLG: 0 ;PROCESSOR TYPE, 0 = KA10, -1 = KI10
424 030041 000000 000000 KLFLG: 0 ;PROCESSOR TYPE, 0 = KA/KI, -1 = KL10
425 030042 777777 777777 MONFLG: -1 ;DIAG MONITOR SPECIAL USER FLAG
426 030043 000000 000000 MONCTL: 0 ;DIAG MON/SYS EXR FLAG
427 030044 000000 000000 MONTEN: 0 ;-1= LOADED BY 10
428 030045 000000 000000 CLOCKF: 0 ;CLOCK TICKED FLAG
429 030046 000000 000000 CONSW: 0 ;CONSOLE SWITCH SETTINGS
430 030047 000000 000000 PASCNT: 0 ;PROGRAM PASS COUNT
431 030050 000000 000000 RUNFLG: 0 ;PROGRAM RUN FLAG
432 030051 000000 000000 TESTPC: 0 ;SUBTEST PC
433 030052 000000 000000 ERRPC: 0 ;ERROR PC
434 030053 000000 000000 ERRTLS: 0 ;ERROR TOTALS
435 030054 000000 000000 TICKS: 0 ;PROGRAM RUNNING TIME
436 030055 000000 000000 MARGIN: 0 ;KI10 MARGIN WORD VALUE
437 030056 000000 000000 $ONETM: 0 ;SUBROUTINE INITIALIZATION FLAG
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 3
FIXED KLM 18-Sep-79 17:18 *FIXED* FIXED CONTROL AND DISPATCH STORAGE, SEPT 18,1979 SEQ 0018
438 ; **********************************************************************
439 ;SPECIAL PROGRAM DISPATCH ADDRESSES
440 ; **********************************************************************
441
442 030057 037 12 0 00 000004 BEGEND: ENDUUO ;END OF PASS
443 030060 254 00 0 00 030010 $BEND1: JRST BEGIN1 ;KEEP RUNNING PROGRAM
444 030061 037 16 0 00 000004 $BEND2: EOPUUO ;END OF PROGRAM - NO RETURN
445 030062 254000 030000 CNTLC: SADR5 ;CONTROL C XFER ADDRESS
446 030063 254000 030000 ALTMGO: SADR6 ;ALTMODE XFER ADDRESS
447 030064 CPOPJ1: ;SKIP RETURN
448 030064 350 00 0 17 000000 UUOSKP: AOS (P) ;SKIP RETURN FROM UUO
449 030065 CPOPJ: ;NON-SKIP REGULAR RETURN
450 030065 263 17 0 00 000000 UUOEXT: RTN ;UUO RETURN
451 030066 255 00 0 00 000000 UUORTN: JFCL ;ADDITIONAL USERS UUO ROUTINE
452 030067 255 00 0 00 000000 $UORTX: JFCL ;ADDITIONAL UUO LINKAGE
453 030070 255 00 0 00 000000 $UUOER: JFCL ;INITED AS (JRST $UOERX)
454 030071 255 00 0 00 000000 $ITRHL: JFCL ;ADDITIONAL INTERRUPT LINKAGE
455 030072 255 00 0 00 000000 $ITRX1: JFCL ; "
456 030073 255 00 0 00 000000 $USRHL: JFCL ; "
457 030074 255 00 0 00 000000 $RSRTX: JFCL ;ADDITIONAL POWER FAIL LINKAGE
458 030075 255 00 0 00 000000 $RSRTY: JFCL ; "
459 030076 255 00 0 00 000000 RESRT1: JFCL ; INITED AS (JRST RESRTX)
460 030077 255 00 0 00 000000 RESRT2: JFCL ; "
461 030100 255 00 0 00 000000 $PARER: JFCL ;ADDITIONAL PARITY ERROR LINKAGE
462 030101 255 00 0 00 000000 ERMORE: JFCL ;ADDITIONAL ERROR HANDLER LINKAGE
463 030102 254 04 0 00 030102 HALT . ;IMPROPER TRANSFER HALT
464
465 030103 000000 000000 $PSHER: 0 ;INITED AS (JRST PSHERR)
466 030104 000000 000000 ITRCH1: 0 ;PC & FLAGS OF CURRENT INTERRUPT
467 030105 000000 000000 0 ;INITED AS (JRST $ITRC1)
468
469 ; **********************************************************************
470 ;PROCESSOR CONTROL STORAGE
471 ; **********************************************************************
472
473 030106 000000 000000 $ACC0: 0 ;INTERRUPT SAVED AC0
474 030107 000000 000000 $SVPI: 0 ;INTERRUPT SAVED PI
475 030110 000000 000000 $SVAPR: 0 ;INTERRUPT SAVED APR
476 030111 000000 000000 $SVPAG: 0 ;INTERRUPT SAVED PAG (DATAI)
477 030112 000000 000000 $SPAG1: 0 ;INTERRUPT SAVED PAG (CONI)
478
479 030113 000000 000000 $SVUUO: 0 ;CURRENT USERS UUO
480 030114 000000 000000 $SVUPC: 0 ;PC OF CURRENT USERS UUO
481
482 030115 000000 000000 REPTU: 0 ;REPEAT UUO ITERATIONS
483 030116 000000 000000 SCOPE: 0 ;ERROR HANDLER SCOPE LOOP FLAG
484 030117 000000 000000 %CORFLG:0 ; " CORRECT FLAG
485 030120 000000 000000 %COREC: 0 ; " CORRECT DATA
486 030121 000000 000000 %ACTFL: 0 ; " ACTUAL FLAG
487 030122 000000 000000 %ACTUL: 0 ; " ACTUAL DATA
488 030123 000000 000000 %DISCR: 0 ; " DISCREPENCY DATA
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 4
FIXED KLM 18-Sep-79 17:18 *FIXED* FIXED CONTROL AND DISPATCH STORAGE, SEPT 18,1979 SEQ 0019
489 ; **********************************************************************
490 ;UUO DISPATCH TABLE
491 ; **********************************************************************
492 XLIST
493 LIST
494 030124 030070 030070 UUODIS: LUUO1,,$UUOER
495 030125 030070 030070 LUUO3,,LUUO2
496 030126 030070 030070 LUUO5,,LUUO4
497 030127 030070 030070 LUUO7,,LUUO6
498 030130 030070 030070 LUUO11,,LUUO10
499 030131 030070 030070 LUUO13,,LUUO12
500 030132 030070 030070 LUUO15,,LUUO14
501 030133 030070 030070 LUUO17,,LUUO16
502 030134 030070 030070 LUUO21,,LUUO20
503 030135 030070 030070 LUUO23,,LUUO22
504 030136 030070 030070 LUUO25,,LUUO24
505 030137 030070 030070 LUUO27,,LUUO26
506 030140 030070 030070 LUUO31,,LUUO30
507 030141 030070 030070 LUUO33,,LUUO32
508
509 ; **********************************************************************
510 ;MEMORY MANAGMENT STORAGE
511 ; **********************************************************************
512
513 030142 000000 000000 DF22F: 0 ;DF10 CONTROL FLAG, 0 = 18, -1 = 22 BIT
514 030143 000000 000000 MAPNEW: 0 ;MEMORY MAPPING CONTROL FLAG, -1 = 4096K MAPPING
515 030144 000000 000000 MEMTOT: 0 ;TOTAL MEMORY SIZE IN K (1024.)
516 030145 000000 000000 MEMLOW: 0 ;LOWEST USABLE MEMORY
517 030146 MEMSIZ: BLOCK ^D41 ;MEMORY SEGMENT POINTER TABLE
518
519 ; **********************************************************************
520 ;PRINT CONTROL STORAGE
521 ; **********************************************************************
522
523 030217 000000 000000 PNTFLG: 0 ;PRINT FLAG, -1 WHILE IN PRINT ROUTINE
524 030220 000000 000000 PNTENB: 0 ;PRINT ENABLE
525 030221 000000 000000 PDISF: 0 ;PRINT DISABLED FLAG
526 030222 000000 000000 PNTINH: 0 ;INHIBIT PRINT INPUT CHECKS
527 030223 000000 000000 PNTSPC: 0 ;PRINT SPACE CONTROL
528 030224 000000 000000 OPTIME: 0 ;TYPE-IN WAIT TIME
529 030225 000000 000000 $TWCNT: 0 ;TIME WAITED
530 030226 000000 000000 $DVOFF: 0 ;LOGICAL DEVICE INITED FLAG
531 030227 000000 000000 TTYFIL: 0 ;TTY EXEC FILLERS FLAG
532 030230 000000 000000 TTYSPD: 0 ;TTY EXEC BAUD RATE
533 030231 000000 000000 $TTCHR: 0 ;ACTUAL TYPED IN CHAR
534 030232 000000 000000 $CHRIN: 0 ;UPPER CASED & PARITY STRIPPED CHAR
535 030233 000000 000000 $TYPNB: 0 ;TYPED IN NUMBER
536 030234 000000 000000 $CRLF: 0 ;FREE CR/LF FLAG
537 030235 000000 000000 $TABF: 0 ;TAB CONVERSION FLAG
538 030236 000000 000000 $FFF: 0 ;FORM FEED CONVERSION FLAG
539 030237 000000 000000 $VTF: 0 ;VERTICAL TAB CONVERSION FLAG
540 030240 000000 000000 USRLFF: 0 ;USER LF FILLERS
541 030241 000000 000000 USRCRF: 0 ;USER CR FILLERS
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 5
FIXED KLM 18-Sep-79 17:18 *FIXED* FIXED CONTROL AND DISPATCH STORAGE, SEPT 18,1979 SEQ 0020
542 ; **********************************************************************
543 ;THE FOLLOWING MISCELLANEOUS PRINT CHARACTERS ARE INCLUDED
544 ;TO FACILITATE PRINTING AND ARE CALLED AS FOLLOWS:
545 ; MOVEI NAME
546 ; PNTA ;OR PNTAF
547 ; **********************************************************************
548
549 030242 CRLF: ASCII/
550 030242 015 012 000 000 000 /
551 030243 CRLF2: ASCII/
552
553 030243 015 012 015 012 000 /
554 030244 054 000 000 000 000 COMMA: ASCII/,/
555 030245 056 000 000 000 000 PERIOD: ASCII/./
556 030246 040 000 000 000 000 SPACE: ASCII/ /
557 030247 011 000 000 000 000 TAB: ASCII/ /
558 030250 MINUS:
559 030250 055 000 000 000 000 HYPEN: ASCII/-/
560 030251 053 000 000 000 000 PLUS: ASCII/+/
561 030252 052 000 000 000 000 AST: ASCII/*/
562 030253 100 000 000 000 000 ATSIN: ASCII/@/
563 030254 050 000 000 000 000 LFP: ASCII/(/
564 030255 051 000 000 000 000 RTP: ASCII/)/
565 030256 007 0000000000 BELL: BYTE (7) 007
566 030257 077 000 000 000 000 QUEST: ASCII/?/
567 030260 057 000 000 000 000 SLASH: ASCII!/!
568 030261 044 000 000 000 000 DOLLAR: ASCII/$/
569 030262 000000 000012 RADIX: ^D10 ;DECIMAL PRINT RADIX
570 030263 000000 000040 RADLSP: 40 ;DECIMAL PRINT LEADING CHAR
571 030264 000000 000012 RADLSC: ^D10 ;DECIMAL PRINT LEADING CHAR COUNT
572
573 ; **********************************************************************
574 ;USER MODE OUTPUT FILE INFORMATION
575 ; **********************************************************************
576
577 030265 $OBUF: BLOCK 3 ;LOGICAL FILE OUTPUT BUFFER HEADER
578 030270 60 62 51 56 64 00 $OUTNM: SIXBIT /PRINT/ ;FILE NAME
579 030271 60 56 64 00 00 00 $OUTEX: SIXBIT /PNT/ ;FILE NAME EXTENSION
580 030272 BLOCK 2
581
582 ; **********************************************************************
583 ;DISK UPDATE MODE FILE INFORMATION
584 ; **********************************************************************
585
586 030274 $IBUF: BLOCK 3
587 030277 60 62 51 56 64 00 $INNM: SIXBIT /PRINT/
588 030300 60 56 64 00 00 00 $INEXT: SIXBIT /PNT/
589 030301 BLOCK 2
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 6
FIXED KLM 18-Sep-79 17:18 *FIXED* FIXED CONTROL AND DISPATCH STORAGE, SEPT 18,1979 SEQ 0021
590 ; **********************************************************************
591 ;PUSHDOWN LIST CONTROL INFORMATION
592 ; **********************************************************************
593
594 030303 777577 030303 PLIST: PLIST-PLISTE,,PLIST
595 030304 PLISTS: BLOCK 200
596 030504 000000 000000 PLISTE: 0 ;END OF PUSHDOWN LIST
597
598 ; **********************************************************************
599 ;POWER LINE CLOCK FREQUENCY FLAG
600 ; **********************************************************************
601
602 030505 000000 000000 CYCL60: 0 ;0 = 60, -1 = 50 CYCLE
603
604 ; **********************************************************************
605 ;KL10 CACHE CONTROL FLAGS
606 ; **********************************************************************
607
608 030506 000000 000000 CSHFLG: 0 ;ALLOW CACHE IF 0
609 030507 000000 000000 CSHMEM: 0 ;CACHE MEMORY SEGMENTS IF 0
610
611 ; **********************************************************************
612 ;NUMBER INPUT DIGIT FLAG
613 ; **********************************************************************
614
615 030510 000000 000000 TTNBRF: 0 ;-1 IF ANY DIGIT TYPED
616
617 ; **********************************************************************
618 ;KL10 & KI10 "INHPAG" SWITCH PAGING PREVENTION
619 ; **********************************************************************
620
621 030511 000000 000000 PVPAGI: 0 ;IF NON-ZERO, OVERRIDE "INHPAG" SWITCH ACTION
622
623 ; **********************************************************************
624 ;ERROR REPORTING ROUTINE ADDITIONAL USERS CONTROL INSTRUCTIONS
625 ; **********************************************************************
626
627 030512 000000 000000 %ERHI1: 0 ;IF NON-ZERO, XCT'D AT START OF %ERUUO
628 030513 000000 000000 %ERHI2: 0 ;IF NON-ZERO, XCT'D AT END OF %ERUUO
629 030514 000000 000000 %ERHI3: 0 ;IF NON-ZERO, XCT'D AFTER "PC" OF %ERUUO
630
631 ; **********************************************************************
632 ;SPECIAL USERS UUO INTERCEPT INSTRUCTION
633 ; **********************************************************************
634
635 030515 000000 000000 $$UUO: 0 ;IF NON-ZERO, XCT'D AT START OF $UORTN
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 7
FIXED KLM 18-Sep-79 17:18 *FIXED* FIXED CONTROL AND DISPATCH STORAGE, SEPT 18,1979 SEQ 0022
636 ; **********************************************************************
637 ;USER MODE MONITOR TYPE FLAG
638 ; **********************************************************************
639
640 030516 000000 000000 MONTYP: 0 ;0 = TOPS10, -1 = TOPS20
641
642 ; **********************************************************************
643 ;SPECIAL USERS MUUO INTERCEPT INSTRUCTION
644 ; **********************************************************************
645
646 030517 000000 000000 $$MUUO: 0 ;IF NON-ZERO, XCT'D AT START OF MUUOER
647
648 ; **********************************************************************
649 ;SPECIAL USERS USER MODE OUTPUT ERROR INTERCEPT INSTUCTION
650 ; **********************************************************************
651
652 030520 000000 000000 $$OUTER:0 ;IF NON-ZERO, XCT'D AT END OF USER MODE ERROR
653
654 ; **********************************************************************
655 ;"SWITCH" CALL USAGE CONTROL
656 ; **********************************************************************
657
658 030521 000000 000000 $$TOGGLE:0 ;IF NON-ZERO, USE C(CONSW) FOR SWITCHES
659
660 ; **********************************************************************
661 ;SPECIAL USERS ALTMODE SWITCH CALL INTERCEPT INSTRUCTIONS
662 ; **********************************************************************
663
664 030522 000000 000000 $$TAX1: 0 ;IF NON-ZERO, XCT'D AT START OF ALTMODE SWITCH CALL
665 030523 000000 000000 $$TAX2: 0 ;IF NON-ZERO, XCT'D AT END OF ALTMODE SWITCH CALL
666
667 ; **********************************************************************
668 ;SM10 (KS-10) PROCESSOR TYPE FLAG
669 ; **********************************************************************
670
671 030524 000000 000000 SM10: 0 ;IF -1 THIS IS A KS-10
672
673 ; **********************************************************************
674 ;RIGHT HALF SWITCHES PROMPT TABLE ADDRESS
675 ; **********************************************************************
676
677 030525 000000 000000 SWPTAB: 0 ;0 = NO PROMPT, ADR = ADR OF SIXBIT PROMPT TABLE
678
679 ; **********************************************************************
680 ;SPECIAL FUTURE EXPANSION ROOM
681 ; **********************************************************************
682
683 ; **********************************************************************
684 ;END OF FIXED STORAGE
685 ; **********************************************************************
686
687 030577 LOC 30577
688 030577 000000 000000 ENDFIX: 0 ;END OF FIXED STORAGE
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 1
SPCCPU KLM 24-Oct-78 08:57 *SPCCPU* SPECIAL BASIC CPU PROCESSOR CONTROL, 26-FEB-76 SEQ 0023
689 SUBTTL *SPCCPU* SPECIAL BASIC CPU PROCESSOR CONTROL, 26-FEB-76
690
691 ;NEW DEFINITIONS USED BY THE KL10 SUBROUTINE PACKAGE
692
693 000000 AC0= 0
694 030000 DIAGNOS=30000 ;PDP-10 DIAGNOSTIC START ADDRESS
695 010000 DDT= 10000 ;PDP-10 DDT START ADDRESS
696 020000 DIAMON= 20000 ;PDP-10 DIAMON LOADER START ADDRESS
697 020000 DONG11= 1B22 ;11 DOORBELL (FROM THE 10)
698
699 ;DTE20 DEVICE CODES
700
701 000200 DTE== 200 ;DTE0
702 000204 DTE0== 204
703 000204 DTE1== 204
704 000210 DTE2== 210
705 000214 DTE3== 214
706
707 ;KL10 EPT COMMUNICATION AREA
708
709 000440 $STD= 440 ;PDP-10 DIAGNOSTIC START ADDRESS
710 000441 $DDT= 441 ;PDP-10 DDT START ADDRESS
711 000442 $STL= 442 ;PDP-10 LOADER START ADDRESS
712 000443 $STM= 443 ;PDP-10 MONITOR START ADDRESS
713
714 000444 $DTFLG= 444 ;DTE20 OPERATION COMPLETE FLAG
715 000445 $DTCLK= 445 ;DTE20 CLOCK INTERRUPT FLAG
716 000446 $DTCI= 446 ;DTE20 CLOCK INTERRUPT INSTRUCTION
717 000447 $DTT11= 447 ;DTE20 10 TO 11 ARGUMENT
718 000450 $DTF11= 450 ;DTE20 11 TO 10 ARGUMENT
719 000451 $DTCMD= 451 ;DTE20 TO 11 COMMAND WORD
720 000452 $DTSEQ= 452 ;DTE20 OPERATION SEQUENCE NUMBER
721 000453 $DTOPR= 453 ;DTE20 OPERATIONAL DTE #
722 000454 $DTCHR= 454 ;DTE20 LAST TYPED CHARACTER
723 000455 $DTMTD= 455 ;DTE20 MONITOR TTY OUTPUT COMPLETE FLAG
724 000456 $DTMTI= 456 ;DTE20 MONITOR TTY INPUT FLAG
725
726 000457 $DTSWR= 457 ;DTE20 CONSOLE SWITCH REGISTER
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 2
SPCCPU KLM 24-Oct-78 08:57 *SPCCPU* SPECIAL BASIC CPU PROCESSOR CONTROL, 26-FEB-76 SEQ 0024
727 ;SPECIAL "FIXED" REASSIGNMENTS
728
729 030600 $$LOC=. ;SAVE CURRENT LOCATION
730
731 030000 LOC 30000
732 030000 254 00 0 00 030600 $$BEGIN:JRST $$START ;SETUP SPECIAL START
733 030001 254 00 0 00 030600 JRST $$START ;"DIAMON" CHAIN START ADDRESS
734
735 000440 LOC 440
736 000440 254 00 0 00 030000 $STD: JRST BEGIN ;SETUP FOR "STD"
737 000443 LOC 443
738 000443 254 00 0 00 030626 $STM: JRST $SPEC ;SIMPLE RUN CONTROL
739
740 030057 LOC 30057
741 030057 254 00 0 00 030631 $BEGEND:JRST $SPBEND ;SETUP SPECIAL "BEGEND"
742
743 ;SPECIAL MUUO, TRAP & PAGE FAIL SETUP
744
745 000420 LOC 420
746 000420 254 04 0 00 000420 $$420: HALT . ;KI10 PAGE FAIL
747 000421 255 00 0 00 000000 $$421: JFCL ;OVERFLOW
748 000422 254 04 0 00 000422 $$422: HALT . ;PUSHDOWN OVERFLOW
749 000423 254 04 0 00 000423 $$423: HALT . ;TRAP 3
750 000424 000000 000000 $$424: 0 ;MMUO
751 000425 000000 000000 $$425: 0 ;MMUO PC
752 000426 000000 000000 $$426: 0 ;KI10-PAGE FAIL, KL10-PROCESS CONTEXT
753 000427 254 04 0 00 000427 $$427: HALT .
754 000430 000000 000427 $$430: 427 ;MMUO NEW PC'S
755 000431 000000 000427 $$431: 427
756 000432 000000 000427 $$432: 427
757 000433 000000 000427 $$433: 427
758 000434 000000 000427 $$434: 427
759 000435 000000 000427 $$435: 427
760 000436 000000 000427 $$436: 427
761 000437 000000 000427 $$437: 427
762
763 000500 LOC 500
764 000500 000000 000000 $$500: 0 ;KL10 PAGE FAIL WORD
765 000501 000000 000000 $$501: 0 ;KL10 PAGE FAIL PC
766 000502 000000 000503 $$502: 503 ;KL10 PAGE FAIL NEW PC
767 000503 254 04 0 00 000503 $$503: HALT .
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 3
SPCCPU KLM 24-Oct-78 08:57 *SPCCPU* SPECIAL BASIC CPU PROCESSOR CONTROL, 26-FEB-76 SEQ 0025
768 030600 LOC $$LOC ;RESET CURRENT LOCATION
769
770 ;SPECIAL STARTUP SEQUENCE
771
772 030600 402 00 0 00 030037 $$START:SETZM USER
773 030601 265 00 0 00 030602 JSP 0,.+1 ;IN USER MODE ?
774 030602 603 00 0 00 010000 TLNE 0,USERF
775 030603 476 00 0 00 030037 SETOM USER ;YES, SET CONTROL WORD
776 030604 336 00 0 00 030042 SKIPN MONFLG ;SPECIAL USER MODE ?
777 030605 402 00 0 00 030037 SETZM USER ;YES, RUN AS EXEC
778 030606 332 00 0 00 030037 SKIPE USER
779 030607 254 00 0 00 030674 JRST START ;USER MODE, DON'T NEED CPU TYPE
780
781 030610 336 00 0 00 030044 $STKIL: SKIPN MONTEN ;LOADED BY "DIAMON" ?
782 030611 476 00 0 00 030024 SETOM ITRCNT ;NO, RUN FOREVER
783 030612 402 00 0 00 030041 SETZM KLFLG ;ASSUME KI10
784 030613 200 01 0 00 034417 MOVE 1,[1,,1]
785 030614 251 01 0 00 000001 BLT 1,1 ;HOPE THIS WORKS
786 030615 316 01 0 00 034417 CAMN 1,[1,,1] ;IF AC NE 1,,1 AFTER BLT, KL10
787 030616 254 00 0 00 030674 JRST START ;KI10, NO ADDITIONAL SETUP
788
789 030617 402 00 0 00 000444 $STKL: SETZM $DTFLG
790 030620 402 00 0 00 000445 SETZM $DTCLK
791 030621 200 00 0 00 000453 MOVE $DTOPR ;GET DTE #
792 030622 436 00 0 00 030657 ORM $$DTE0 ;INSERT IN DTE I/O INSTS
793 030623 436 00 0 00 030670 ORM $$DTE2
794 030624 476 00 0 00 030041 SETOM KLFLG ;SET KL10 CONTROL FLAG
795 030625 254 00 0 00 030674 JRST START
796
797 030626 200 00 0 00 034420 $SPEC: MOVE [JRST STARTA] ;SIMPLE RUN CONTROL
798 030627 202 00 0 00 030633 MOVEM $SPB1
799 030630 254 00 0 00 030674 JRST START
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 4
SPCCPU KLM 24-Oct-78 08:57 *SPCCPU* SPECIAL BASIC CPU PROCESSOR CONTROL, 26-FEB-76 SEQ 0026
800 ;SPECIAL "BEGEND" ROUTINE
801
802 030631 350 00 0 00 030047 $SPBEND:AOS PASCNT ;INCREMENT PASS COUNT
803 030632 370 00 0 00 030024 SOS ITRCNT ;DECREMENT ITERATION COUNT
804 030633 336 00 0 00 030037 $SPB1: SKIPN USER
805 030634 254 00 0 00 030642 JRST $SPBEX ;EXEC MODE
806
807 030635 332 00 0 00 030024 $SPBUS: SKIPE ITRCNT ;USER MODE, COMPLETED ?
808 030636 254 00 0 00 030715 JRST STARTA ;NO, KEEP RUNNING
809 030637 336 00 0 00 030044 SKIPN MONTEN ;DONE, LOADED BY "DIAMON" ?
810 030640 047 00 0 00 000012 EXIT ;NO, RETURN TO MONITOR
811 030641 254 00 1 00 030012 JRST @RETURN ;YES, RETURN TO "DIAMON"
812
813 030642 332 00 0 00 030041 $SPBEX: SKIPE KLFLG
814 030643 254 00 0 00 030650 JRST $SPBKL ;KL10 & EXEC
815 030644 7 004 14 0 00 030024 DATAO PI,ITRCNT ;KI10 & EXEC, DISPLAY ITER COUNT
816 030645 332 00 0 00 030024 SKIPE ITRCNT
817 030646 254 00 0 00 030715 JRST STARTA ;NOT COMPLETED YET
818 030647 254 00 1 00 030012 JRST @RETURN ;DONE
819
820 030650 336 00 0 00 030024 $SPBKL: SKIPN ITRCNT
821 030651 254 00 0 00 030663 JRST $SPKLD ;KL10, EXEC & COMPLETED
822
823 030652 335 00 0 00 030043 SKIPGE MONCTL
824 030653 254 00 0 00 030715 JRST STARTA ;"DIAMON" CONTROL
825 030654 201 00 0 00 000404 MOVEI 0,404 ;NOTIFY PDP-11 OF END OF PASS
826 030655 202 00 0 00 000451 MOVEM 0,$DTCMD
827 030656 402 00 0 00 000444 SETZM $DTFLG
828 030657 7 200 20 0 00 020000 $$DTE0: CONO DTE,DONG11
829 030660 336 00 0 00 000444 SKIPN $DTFLG ;WAIT TILL 11 RESPONDS
830 030661 254 00 0 00 030660 JRST .-1
831 030662 254 00 0 00 030715 JRST STARTA ;KEEP RUNNING
832
833 ;SPECIAL KL10 COMPLETED ROUTINE
834
835 030663 332 00 0 00 030044 $SPKLD: SKIPE MONTEN
836 030664 254 00 1 00 030012 JRST @RETURN ;LOADED BY "DIAMON"
837
838 030665 201 00 0 00 000403 MOVEI 0,403 ;NOTIFY PDP-11 OF COMPLETION
839 030666 202 00 0 00 000451 MOVEM 0,$DTCMD
840 030667 402 00 0 00 000444 SETZM $DTFLG
841 030670 7 200 20 0 00 020000 $$DTE2: CONO DTE,DONG11
842 030671 336 00 0 00 000444 SKIPN $DTFLG ;SHOULD NEVER HAPPEN
843 030672 254 00 0 00 030671 JRST .-1 ;11 NEVER RETURNS ON END OF PROGRAM
844 030673 254 04 0 00 030000 HALT BEGIN ;IF IT DOES, HALT.
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 1
DFKAD1 MAC 1-Oct-84 16:01 DIAGNOSTIC SECTION SEQ 0027
845 SUBTTL DIAGNOSTIC SECTION
846
847 030674 336 00 0 00 030037 START: SKIPN USER
848 030675 254 00 0 00 030715 JRST STARTA
849
850 030676 331 00 0 00 030043 SKIPL MONCTL
851 030677 051 03 0 00 030701 TTCALL 3,PGMNAM
852 030700 254 00 0 00 030715 JRST STARTA
853
854 030701 PGMNAM: ASCIZ/
855 030701 015 012 104 105 103 DECSYSTEM KL10 BASIC INSTRUCTION DIAGNOSTIC (4) [DFKAD]
856 030702 123 131 123 124 105
857 030703 115 040 113 114 061
858 030704 060 040 102 101 123
859 030705 111 103 040 111 116
860 030706 123 124 122 125 103
861 030707 124 111 117 116 040
862 030710 104 111 101 107 116
863 030711 117 123 124 111 103
864 030712 040 050 064 051 040
865 030713 133 104 106 113 101
866 030714 104 135 015 012 000 /
867
868 ;Basic instruction test (4)
869 ;The test is designed for initial debugging of
870 ;Processor hardware and to detect (solid) failures
871 ;In the field.
872
873 030715 254 00 0 00 030716 STARTA: JRST .+1
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 2
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AC HARDWARE AND INDEX REGISTERS SEQ 0028
874 SUBTTL TEST OF AC HARDWARE AND INDEX REGISTERS
875
876 ;Note: an "*" in the comment field of an instruction indicates that
877 ; It is the tested instruction.
878
879
880 ;**********
881
882 ;This test verifies that ac1 is accessable
883 ;In this case, ac1 is preloaded with 1.
884 ;C(ac1) is then checked for a1. this test passes if c(ac1)=1.
885 ;If this test fails, the ac hardware is probably faulty.
886
887 030716 400 00 0 00 000000 C100: SETZ ;Clear ac0
888 030717 201 01 0 00 000001 MOVEI 1,1 ;Preload ac1 umth 1
889 030720 302 01 0 00 000001 CAIE 1,1 ;Pass if c(ac1)=1
890 STOP^
891 030721 254 04 0 00 030722 HALT .+1 ;Test failed if program halts here
892 030722 324 00 0 00 030723 JUMPA .+1 ;To loop change this instruction^
893
894 ;**********
895
896 ;This test verifies that ac2 is accessable.
897 ;In this case, ac2 is preloaded with 2.
898 ;C(ac2) is then checked for 2. this test passes if c(ac2)=2.
899 ;If this test fails, the ac hardware is probably faulty.
900
901 030723 201 02 0 00 000002 C200: MOVEI 2,2 ;Preload ac2 with 2
902 030724 302 02 0 00 000002 CAIE 2,2 ;Pass if c(ac2)=2
903 STOP^
904 030725 254 04 0 00 030726 HALT .+1 ;Test failed if program halts here
905 030726 324 00 0 00 030727 JUMPA .+1 ;To loop change this instruction^
906
907 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 3
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AC HARDWARE AND INDEX REGISTERS SEQ 0029
908 ;This test verifies that ac4 is accessable.
909 ;In this case, ac4 is preloaded with 4.
910 ;C(ac4) is then checked for 4. this test passes if c(ac4)=4.
911 ;If this test fails, the ac hardware is probably faulty.
912
913 030727 201 04 0 00 000004 C300: MOVEI 4,4 ;Preload ac4 with 4
914 030730 302 04 0 00 000004 CAIE 4,4 ;Pass if c(ac4)=4
915 STOP^
916 030731 254 04 0 00 030732 HALT .+1 ;Test failed if program halts here
917 030732 324 00 0 00 030733 JUMPA .+1 ;To loop change this instruction^
918
919 ;**********
920
921 ;This test verifies that ac10 is accessable.
922 ;In this case, ac10 is preloaded with 10.
923 ;C(ac10) is then checked for 10. this test passes if c(ac10)=10.
924 ;If this test fails, the ac hardware is probably faulty.
925
926 030733 201 10 0 00 000010 C400: MOVEI 10,10 ;Preload ac10 with 10
927 030734 302 10 0 00 000010 CAIE 10,10 ;Pass if c(ac10)=10
928 STOP^
929 030735 254 04 0 00 030736 HALT .+1 ;Test failed if program halts here
930 030736 324 00 0 00 030737 JUMPA .+1 ;To loop change this instruction^
931
932 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 4
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AC HARDWARE AND INDEX REGISTERS SEQ 0030
933 000500 SN=500
934 777777 777777 ZZ=-1
935
936 ;This test verifies that all acs exist. first, each ac is
937 ;Preloaded with its own address. then, the contents of each
938 ;Ac is checked for its address. if any ac does not contain
939 ;Its address, this test fails.
940
941 C500: REPEAT ^D16,
942 < ZZ=ZZ+1
943 MOVEI ZZ,ZZ ;Preload each ac with its addr>
944 000000 ZZ=ZZ+1
945 030737 201 00 0 00 000000 MOVEI ZZ,ZZ ;Preload each ac with its addr
946 000001 ZZ=ZZ+1
947 030740 201 01 0 00 000001 MOVEI ZZ,ZZ ;Preload each ac with its addr
948 000002 ZZ=ZZ+1
949 030741 201 02 0 00 000002 MOVEI ZZ,ZZ ;Preload each ac with its addr
950 000003 ZZ=ZZ+1
951 030742 201 03 0 00 000003 MOVEI ZZ,ZZ ;Preload each ac with its addr
952 000004 ZZ=ZZ+1
953 030743 201 04 0 00 000004 MOVEI ZZ,ZZ ;Preload each ac with its addr
954 000005 ZZ=ZZ+1
955 030744 201 05 0 00 000005 MOVEI ZZ,ZZ ;Preload each ac with its addr
956 000006 ZZ=ZZ+1
957 030745 201 06 0 00 000006 MOVEI ZZ,ZZ ;Preload each ac with its addr
958 000007 ZZ=ZZ+1
959 030746 201 07 0 00 000007 MOVEI ZZ,ZZ ;Preload each ac with its addr
960 000010 ZZ=ZZ+1
961 030747 201 10 0 00 000010 MOVEI ZZ,ZZ ;Preload each ac with its addr
962 000011 ZZ=ZZ+1
963 030750 201 11 0 00 000011 MOVEI ZZ,ZZ ;Preload each ac with its addr
964 000012 ZZ=ZZ+1
965 030751 201 12 0 00 000012 MOVEI ZZ,ZZ ;Preload each ac with its addr
966 000013 ZZ=ZZ+1
967 030752 201 13 0 00 000013 MOVEI ZZ,ZZ ;Preload each ac with its addr
968 000014 ZZ=ZZ+1
969 030753 201 14 0 00 000014 MOVEI ZZ,ZZ ;Preload each ac with its addr
970 000015 ZZ=ZZ+1
971 030754 201 15 0 00 000015 MOVEI ZZ,ZZ ;Preload each ac with its addr
972 000016 ZZ=ZZ+1
973 030755 201 16 0 00 000016 MOVEI ZZ,ZZ ;Preload each ac with its addr
974 000017 ZZ=ZZ+1
975 030756 201 17 0 00 000017 MOVEI ZZ,ZZ ;Preload each ac with its addr
976 PAGE
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 4-1
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AC HARDWARE AND INDEX REGISTERS SEQ 0031
977 000020 ZZ=20
978
979 REPEAT ^D16,<
980 ;This test verifies that all acs exist. first, each ac is
981 ;Preloaded with its own address. then, the contents of each
982 ;Ac is checked for its address. if any ac does not contain
983 ;Its address, this test fails.
984
985 SN=SN+1
986 ZZ=ZZ-1
987 CAIE ZZ,ZZ ;Check that each ac contains its own address
988 STOP
989 ;In case of failure, loop to "c500" address
990
991 ;**********
992 >
993
994 ;This test verifies that all acs exist. first, each ac is
995 ;Preloaded with its own address. then, the contents of each
996 ;Ac is checked for its address. if any ac does not contain
997 ;Its address, this test fails.
998
999 000501 SN=SN+1
1000 000017 ZZ=ZZ-1
1001 030757 302 17 0 00 000017 CAIE ZZ,ZZ ;Check that each ac contains its own address
1002 STOP^
1003 030760 254 04 0 00 030761 HALT .+1 ;Test failed if program halts here
1004 030761 324 00 0 00 030762 JUMPA .+1 ;To loop change this instruction^
1005 ;In case of failure, loop to "c500" address
1006
1007 ;**********
1008
1009
1010 ;This test verifies that all acs exist. first, each ac is
1011 ;Preloaded with its own address. then, the contents of each
1012 ;Ac is checked for its address. if any ac does not contain
1013 ;Its address, this test fails.
1014
1015 000502 SN=SN+1
1016 000016 ZZ=ZZ-1
1017 030762 302 16 0 00 000016 CAIE ZZ,ZZ ;Check that each ac contains its own address
1018 STOP^
1019 030763 254 04 0 00 030764 HALT .+1 ;Test failed if program halts here
1020 030764 324 00 0 00 030765 JUMPA .+1 ;To loop change this instruction^
1021 ;In case of failure, loop to "c500" address
1022
1023 ;**********
1024
1025
1026 ;This test verifies that all acs exist. first, each ac is
1027 ;Preloaded with its own address. then, the contents of each
1028 ;Ac is checked for its address. if any ac does not contain
1029 ;Its address, this test fails.
1030
1031 000503 SN=SN+1
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 4-2
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AC HARDWARE AND INDEX REGISTERS SEQ 0032
1032 000015 ZZ=ZZ-1
1033 030765 302 15 0 00 000015 CAIE ZZ,ZZ ;Check that each ac contains its own address
1034 STOP^
1035 030766 254 04 0 00 030767 HALT .+1 ;Test failed if program halts here
1036 030767 324 00 0 00 030770 JUMPA .+1 ;To loop change this instruction^
1037 ;In case of failure, loop to "c500" address
1038
1039 ;**********
1040
1041
1042 ;This test verifies that all acs exist. first, each ac is
1043 ;Preloaded with its own address. then, the contents of each
1044 ;Ac is checked for its address. if any ac does not contain
1045 ;Its address, this test fails.
1046
1047 000504 SN=SN+1
1048 000014 ZZ=ZZ-1
1049 030770 302 14 0 00 000014 CAIE ZZ,ZZ ;Check that each ac contains its own address
1050 STOP^
1051 030771 254 04 0 00 030772 HALT .+1 ;Test failed if program halts here
1052 030772 324 00 0 00 030773 JUMPA .+1 ;To loop change this instruction^
1053 ;In case of failure, loop to "c500" address
1054
1055 ;**********
1056
1057
1058 ;This test verifies that all acs exist. first, each ac is
1059 ;Preloaded with its own address. then, the contents of each
1060 ;Ac is checked for its address. if any ac does not contain
1061 ;Its address, this test fails.
1062
1063 000505 SN=SN+1
1064 000013 ZZ=ZZ-1
1065 030773 302 13 0 00 000013 CAIE ZZ,ZZ ;Check that each ac contains its own address
1066 STOP^
1067 030774 254 04 0 00 030775 HALT .+1 ;Test failed if program halts here
1068 030775 324 00 0 00 030776 JUMPA .+1 ;To loop change this instruction^
1069 ;In case of failure, loop to "c500" address
1070
1071 ;**********
1072
1073
1074 ;This test verifies that all acs exist. first, each ac is
1075 ;Preloaded with its own address. then, the contents of each
1076 ;Ac is checked for its address. if any ac does not contain
1077 ;Its address, this test fails.
1078
1079 000506 SN=SN+1
1080 000012 ZZ=ZZ-1
1081 030776 302 12 0 00 000012 CAIE ZZ,ZZ ;Check that each ac contains its own address
1082 STOP^
1083 030777 254 04 0 00 031000 HALT .+1 ;Test failed if program halts here
1084 031000 324 00 0 00 031001 JUMPA .+1 ;To loop change this instruction^
1085 ;In case of failure, loop to "c500" address
1086
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 4-3
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AC HARDWARE AND INDEX REGISTERS SEQ 0033
1087 ;**********
1088
1089
1090 ;This test verifies that all acs exist. first, each ac is
1091 ;Preloaded with its own address. then, the contents of each
1092 ;Ac is checked for its address. if any ac does not contain
1093 ;Its address, this test fails.
1094
1095 000507 SN=SN+1
1096 000011 ZZ=ZZ-1
1097 031001 302 11 0 00 000011 CAIE ZZ,ZZ ;Check that each ac contains its own address
1098 STOP^
1099 031002 254 04 0 00 031003 HALT .+1 ;Test failed if program halts here
1100 031003 324 00 0 00 031004 JUMPA .+1 ;To loop change this instruction^
1101 ;In case of failure, loop to "c500" address
1102
1103 ;**********
1104
1105
1106 ;This test verifies that all acs exist. first, each ac is
1107 ;Preloaded with its own address. then, the contents of each
1108 ;Ac is checked for its address. if any ac does not contain
1109 ;Its address, this test fails.
1110
1111 000510 SN=SN+1
1112 000010 ZZ=ZZ-1
1113 031004 302 10 0 00 000010 CAIE ZZ,ZZ ;Check that each ac contains its own address
1114 STOP^
1115 031005 254 04 0 00 031006 HALT .+1 ;Test failed if program halts here
1116 031006 324 00 0 00 031007 JUMPA .+1 ;To loop change this instruction^
1117 ;In case of failure, loop to "c500" address
1118
1119 ;**********
1120
1121
1122 ;This test verifies that all acs exist. first, each ac is
1123 ;Preloaded with its own address. then, the contents of each
1124 ;Ac is checked for its address. if any ac does not contain
1125 ;Its address, this test fails.
1126
1127 000511 SN=SN+1
1128 000007 ZZ=ZZ-1
1129 031007 302 07 0 00 000007 CAIE ZZ,ZZ ;Check that each ac contains its own address
1130 STOP^
1131 031010 254 04 0 00 031011 HALT .+1 ;Test failed if program halts here
1132 031011 324 00 0 00 031012 JUMPA .+1 ;To loop change this instruction^
1133 ;In case of failure, loop to "c500" address
1134
1135 ;**********
1136
1137
1138 ;This test verifies that all acs exist. first, each ac is
1139 ;Preloaded with its own address. then, the contents of each
1140 ;Ac is checked for its address. if any ac does not contain
1141 ;Its address, this test fails.
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 4-4
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AC HARDWARE AND INDEX REGISTERS SEQ 0034
1142
1143 000512 SN=SN+1
1144 000006 ZZ=ZZ-1
1145 031012 302 06 0 00 000006 CAIE ZZ,ZZ ;Check that each ac contains its own address
1146 STOP^
1147 031013 254 04 0 00 031014 HALT .+1 ;Test failed if program halts here
1148 031014 324 00 0 00 031015 JUMPA .+1 ;To loop change this instruction^
1149 ;In case of failure, loop to "c500" address
1150
1151 ;**********
1152
1153
1154 ;This test verifies that all acs exist. first, each ac is
1155 ;Preloaded with its own address. then, the contents of each
1156 ;Ac is checked for its address. if any ac does not contain
1157 ;Its address, this test fails.
1158
1159 000513 SN=SN+1
1160 000005 ZZ=ZZ-1
1161 031015 302 05 0 00 000005 CAIE ZZ,ZZ ;Check that each ac contains its own address
1162 STOP^
1163 031016 254 04 0 00 031017 HALT .+1 ;Test failed if program halts here
1164 031017 324 00 0 00 031020 JUMPA .+1 ;To loop change this instruction^
1165 ;In case of failure, loop to "c500" address
1166
1167 ;**********
1168
1169
1170 ;This test verifies that all acs exist. first, each ac is
1171 ;Preloaded with its own address. then, the contents of each
1172 ;Ac is checked for its address. if any ac does not contain
1173 ;Its address, this test fails.
1174
1175 000514 SN=SN+1
1176 000004 ZZ=ZZ-1
1177 031020 302 04 0 00 000004 CAIE ZZ,ZZ ;Check that each ac contains its own address
1178 STOP^
1179 031021 254 04 0 00 031022 HALT .+1 ;Test failed if program halts here
1180 031022 324 00 0 00 031023 JUMPA .+1 ;To loop change this instruction^
1181 ;In case of failure, loop to "c500" address
1182
1183 ;**********
1184
1185
1186 ;This test verifies that all acs exist. first, each ac is
1187 ;Preloaded with its own address. then, the contents of each
1188 ;Ac is checked for its address. if any ac does not contain
1189 ;Its address, this test fails.
1190
1191 000515 SN=SN+1
1192 000003 ZZ=ZZ-1
1193 031023 302 03 0 00 000003 CAIE ZZ,ZZ ;Check that each ac contains its own address
1194 STOP^
1195 031024 254 04 0 00 031025 HALT .+1 ;Test failed if program halts here
1196 031025 324 00 0 00 031026 JUMPA .+1 ;To loop change this instruction^
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 4-5
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AC HARDWARE AND INDEX REGISTERS SEQ 0035
1197 ;In case of failure, loop to "c500" address
1198
1199 ;**********
1200
1201
1202 ;This test verifies that all acs exist. first, each ac is
1203 ;Preloaded with its own address. then, the contents of each
1204 ;Ac is checked for its address. if any ac does not contain
1205 ;Its address, this test fails.
1206
1207 000516 SN=SN+1
1208 000002 ZZ=ZZ-1
1209 031026 302 02 0 00 000002 CAIE ZZ,ZZ ;Check that each ac contains its own address
1210 STOP^
1211 031027 254 04 0 00 031030 HALT .+1 ;Test failed if program halts here
1212 031030 324 00 0 00 031031 JUMPA .+1 ;To loop change this instruction^
1213 ;In case of failure, loop to "c500" address
1214
1215 ;**********
1216
1217
1218 ;This test verifies that all acs exist. first, each ac is
1219 ;Preloaded with its own address. then, the contents of each
1220 ;Ac is checked for its address. if any ac does not contain
1221 ;Its address, this test fails.
1222
1223 000517 SN=SN+1
1224 000001 ZZ=ZZ-1
1225 031031 302 01 0 00 000001 CAIE ZZ,ZZ ;Check that each ac contains its own address
1226 STOP^
1227 031032 254 04 0 00 031033 HALT .+1 ;Test failed if program halts here
1228 031033 324 00 0 00 031034 JUMPA .+1 ;To loop change this instruction^
1229 ;In case of failure, loop to "c500" address
1230
1231 ;**********
1232
1233
1234 ;This test verifies that all acs exist. first, each ac is
1235 ;Preloaded with its own address. then, the contents of each
1236 ;Ac is checked for its address. if any ac does not contain
1237 ;Its address, this test fails.
1238
1239 000520 SN=SN+1
1240 000000 ZZ=ZZ-1
1241 031034 302 00 0 00 000000 CAIE ZZ,ZZ ;Check that each ac contains its own address
1242 STOP^
1243 031035 254 04 0 00 031036 HALT .+1 ;Test failed if program halts here
1244 031036 324 00 0 00 031037 JUMPA .+1 ;To loop change this instruction^
1245 ;In case of failure, loop to "c500" address
1246
1247 ;**********
1248
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 5
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AC HARDWARE AND INDEX REGISTERS SEQ 0036
1249 000600 SN=600
1250 000000 ZZ=0
1251
1252 ;This test verifies that an address within the ac range may be accessed as
1253 ;Either an ac or a memory location and that either reference refers to the
1254 ;Same hardware. each ac is preloaded with its address. then the contents
1255 ;Of each ac is checked for its address. if any ac does not contain its
1256 ;Address, this test fails.
1257
1258 C600: REPEAT ^D15,
1259 < ZZ=ZZ+1
1260 MOVEI ZZ ;Preload each ac with its address
1261 MOVEM ZZ ;By referencing each ac as memory.>
1262 000001 ZZ=ZZ+1
1263 031037 201 00 0 00 000001 MOVEI ZZ ;Preload each ac with its address
1264 031040 202 00 0 00 000001 MOVEM ZZ ;By referencing each ac as memory.
1265 000002 ZZ=ZZ+1
1266 031041 201 00 0 00 000002 MOVEI ZZ ;Preload each ac with its address
1267 031042 202 00 0 00 000002 MOVEM ZZ ;By referencing each ac as memory.
1268 000003 ZZ=ZZ+1
1269 031043 201 00 0 00 000003 MOVEI ZZ ;Preload each ac with its address
1270 031044 202 00 0 00 000003 MOVEM ZZ ;By referencing each ac as memory.
1271 000004 ZZ=ZZ+1
1272 031045 201 00 0 00 000004 MOVEI ZZ ;Preload each ac with its address
1273 031046 202 00 0 00 000004 MOVEM ZZ ;By referencing each ac as memory.
1274 000005 ZZ=ZZ+1
1275 031047 201 00 0 00 000005 MOVEI ZZ ;Preload each ac with its address
1276 031050 202 00 0 00 000005 MOVEM ZZ ;By referencing each ac as memory.
1277 000006 ZZ=ZZ+1
1278 031051 201 00 0 00 000006 MOVEI ZZ ;Preload each ac with its address
1279 031052 202 00 0 00 000006 MOVEM ZZ ;By referencing each ac as memory.
1280 000007 ZZ=ZZ+1
1281 031053 201 00 0 00 000007 MOVEI ZZ ;Preload each ac with its address
1282 031054 202 00 0 00 000007 MOVEM ZZ ;By referencing each ac as memory.
1283 000010 ZZ=ZZ+1
1284 031055 201 00 0 00 000010 MOVEI ZZ ;Preload each ac with its address
1285 031056 202 00 0 00 000010 MOVEM ZZ ;By referencing each ac as memory.
1286 000011 ZZ=ZZ+1
1287 031057 201 00 0 00 000011 MOVEI ZZ ;Preload each ac with its address
1288 031060 202 00 0 00 000011 MOVEM ZZ ;By referencing each ac as memory.
1289 000012 ZZ=ZZ+1
1290 031061 201 00 0 00 000012 MOVEI ZZ ;Preload each ac with its address
1291 031062 202 00 0 00 000012 MOVEM ZZ ;By referencing each ac as memory.
1292 000013 ZZ=ZZ+1
1293 031063 201 00 0 00 000013 MOVEI ZZ ;Preload each ac with its address
1294 031064 202 00 0 00 000013 MOVEM ZZ ;By referencing each ac as memory.
1295 000014 ZZ=ZZ+1
1296 031065 201 00 0 00 000014 MOVEI ZZ ;Preload each ac with its address
1297 031066 202 00 0 00 000014 MOVEM ZZ ;By referencing each ac as memory.
1298 000015 ZZ=ZZ+1
1299 031067 201 00 0 00 000015 MOVEI ZZ ;Preload each ac with its address
1300 031070 202 00 0 00 000015 MOVEM ZZ ;By referencing each ac as memory.
1301 000016 ZZ=ZZ+1
1302 031071 201 00 0 00 000016 MOVEI ZZ ;Preload each ac with its address
1303 031072 202 00 0 00 000016 MOVEM ZZ ;By referencing each ac as memory.
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 5-1
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AC HARDWARE AND INDEX REGISTERS SEQ 0037
1304 000017 ZZ=ZZ+1
1305 031073 201 00 0 00 000017 MOVEI ZZ ;Preload each ac with its address
1306 031074 202 00 0 00 000017 MOVEM ZZ ;By referencing each ac as memory.
1307
1308 000020 ZZ=20
1309
1310 REPEAT ^D15,<
1311 ;This test verifies that an address within the ac range may be accessed as
1312 ;Either an ac or a memory location and that either reference refers to the
1313 ;Same hardware. each ac is preloaded with its address. then the contents
1314 ;Of each ac is checked for its address. if any ac does not contain its
1315 ;Address, this test fails.
1316
1317 SN=SN+1
1318 ZZ=ZZ-1
1319 CAIE ZZ,ZZ ;Check that each ac contains its own address
1320 STOP
1321 ;In case of failure, loop to "c600" address
1322
1323 ;**********
1324 >
1325
1326 ;This test verifies that an address within the ac range may be accessed as
1327 ;Either an ac or a memory location and that either reference refers to the
1328 ;Same hardware. each ac is preloaded with its address. then the contents
1329 ;Of each ac is checked for its address. if any ac does not contain its
1330 ;Address, this test fails.
1331
1332 000601 SN=SN+1
1333 000017 ZZ=ZZ-1
1334 031075 302 17 0 00 000017 CAIE ZZ,ZZ ;Check that each ac contains its own address
1335 STOP^
1336 031076 254 04 0 00 031077 HALT .+1 ;Test failed if program halts here
1337 031077 324 00 0 00 031100 JUMPA .+1 ;To loop change this instruction^
1338 ;In case of failure, loop to "c600" address
1339
1340 ;**********
1341
1342
1343 ;This test verifies that an address within the ac range may be accessed as
1344 ;Either an ac or a memory location and that either reference refers to the
1345 ;Same hardware. each ac is preloaded with its address. then the contents
1346 ;Of each ac is checked for its address. if any ac does not contain its
1347 ;Address, this test fails.
1348
1349 000602 SN=SN+1
1350 000016 ZZ=ZZ-1
1351 031100 302 16 0 00 000016 CAIE ZZ,ZZ ;Check that each ac contains its own address
1352 STOP^
1353 031101 254 04 0 00 031102 HALT .+1 ;Test failed if program halts here
1354 031102 324 00 0 00 031103 JUMPA .+1 ;To loop change this instruction^
1355 ;In case of failure, loop to "c600" address
1356
1357 ;**********
1358
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 5-2
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AC HARDWARE AND INDEX REGISTERS SEQ 0038
1359
1360 ;This test verifies that an address within the ac range may be accessed as
1361 ;Either an ac or a memory location and that either reference refers to the
1362 ;Same hardware. each ac is preloaded with its address. then the contents
1363 ;Of each ac is checked for its address. if any ac does not contain its
1364 ;Address, this test fails.
1365
1366 000603 SN=SN+1
1367 000015 ZZ=ZZ-1
1368 031103 302 15 0 00 000015 CAIE ZZ,ZZ ;Check that each ac contains its own address
1369 STOP^
1370 031104 254 04 0 00 031105 HALT .+1 ;Test failed if program halts here
1371 031105 324 00 0 00 031106 JUMPA .+1 ;To loop change this instruction^
1372 ;In case of failure, loop to "c600" address
1373
1374 ;**********
1375
1376
1377 ;This test verifies that an address within the ac range may be accessed as
1378 ;Either an ac or a memory location and that either reference refers to the
1379 ;Same hardware. each ac is preloaded with its address. then the contents
1380 ;Of each ac is checked for its address. if any ac does not contain its
1381 ;Address, this test fails.
1382
1383 000604 SN=SN+1
1384 000014 ZZ=ZZ-1
1385 031106 302 14 0 00 000014 CAIE ZZ,ZZ ;Check that each ac contains its own address
1386 STOP^
1387 031107 254 04 0 00 031110 HALT .+1 ;Test failed if program halts here
1388 031110 324 00 0 00 031111 JUMPA .+1 ;To loop change this instruction^
1389 ;In case of failure, loop to "c600" address
1390
1391 ;**********
1392
1393
1394 ;This test verifies that an address within the ac range may be accessed as
1395 ;Either an ac or a memory location and that either reference refers to the
1396 ;Same hardware. each ac is preloaded with its address. then the contents
1397 ;Of each ac is checked for its address. if any ac does not contain its
1398 ;Address, this test fails.
1399
1400 000605 SN=SN+1
1401 000013 ZZ=ZZ-1
1402 031111 302 13 0 00 000013 CAIE ZZ,ZZ ;Check that each ac contains its own address
1403 STOP^
1404 031112 254 04 0 00 031113 HALT .+1 ;Test failed if program halts here
1405 031113 324 00 0 00 031114 JUMPA .+1 ;To loop change this instruction^
1406 ;In case of failure, loop to "c600" address
1407
1408 ;**********
1409
1410
1411 ;This test verifies that an address within the ac range may be accessed as
1412 ;Either an ac or a memory location and that either reference refers to the
1413 ;Same hardware. each ac is preloaded with its address. then the contents
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 5-3
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AC HARDWARE AND INDEX REGISTERS SEQ 0039
1414 ;Of each ac is checked for its address. if any ac does not contain its
1415 ;Address, this test fails.
1416
1417 000606 SN=SN+1
1418 000012 ZZ=ZZ-1
1419 031114 302 12 0 00 000012 CAIE ZZ,ZZ ;Check that each ac contains its own address
1420 STOP^
1421 031115 254 04 0 00 031116 HALT .+1 ;Test failed if program halts here
1422 031116 324 00 0 00 031117 JUMPA .+1 ;To loop change this instruction^
1423 ;In case of failure, loop to "c600" address
1424
1425 ;**********
1426
1427
1428 ;This test verifies that an address within the ac range may be accessed as
1429 ;Either an ac or a memory location and that either reference refers to the
1430 ;Same hardware. each ac is preloaded with its address. then the contents
1431 ;Of each ac is checked for its address. if any ac does not contain its
1432 ;Address, this test fails.
1433
1434 000607 SN=SN+1
1435 000011 ZZ=ZZ-1
1436 031117 302 11 0 00 000011 CAIE ZZ,ZZ ;Check that each ac contains its own address
1437 STOP^
1438 031120 254 04 0 00 031121 HALT .+1 ;Test failed if program halts here
1439 031121 324 00 0 00 031122 JUMPA .+1 ;To loop change this instruction^
1440 ;In case of failure, loop to "c600" address
1441
1442 ;**********
1443
1444
1445 ;This test verifies that an address within the ac range may be accessed as
1446 ;Either an ac or a memory location and that either reference refers to the
1447 ;Same hardware. each ac is preloaded with its address. then the contents
1448 ;Of each ac is checked for its address. if any ac does not contain its
1449 ;Address, this test fails.
1450
1451 000610 SN=SN+1
1452 000010 ZZ=ZZ-1
1453 031122 302 10 0 00 000010 CAIE ZZ,ZZ ;Check that each ac contains its own address
1454 STOP^
1455 031123 254 04 0 00 031124 HALT .+1 ;Test failed if program halts here
1456 031124 324 00 0 00 031125 JUMPA .+1 ;To loop change this instruction^
1457 ;In case of failure, loop to "c600" address
1458
1459 ;**********
1460
1461
1462 ;This test verifies that an address within the ac range may be accessed as
1463 ;Either an ac or a memory location and that either reference refers to the
1464 ;Same hardware. each ac is preloaded with its address. then the contents
1465 ;Of each ac is checked for its address. if any ac does not contain its
1466 ;Address, this test fails.
1467
1468 000611 SN=SN+1
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 5-4
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AC HARDWARE AND INDEX REGISTERS SEQ 0040
1469 000007 ZZ=ZZ-1
1470 031125 302 07 0 00 000007 CAIE ZZ,ZZ ;Check that each ac contains its own address
1471 STOP^
1472 031126 254 04 0 00 031127 HALT .+1 ;Test failed if program halts here
1473 031127 324 00 0 00 031130 JUMPA .+1 ;To loop change this instruction^
1474 ;In case of failure, loop to "c600" address
1475
1476 ;**********
1477
1478
1479 ;This test verifies that an address within the ac range may be accessed as
1480 ;Either an ac or a memory location and that either reference refers to the
1481 ;Same hardware. each ac is preloaded with its address. then the contents
1482 ;Of each ac is checked for its address. if any ac does not contain its
1483 ;Address, this test fails.
1484
1485 000612 SN=SN+1
1486 000006 ZZ=ZZ-1
1487 031130 302 06 0 00 000006 CAIE ZZ,ZZ ;Check that each ac contains its own address
1488 STOP^
1489 031131 254 04 0 00 031132 HALT .+1 ;Test failed if program halts here
1490 031132 324 00 0 00 031133 JUMPA .+1 ;To loop change this instruction^
1491 ;In case of failure, loop to "c600" address
1492
1493 ;**********
1494
1495
1496 ;This test verifies that an address within the ac range may be accessed as
1497 ;Either an ac or a memory location and that either reference refers to the
1498 ;Same hardware. each ac is preloaded with its address. then the contents
1499 ;Of each ac is checked for its address. if any ac does not contain its
1500 ;Address, this test fails.
1501
1502 000613 SN=SN+1
1503 000005 ZZ=ZZ-1
1504 031133 302 05 0 00 000005 CAIE ZZ,ZZ ;Check that each ac contains its own address
1505 STOP^
1506 031134 254 04 0 00 031135 HALT .+1 ;Test failed if program halts here
1507 031135 324 00 0 00 031136 JUMPA .+1 ;To loop change this instruction^
1508 ;In case of failure, loop to "c600" address
1509
1510 ;**********
1511
1512
1513 ;This test verifies that an address within the ac range may be accessed as
1514 ;Either an ac or a memory location and that either reference refers to the
1515 ;Same hardware. each ac is preloaded with its address. then the contents
1516 ;Of each ac is checked for its address. if any ac does not contain its
1517 ;Address, this test fails.
1518
1519 000614 SN=SN+1
1520 000004 ZZ=ZZ-1
1521 031136 302 04 0 00 000004 CAIE ZZ,ZZ ;Check that each ac contains its own address
1522 STOP^
1523 031137 254 04 0 00 031140 HALT .+1 ;Test failed if program halts here
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 5-5
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AC HARDWARE AND INDEX REGISTERS SEQ 0041
1524 031140 324 00 0 00 031141 JUMPA .+1 ;To loop change this instruction^
1525 ;In case of failure, loop to "c600" address
1526
1527 ;**********
1528
1529
1530 ;This test verifies that an address within the ac range may be accessed as
1531 ;Either an ac or a memory location and that either reference refers to the
1532 ;Same hardware. each ac is preloaded with its address. then the contents
1533 ;Of each ac is checked for its address. if any ac does not contain its
1534 ;Address, this test fails.
1535
1536 000615 SN=SN+1
1537 000003 ZZ=ZZ-1
1538 031141 302 03 0 00 000003 CAIE ZZ,ZZ ;Check that each ac contains its own address
1539 STOP^
1540 031142 254 04 0 00 031143 HALT .+1 ;Test failed if program halts here
1541 031143 324 00 0 00 031144 JUMPA .+1 ;To loop change this instruction^
1542 ;In case of failure, loop to "c600" address
1543
1544 ;**********
1545
1546
1547 ;This test verifies that an address within the ac range may be accessed as
1548 ;Either an ac or a memory location and that either reference refers to the
1549 ;Same hardware. each ac is preloaded with its address. then the contents
1550 ;Of each ac is checked for its address. if any ac does not contain its
1551 ;Address, this test fails.
1552
1553 000616 SN=SN+1
1554 000002 ZZ=ZZ-1
1555 031144 302 02 0 00 000002 CAIE ZZ,ZZ ;Check that each ac contains its own address
1556 STOP^
1557 031145 254 04 0 00 031146 HALT .+1 ;Test failed if program halts here
1558 031146 324 00 0 00 031147 JUMPA .+1 ;To loop change this instruction^
1559 ;In case of failure, loop to "c600" address
1560
1561 ;**********
1562
1563
1564 ;This test verifies that an address within the ac range may be accessed as
1565 ;Either an ac or a memory location and that either reference refers to the
1566 ;Same hardware. each ac is preloaded with its address. then the contents
1567 ;Of each ac is checked for its address. if any ac does not contain its
1568 ;Address, this test fails.
1569
1570 000617 SN=SN+1
1571 000001 ZZ=ZZ-1
1572 031147 302 01 0 00 000001 CAIE ZZ,ZZ ;Check that each ac contains its own address
1573 STOP^
1574 031150 254 04 0 00 031151 HALT .+1 ;Test failed if program halts here
1575 031151 324 00 0 00 031152 JUMPA .+1 ;To loop change this instruction^
1576 ;In case of failure, loop to "c600" address
1577
1578 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 5-6
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AC HARDWARE AND INDEX REGISTERS SEQ 0042
1579
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 6
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AC HARDWARE AND INDEX REGISTERS SEQ 0043
1580 000700 SN=700
1581 000000 ZZ=0
1582
1583 C700: REPEAT ^D15,<
1584 ;This test verifies that the index registers are accessable. first, an
1585 ;Index register is preloaded with its address. then, it is referenced
1586 ;As an index register. if it contains its address, this test passes.
1587 ;This test is repeated 15 times in order to test each index register.
1588
1589 SN=SN+1
1590 ZZ=ZZ+1
1591 MOVEI ZZ,ZZ ;Preload index register with its address
1592 CAIE ZZ,(ZZ) ;Pass if index register contains its address
1593 STOP
1594
1595 ;**********
1596 >
1597
1598 ;This test verifies that the index registers are accessable. first, an
1599 ;Index register is preloaded with its address. then, it is referenced
1600 ;As an index register. if it contains its address, this test passes.
1601 ;This test is repeated 15 times in order to test each index register.
1602
1603 000701 SN=SN+1
1604 000001 ZZ=ZZ+1
1605 031152 201 01 0 00 000001 MOVEI ZZ,ZZ ;Preload index register with its address
1606 031153 302 01 0 01 000000 CAIE ZZ,(ZZ) ;Pass if index register contains its address
1607 STOP^
1608 031154 254 04 0 00 031155 HALT .+1 ;Test failed if program halts here
1609 031155 324 00 0 00 031156 JUMPA .+1 ;To loop change this instruction^
1610
1611 ;**********
1612
1613
1614 ;This test verifies that the index registers are accessable. first, an
1615 ;Index register is preloaded with its address. then, it is referenced
1616 ;As an index register. if it contains its address, this test passes.
1617 ;This test is repeated 15 times in order to test each index register.
1618
1619 000702 SN=SN+1
1620 000002 ZZ=ZZ+1
1621 031156 201 02 0 00 000002 MOVEI ZZ,ZZ ;Preload index register with its address
1622 031157 302 02 0 02 000000 CAIE ZZ,(ZZ) ;Pass if index register contains its address
1623 STOP^
1624 031160 254 04 0 00 031161 HALT .+1 ;Test failed if program halts here
1625 031161 324 00 0 00 031162 JUMPA .+1 ;To loop change this instruction^
1626
1627 ;**********
1628
1629
1630 ;This test verifies that the index registers are accessable. first, an
1631 ;Index register is preloaded with its address. then, it is referenced
1632 ;As an index register. if it contains its address, this test passes.
1633 ;This test is repeated 15 times in order to test each index register.
1634
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 6-1
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AC HARDWARE AND INDEX REGISTERS SEQ 0044
1635 000703 SN=SN+1
1636 000003 ZZ=ZZ+1
1637 031162 201 03 0 00 000003 MOVEI ZZ,ZZ ;Preload index register with its address
1638 031163 302 03 0 03 000000 CAIE ZZ,(ZZ) ;Pass if index register contains its address
1639 STOP^
1640 031164 254 04 0 00 031165 HALT .+1 ;Test failed if program halts here
1641 031165 324 00 0 00 031166 JUMPA .+1 ;To loop change this instruction^
1642
1643 ;**********
1644
1645
1646 ;This test verifies that the index registers are accessable. first, an
1647 ;Index register is preloaded with its address. then, it is referenced
1648 ;As an index register. if it contains its address, this test passes.
1649 ;This test is repeated 15 times in order to test each index register.
1650
1651 000704 SN=SN+1
1652 000004 ZZ=ZZ+1
1653 031166 201 04 0 00 000004 MOVEI ZZ,ZZ ;Preload index register with its address
1654 031167 302 04 0 04 000000 CAIE ZZ,(ZZ) ;Pass if index register contains its address
1655 STOP^
1656 031170 254 04 0 00 031171 HALT .+1 ;Test failed if program halts here
1657 031171 324 00 0 00 031172 JUMPA .+1 ;To loop change this instruction^
1658
1659 ;**********
1660
1661
1662 ;This test verifies that the index registers are accessable. first, an
1663 ;Index register is preloaded with its address. then, it is referenced
1664 ;As an index register. if it contains its address, this test passes.
1665 ;This test is repeated 15 times in order to test each index register.
1666
1667 000705 SN=SN+1
1668 000005 ZZ=ZZ+1
1669 031172 201 05 0 00 000005 MOVEI ZZ,ZZ ;Preload index register with its address
1670 031173 302 05 0 05 000000 CAIE ZZ,(ZZ) ;Pass if index register contains its address
1671 STOP^
1672 031174 254 04 0 00 031175 HALT .+1 ;Test failed if program halts here
1673 031175 324 00 0 00 031176 JUMPA .+1 ;To loop change this instruction^
1674
1675 ;**********
1676
1677
1678 ;This test verifies that the index registers are accessable. first, an
1679 ;Index register is preloaded with its address. then, it is referenced
1680 ;As an index register. if it contains its address, this test passes.
1681 ;This test is repeated 15 times in order to test each index register.
1682
1683 000706 SN=SN+1
1684 000006 ZZ=ZZ+1
1685 031176 201 06 0 00 000006 MOVEI ZZ,ZZ ;Preload index register with its address
1686 031177 302 06 0 06 000000 CAIE ZZ,(ZZ) ;Pass if index register contains its address
1687 STOP^
1688 031200 254 04 0 00 031201 HALT .+1 ;Test failed if program halts here
1689 031201 324 00 0 00 031202 JUMPA .+1 ;To loop change this instruction^
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 6-2
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AC HARDWARE AND INDEX REGISTERS SEQ 0045
1690
1691 ;**********
1692
1693
1694 ;This test verifies that the index registers are accessable. first, an
1695 ;Index register is preloaded with its address. then, it is referenced
1696 ;As an index register. if it contains its address, this test passes.
1697 ;This test is repeated 15 times in order to test each index register.
1698
1699 000707 SN=SN+1
1700 000007 ZZ=ZZ+1
1701 031202 201 07 0 00 000007 MOVEI ZZ,ZZ ;Preload index register with its address
1702 031203 302 07 0 07 000000 CAIE ZZ,(ZZ) ;Pass if index register contains its address
1703 STOP^
1704 031204 254 04 0 00 031205 HALT .+1 ;Test failed if program halts here
1705 031205 324 00 0 00 031206 JUMPA .+1 ;To loop change this instruction^
1706
1707 ;**********
1708
1709
1710 ;This test verifies that the index registers are accessable. first, an
1711 ;Index register is preloaded with its address. then, it is referenced
1712 ;As an index register. if it contains its address, this test passes.
1713 ;This test is repeated 15 times in order to test each index register.
1714
1715 000710 SN=SN+1
1716 000010 ZZ=ZZ+1
1717 031206 201 10 0 00 000010 MOVEI ZZ,ZZ ;Preload index register with its address
1718 031207 302 10 0 10 000000 CAIE ZZ,(ZZ) ;Pass if index register contains its address
1719 STOP^
1720 031210 254 04 0 00 031211 HALT .+1 ;Test failed if program halts here
1721 031211 324 00 0 00 031212 JUMPA .+1 ;To loop change this instruction^
1722
1723 ;**********
1724
1725
1726 ;This test verifies that the index registers are accessable. first, an
1727 ;Index register is preloaded with its address. then, it is referenced
1728 ;As an index register. if it contains its address, this test passes.
1729 ;This test is repeated 15 times in order to test each index register.
1730
1731 000711 SN=SN+1
1732 000011 ZZ=ZZ+1
1733 031212 201 11 0 00 000011 MOVEI ZZ,ZZ ;Preload index register with its address
1734 031213 302 11 0 11 000000 CAIE ZZ,(ZZ) ;Pass if index register contains its address
1735 STOP^
1736 031214 254 04 0 00 031215 HALT .+1 ;Test failed if program halts here
1737 031215 324 00 0 00 031216 JUMPA .+1 ;To loop change this instruction^
1738
1739 ;**********
1740
1741
1742 ;This test verifies that the index registers are accessable. first, an
1743 ;Index register is preloaded with its address. then, it is referenced
1744 ;As an index register. if it contains its address, this test passes.
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 6-3
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AC HARDWARE AND INDEX REGISTERS SEQ 0046
1745 ;This test is repeated 15 times in order to test each index register.
1746
1747 000712 SN=SN+1
1748 000012 ZZ=ZZ+1
1749 031216 201 12 0 00 000012 MOVEI ZZ,ZZ ;Preload index register with its address
1750 031217 302 12 0 12 000000 CAIE ZZ,(ZZ) ;Pass if index register contains its address
1751 STOP^
1752 031220 254 04 0 00 031221 HALT .+1 ;Test failed if program halts here
1753 031221 324 00 0 00 031222 JUMPA .+1 ;To loop change this instruction^
1754
1755 ;**********
1756
1757
1758 ;This test verifies that the index registers are accessable. first, an
1759 ;Index register is preloaded with its address. then, it is referenced
1760 ;As an index register. if it contains its address, this test passes.
1761 ;This test is repeated 15 times in order to test each index register.
1762
1763 000713 SN=SN+1
1764 000013 ZZ=ZZ+1
1765 031222 201 13 0 00 000013 MOVEI ZZ,ZZ ;Preload index register with its address
1766 031223 302 13 0 13 000000 CAIE ZZ,(ZZ) ;Pass if index register contains its address
1767 STOP^
1768 031224 254 04 0 00 031225 HALT .+1 ;Test failed if program halts here
1769 031225 324 00 0 00 031226 JUMPA .+1 ;To loop change this instruction^
1770
1771 ;**********
1772
1773
1774 ;This test verifies that the index registers are accessable. first, an
1775 ;Index register is preloaded with its address. then, it is referenced
1776 ;As an index register. if it contains its address, this test passes.
1777 ;This test is repeated 15 times in order to test each index register.
1778
1779 000714 SN=SN+1
1780 000014 ZZ=ZZ+1
1781 031226 201 14 0 00 000014 MOVEI ZZ,ZZ ;Preload index register with its address
1782 031227 302 14 0 14 000000 CAIE ZZ,(ZZ) ;Pass if index register contains its address
1783 STOP^
1784 031230 254 04 0 00 031231 HALT .+1 ;Test failed if program halts here
1785 031231 324 00 0 00 031232 JUMPA .+1 ;To loop change this instruction^
1786
1787 ;**********
1788
1789
1790 ;This test verifies that the index registers are accessable. first, an
1791 ;Index register is preloaded with its address. then, it is referenced
1792 ;As an index register. if it contains its address, this test passes.
1793 ;This test is repeated 15 times in order to test each index register.
1794
1795 000715 SN=SN+1
1796 000015 ZZ=ZZ+1
1797 031232 201 15 0 00 000015 MOVEI ZZ,ZZ ;Preload index register with its address
1798 031233 302 15 0 15 000000 CAIE ZZ,(ZZ) ;Pass if index register contains its address
1799 STOP^
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 6-4
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AC HARDWARE AND INDEX REGISTERS SEQ 0047
1800 031234 254 04 0 00 031235 HALT .+1 ;Test failed if program halts here
1801 031235 324 00 0 00 031236 JUMPA .+1 ;To loop change this instruction^
1802
1803 ;**********
1804
1805
1806 ;This test verifies that the index registers are accessable. first, an
1807 ;Index register is preloaded with its address. then, it is referenced
1808 ;As an index register. if it contains its address, this test passes.
1809 ;This test is repeated 15 times in order to test each index register.
1810
1811 000716 SN=SN+1
1812 000016 ZZ=ZZ+1
1813 031236 201 16 0 00 000016 MOVEI ZZ,ZZ ;Preload index register with its address
1814 031237 302 16 0 16 000000 CAIE ZZ,(ZZ) ;Pass if index register contains its address
1815 STOP^
1816 031240 254 04 0 00 031241 HALT .+1 ;Test failed if program halts here
1817 031241 324 00 0 00 031242 JUMPA .+1 ;To loop change this instruction^
1818
1819 ;**********
1820
1821
1822 ;This test verifies that the index registers are accessable. first, an
1823 ;Index register is preloaded with its address. then, it is referenced
1824 ;As an index register. if it contains its address, this test passes.
1825 ;This test is repeated 15 times in order to test each index register.
1826
1827 000717 SN=SN+1
1828 000017 ZZ=ZZ+1
1829 031242 201 17 0 00 000017 MOVEI ZZ,ZZ ;Preload index register with its address
1830 031243 302 17 0 17 000000 CAIE ZZ,(ZZ) ;Pass if index register contains its address
1831 STOP^
1832 031244 254 04 0 00 031245 HALT .+1 ;Test failed if program halts here
1833 031245 324 00 0 00 031246 JUMPA .+1 ;To loop change this instruction^
1834
1835 ;**********
1836
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 7
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AC HARDWARE AND INDEX REGISTERS SEQ 0048
1837 001000 SN=1000
1838 000000 ZZ=0
1839
1840 C1000: REPEAT ^D15,<
1841 ;This test verifies that all index registers index correctly. first, both
1842 ;Halves of the index register are preloaded with its address. then, the
1843 ;Index register is referenced. it is then checked for its address in both
1844 ;Halves. if it contains its address in both halves this test passes.
1845 ;This test is repeated 15 times in order to test each index register.
1846
1847 SN=SN+1
1848 ZZ=ZZ+1
1849 MOVEI ZZ,ZZ ;Preload both halves of index reg with its address
1850 HRLI ZZ,ZZ ;Pass if index register contains its address
1851 CAME ZZ,(ZZ) ;In both halves
1852 STOP
1853
1854 ;**********
1855 >
1856
1857 ;This test verifies that all index registers index correctly. first, both
1858 ;Halves of the index register are preloaded with its address. then, the
1859 ;Index register is referenced. it is then checked for its address in both
1860 ;Halves. if it contains its address in both halves this test passes.
1861 ;This test is repeated 15 times in order to test each index register.
1862
1863 001001 SN=SN+1
1864 000001 ZZ=ZZ+1
1865 031246 201 01 0 00 000001 MOVEI ZZ,ZZ ;Preload both halves of index reg with its address
1866 031247 505 01 0 00 000001 HRLI ZZ,ZZ ;Pass if index register contains its address
1867 031250 312 01 0 01 000000 CAME ZZ,(ZZ) ;In both halves
1868 STOP^
1869 031251 254 04 0 00 031252 HALT .+1 ;Test failed if program halts here
1870 031252 324 00 0 00 031253 JUMPA .+1 ;To loop change this instruction^
1871
1872 ;**********
1873
1874
1875 ;This test verifies that all index registers index correctly. first, both
1876 ;Halves of the index register are preloaded with its address. then, the
1877 ;Index register is referenced. it is then checked for its address in both
1878 ;Halves. if it contains its address in both halves this test passes.
1879 ;This test is repeated 15 times in order to test each index register.
1880
1881 001002 SN=SN+1
1882 000002 ZZ=ZZ+1
1883 031253 201 02 0 00 000002 MOVEI ZZ,ZZ ;Preload both halves of index reg with its address
1884 031254 505 02 0 00 000002 HRLI ZZ,ZZ ;Pass if index register contains its address
1885 031255 312 02 0 02 000000 CAME ZZ,(ZZ) ;In both halves
1886 STOP^
1887 031256 254 04 0 00 031257 HALT .+1 ;Test failed if program halts here
1888 031257 324 00 0 00 031260 JUMPA .+1 ;To loop change this instruction^
1889
1890 ;**********
1891
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 7-1
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AC HARDWARE AND INDEX REGISTERS SEQ 0049
1892
1893 ;This test verifies that all index registers index correctly. first, both
1894 ;Halves of the index register are preloaded with its address. then, the
1895 ;Index register is referenced. it is then checked for its address in both
1896 ;Halves. if it contains its address in both halves this test passes.
1897 ;This test is repeated 15 times in order to test each index register.
1898
1899 001003 SN=SN+1
1900 000003 ZZ=ZZ+1
1901 031260 201 03 0 00 000003 MOVEI ZZ,ZZ ;Preload both halves of index reg with its address
1902 031261 505 03 0 00 000003 HRLI ZZ,ZZ ;Pass if index register contains its address
1903 031262 312 03 0 03 000000 CAME ZZ,(ZZ) ;In both halves
1904 STOP^
1905 031263 254 04 0 00 031264 HALT .+1 ;Test failed if program halts here
1906 031264 324 00 0 00 031265 JUMPA .+1 ;To loop change this instruction^
1907
1908 ;**********
1909
1910
1911 ;This test verifies that all index registers index correctly. first, both
1912 ;Halves of the index register are preloaded with its address. then, the
1913 ;Index register is referenced. it is then checked for its address in both
1914 ;Halves. if it contains its address in both halves this test passes.
1915 ;This test is repeated 15 times in order to test each index register.
1916
1917 001004 SN=SN+1
1918 000004 ZZ=ZZ+1
1919 031265 201 04 0 00 000004 MOVEI ZZ,ZZ ;Preload both halves of index reg with its address
1920 031266 505 04 0 00 000004 HRLI ZZ,ZZ ;Pass if index register contains its address
1921 031267 312 04 0 04 000000 CAME ZZ,(ZZ) ;In both halves
1922 STOP^
1923 031270 254 04 0 00 031271 HALT .+1 ;Test failed if program halts here
1924 031271 324 00 0 00 031272 JUMPA .+1 ;To loop change this instruction^
1925
1926 ;**********
1927
1928
1929 ;This test verifies that all index registers index correctly. first, both
1930 ;Halves of the index register are preloaded with its address. then, the
1931 ;Index register is referenced. it is then checked for its address in both
1932 ;Halves. if it contains its address in both halves this test passes.
1933 ;This test is repeated 15 times in order to test each index register.
1934
1935 001005 SN=SN+1
1936 000005 ZZ=ZZ+1
1937 031272 201 05 0 00 000005 MOVEI ZZ,ZZ ;Preload both halves of index reg with its address
1938 031273 505 05 0 00 000005 HRLI ZZ,ZZ ;Pass if index register contains its address
1939 031274 312 05 0 05 000000 CAME ZZ,(ZZ) ;In both halves
1940 STOP^
1941 031275 254 04 0 00 031276 HALT .+1 ;Test failed if program halts here
1942 031276 324 00 0 00 031277 JUMPA .+1 ;To loop change this instruction^
1943
1944 ;**********
1945
1946
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 7-2
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AC HARDWARE AND INDEX REGISTERS SEQ 0050
1947 ;This test verifies that all index registers index correctly. first, both
1948 ;Halves of the index register are preloaded with its address. then, the
1949 ;Index register is referenced. it is then checked for its address in both
1950 ;Halves. if it contains its address in both halves this test passes.
1951 ;This test is repeated 15 times in order to test each index register.
1952
1953 001006 SN=SN+1
1954 000006 ZZ=ZZ+1
1955 031277 201 06 0 00 000006 MOVEI ZZ,ZZ ;Preload both halves of index reg with its address
1956 031300 505 06 0 00 000006 HRLI ZZ,ZZ ;Pass if index register contains its address
1957 031301 312 06 0 06 000000 CAME ZZ,(ZZ) ;In both halves
1958 STOP^
1959 031302 254 04 0 00 031303 HALT .+1 ;Test failed if program halts here
1960 031303 324 00 0 00 031304 JUMPA .+1 ;To loop change this instruction^
1961
1962 ;**********
1963
1964
1965 ;This test verifies that all index registers index correctly. first, both
1966 ;Halves of the index register are preloaded with its address. then, the
1967 ;Index register is referenced. it is then checked for its address in both
1968 ;Halves. if it contains its address in both halves this test passes.
1969 ;This test is repeated 15 times in order to test each index register.
1970
1971 001007 SN=SN+1
1972 000007 ZZ=ZZ+1
1973 031304 201 07 0 00 000007 MOVEI ZZ,ZZ ;Preload both halves of index reg with its address
1974 031305 505 07 0 00 000007 HRLI ZZ,ZZ ;Pass if index register contains its address
1975 031306 312 07 0 07 000000 CAME ZZ,(ZZ) ;In both halves
1976 STOP^
1977 031307 254 04 0 00 031310 HALT .+1 ;Test failed if program halts here
1978 031310 324 00 0 00 031311 JUMPA .+1 ;To loop change this instruction^
1979
1980 ;**********
1981
1982
1983 ;This test verifies that all index registers index correctly. first, both
1984 ;Halves of the index register are preloaded with its address. then, the
1985 ;Index register is referenced. it is then checked for its address in both
1986 ;Halves. if it contains its address in both halves this test passes.
1987 ;This test is repeated 15 times in order to test each index register.
1988
1989 001010 SN=SN+1
1990 000010 ZZ=ZZ+1
1991 031311 201 10 0 00 000010 MOVEI ZZ,ZZ ;Preload both halves of index reg with its address
1992 031312 505 10 0 00 000010 HRLI ZZ,ZZ ;Pass if index register contains its address
1993 031313 312 10 0 10 000000 CAME ZZ,(ZZ) ;In both halves
1994 STOP^
1995 031314 254 04 0 00 031315 HALT .+1 ;Test failed if program halts here
1996 031315 324 00 0 00 031316 JUMPA .+1 ;To loop change this instruction^
1997
1998 ;**********
1999
2000
2001 ;This test verifies that all index registers index correctly. first, both
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 7-3
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AC HARDWARE AND INDEX REGISTERS SEQ 0051
2002 ;Halves of the index register are preloaded with its address. then, the
2003 ;Index register is referenced. it is then checked for its address in both
2004 ;Halves. if it contains its address in both halves this test passes.
2005 ;This test is repeated 15 times in order to test each index register.
2006
2007 001011 SN=SN+1
2008 000011 ZZ=ZZ+1
2009 031316 201 11 0 00 000011 MOVEI ZZ,ZZ ;Preload both halves of index reg with its address
2010 031317 505 11 0 00 000011 HRLI ZZ,ZZ ;Pass if index register contains its address
2011 031320 312 11 0 11 000000 CAME ZZ,(ZZ) ;In both halves
2012 STOP^
2013 031321 254 04 0 00 031322 HALT .+1 ;Test failed if program halts here
2014 031322 324 00 0 00 031323 JUMPA .+1 ;To loop change this instruction^
2015
2016 ;**********
2017
2018
2019 ;This test verifies that all index registers index correctly. first, both
2020 ;Halves of the index register are preloaded with its address. then, the
2021 ;Index register is referenced. it is then checked for its address in both
2022 ;Halves. if it contains its address in both halves this test passes.
2023 ;This test is repeated 15 times in order to test each index register.
2024
2025 001012 SN=SN+1
2026 000012 ZZ=ZZ+1
2027 031323 201 12 0 00 000012 MOVEI ZZ,ZZ ;Preload both halves of index reg with its address
2028 031324 505 12 0 00 000012 HRLI ZZ,ZZ ;Pass if index register contains its address
2029 031325 312 12 0 12 000000 CAME ZZ,(ZZ) ;In both halves
2030 STOP^
2031 031326 254 04 0 00 031327 HALT .+1 ;Test failed if program halts here
2032 031327 324 00 0 00 031330 JUMPA .+1 ;To loop change this instruction^
2033
2034 ;**********
2035
2036
2037 ;This test verifies that all index registers index correctly. first, both
2038 ;Halves of the index register are preloaded with its address. then, the
2039 ;Index register is referenced. it is then checked for its address in both
2040 ;Halves. if it contains its address in both halves this test passes.
2041 ;This test is repeated 15 times in order to test each index register.
2042
2043 001013 SN=SN+1
2044 000013 ZZ=ZZ+1
2045 031330 201 13 0 00 000013 MOVEI ZZ,ZZ ;Preload both halves of index reg with its address
2046 031331 505 13 0 00 000013 HRLI ZZ,ZZ ;Pass if index register contains its address
2047 031332 312 13 0 13 000000 CAME ZZ,(ZZ) ;In both halves
2048 STOP^
2049 031333 254 04 0 00 031334 HALT .+1 ;Test failed if program halts here
2050 031334 324 00 0 00 031335 JUMPA .+1 ;To loop change this instruction^
2051
2052 ;**********
2053
2054
2055 ;This test verifies that all index registers index correctly. first, both
2056 ;Halves of the index register are preloaded with its address. then, the
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 7-4
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AC HARDWARE AND INDEX REGISTERS SEQ 0052
2057 ;Index register is referenced. it is then checked for its address in both
2058 ;Halves. if it contains its address in both halves this test passes.
2059 ;This test is repeated 15 times in order to test each index register.
2060
2061 001014 SN=SN+1
2062 000014 ZZ=ZZ+1
2063 031335 201 14 0 00 000014 MOVEI ZZ,ZZ ;Preload both halves of index reg with its address
2064 031336 505 14 0 00 000014 HRLI ZZ,ZZ ;Pass if index register contains its address
2065 031337 312 14 0 14 000000 CAME ZZ,(ZZ) ;In both halves
2066 STOP^
2067 031340 254 04 0 00 031341 HALT .+1 ;Test failed if program halts here
2068 031341 324 00 0 00 031342 JUMPA .+1 ;To loop change this instruction^
2069
2070 ;**********
2071
2072
2073 ;This test verifies that all index registers index correctly. first, both
2074 ;Halves of the index register are preloaded with its address. then, the
2075 ;Index register is referenced. it is then checked for its address in both
2076 ;Halves. if it contains its address in both halves this test passes.
2077 ;This test is repeated 15 times in order to test each index register.
2078
2079 001015 SN=SN+1
2080 000015 ZZ=ZZ+1
2081 031342 201 15 0 00 000015 MOVEI ZZ,ZZ ;Preload both halves of index reg with its address
2082 031343 505 15 0 00 000015 HRLI ZZ,ZZ ;Pass if index register contains its address
2083 031344 312 15 0 15 000000 CAME ZZ,(ZZ) ;In both halves
2084 STOP^
2085 031345 254 04 0 00 031346 HALT .+1 ;Test failed if program halts here
2086 031346 324 00 0 00 031347 JUMPA .+1 ;To loop change this instruction^
2087
2088 ;**********
2089
2090
2091 ;This test verifies that all index registers index correctly. first, both
2092 ;Halves of the index register are preloaded with its address. then, the
2093 ;Index register is referenced. it is then checked for its address in both
2094 ;Halves. if it contains its address in both halves this test passes.
2095 ;This test is repeated 15 times in order to test each index register.
2096
2097 001016 SN=SN+1
2098 000016 ZZ=ZZ+1
2099 031347 201 16 0 00 000016 MOVEI ZZ,ZZ ;Preload both halves of index reg with its address
2100 031350 505 16 0 00 000016 HRLI ZZ,ZZ ;Pass if index register contains its address
2101 031351 312 16 0 16 000000 CAME ZZ,(ZZ) ;In both halves
2102 STOP^
2103 031352 254 04 0 00 031353 HALT .+1 ;Test failed if program halts here
2104 031353 324 00 0 00 031354 JUMPA .+1 ;To loop change this instruction^
2105
2106 ;**********
2107
2108
2109 ;This test verifies that all index registers index correctly. first, both
2110 ;Halves of the index register are preloaded with its address. then, the
2111 ;Index register is referenced. it is then checked for its address in both
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 7-5
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AC HARDWARE AND INDEX REGISTERS SEQ 0053
2112 ;Halves. if it contains its address in both halves this test passes.
2113 ;This test is repeated 15 times in order to test each index register.
2114
2115 001017 SN=SN+1
2116 000017 ZZ=ZZ+1
2117 031354 201 17 0 00 000017 MOVEI ZZ,ZZ ;Preload both halves of index reg with its address
2118 031355 505 17 0 00 000017 HRLI ZZ,ZZ ;Pass if index register contains its address
2119 031356 312 17 0 17 000000 CAME ZZ,(ZZ) ;In both halves
2120 STOP^
2121 031357 254 04 0 00 031360 HALT .+1 ;Test failed if program halts here
2122 031360 324 00 0 00 031361 JUMPA .+1 ;To loop change this instruction^
2123
2124 ;**********
2125
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 8
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0054
2126 SUBTTL TEST OF INDEX REGISTER ADDRESSING
2127
2128 ;**********
2129
2130 ;This test verifies that index register addressing functions correctly.
2131 ;In this test, a move instruction using indexing is executed. the move
2132 ;Instruction should place the contents of the location specified by index
2133 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2134 ;Ac1 was preloaded with a 0, the final result in ac3 should be 0. if
2135 ;C(ac3)=0, this test passes.
2136
2137 031361 476 00 0 00 000003 C1100: SETOM 3 ;Preload ac3 with -1,,1
2138 031362 402 00 0 00 000001 SETZM 1 ;Preload ac1 with 0
2139 031363 201 02 0 00 000001 MOVEI 2,1 ;Setup index register 2 with 1
2140 031364 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2141 031365 332 00 0 00 000003 SKIPE 3 ;Test indexing
2142 STOP^
2143 031366 254 04 0 00 031367 HALT .+1 ;Test failed if program halts here
2144 031367 324 00 0 00 031370 JUMPA .+1 ;To loop change this instruction^
2145
2146 ;**********
2147
2148 001200 SN=1200
2149 000000 ZZ=0
2150
2151 C1200: REPEAT ^D18,<
2152 ;This test verifies that index register addressing functions correctly.
2153 ;In this test, a move instruction using indexing is executed. the move
2154 ;Instruction should place the contents of the location specified by index
2155 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2156 ;Ac1 was preloaded with a floating 1. the final result in ac3 should be a
2157 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2158
2159 SN=SN+1
2160 ZZ=ZZ+ZZ
2161 IFE ZZ,<ZZ=1>
2162 SETOM 3 ;Preload ac3 with -1,,-1
2163 MOVEI 1,ZZ ;Preload ac1 with floating 1
2164 MOVEI 2,1 ;Setup index register
2165 MOVE 3,(2) ;*Fwt from indexed location
2166 CAIE 3,ZZ ;Test indexing
2167 STOP
2168
2169 ;**********
2170 >
2171
2172 ;This test verifies that index register addressing functions correctly.
2173 ;In this test, a move instruction using indexing is executed. the move
2174 ;Instruction should place the contents of the location specified by index
2175 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2176 ;Ac1 was preloaded with a floating 1. the final result in ac3 should be a
2177 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2178
2179 001201 SN=SN+1
2180 000000 ZZ=ZZ+ZZ
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 8-1
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0055
2181 000001 IFE ZZ,<ZZ=1>
2182 031370 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2183 031371 201 01 0 00 000001 MOVEI 1,ZZ ;Preload ac1 with floating 1
2184 031372 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2185 031373 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2186 031374 302 03 0 00 000001 CAIE 3,ZZ ;Test indexing
2187 STOP^
2188 031375 254 04 0 00 031376 HALT .+1 ;Test failed if program halts here
2189 031376 324 00 0 00 031377 JUMPA .+1 ;To loop change this instruction^
2190
2191 ;**********
2192
2193
2194 ;This test verifies that index register addressing functions correctly.
2195 ;In this test, a move instruction using indexing is executed. the move
2196 ;Instruction should place the contents of the location specified by index
2197 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2198 ;Ac1 was preloaded with a floating 1. the final result in ac3 should be a
2199 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2200
2201 001202 SN=SN+1
2202 000002 ZZ=ZZ+ZZ
2203 IFE ZZ,<ZZ=1>
2204 031377 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2205 031400 201 01 0 00 000002 MOVEI 1,ZZ ;Preload ac1 with floating 1
2206 031401 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2207 031402 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2208 031403 302 03 0 00 000002 CAIE 3,ZZ ;Test indexing
2209 STOP^
2210 031404 254 04 0 00 031405 HALT .+1 ;Test failed if program halts here
2211 031405 324 00 0 00 031406 JUMPA .+1 ;To loop change this instruction^
2212
2213 ;**********
2214
2215
2216 ;This test verifies that index register addressing functions correctly.
2217 ;In this test, a move instruction using indexing is executed. the move
2218 ;Instruction should place the contents of the location specified by index
2219 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2220 ;Ac1 was preloaded with a floating 1. the final result in ac3 should be a
2221 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2222
2223 001203 SN=SN+1
2224 000004 ZZ=ZZ+ZZ
2225 IFE ZZ,<ZZ=1>
2226 031406 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2227 031407 201 01 0 00 000004 MOVEI 1,ZZ ;Preload ac1 with floating 1
2228 031410 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2229 031411 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2230 031412 302 03 0 00 000004 CAIE 3,ZZ ;Test indexing
2231 STOP^
2232 031413 254 04 0 00 031414 HALT .+1 ;Test failed if program halts here
2233 031414 324 00 0 00 031415 JUMPA .+1 ;To loop change this instruction^
2234
2235 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 8-2
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0056
2236
2237
2238 ;This test verifies that index register addressing functions correctly.
2239 ;In this test, a move instruction using indexing is executed. the move
2240 ;Instruction should place the contents of the location specified by index
2241 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2242 ;Ac1 was preloaded with a floating 1. the final result in ac3 should be a
2243 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2244
2245 001204 SN=SN+1
2246 000010 ZZ=ZZ+ZZ
2247 IFE ZZ,<ZZ=1>
2248 031415 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2249 031416 201 01 0 00 000010 MOVEI 1,ZZ ;Preload ac1 with floating 1
2250 031417 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2251 031420 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2252 031421 302 03 0 00 000010 CAIE 3,ZZ ;Test indexing
2253 STOP^
2254 031422 254 04 0 00 031423 HALT .+1 ;Test failed if program halts here
2255 031423 324 00 0 00 031424 JUMPA .+1 ;To loop change this instruction^
2256
2257 ;**********
2258
2259
2260 ;This test verifies that index register addressing functions correctly.
2261 ;In this test, a move instruction using indexing is executed. the move
2262 ;Instruction should place the contents of the location specified by index
2263 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2264 ;Ac1 was preloaded with a floating 1. the final result in ac3 should be a
2265 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2266
2267 001205 SN=SN+1
2268 000020 ZZ=ZZ+ZZ
2269 IFE ZZ,<ZZ=1>
2270 031424 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2271 031425 201 01 0 00 000020 MOVEI 1,ZZ ;Preload ac1 with floating 1
2272 031426 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2273 031427 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2274 031430 302 03 0 00 000020 CAIE 3,ZZ ;Test indexing
2275 STOP^
2276 031431 254 04 0 00 031432 HALT .+1 ;Test failed if program halts here
2277 031432 324 00 0 00 031433 JUMPA .+1 ;To loop change this instruction^
2278
2279 ;**********
2280
2281
2282 ;This test verifies that index register addressing functions correctly.
2283 ;In this test, a move instruction using indexing is executed. the move
2284 ;Instruction should place the contents of the location specified by index
2285 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2286 ;Ac1 was preloaded with a floating 1. the final result in ac3 should be a
2287 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2288
2289 001206 SN=SN+1
2290 000040 ZZ=ZZ+ZZ
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 8-3
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0057
2291 IFE ZZ,<ZZ=1>
2292 031433 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2293 031434 201 01 0 00 000040 MOVEI 1,ZZ ;Preload ac1 with floating 1
2294 031435 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2295 031436 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2296 031437 302 03 0 00 000040 CAIE 3,ZZ ;Test indexing
2297 STOP^
2298 031440 254 04 0 00 031441 HALT .+1 ;Test failed if program halts here
2299 031441 324 00 0 00 031442 JUMPA .+1 ;To loop change this instruction^
2300
2301 ;**********
2302
2303
2304 ;This test verifies that index register addressing functions correctly.
2305 ;In this test, a move instruction using indexing is executed. the move
2306 ;Instruction should place the contents of the location specified by index
2307 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2308 ;Ac1 was preloaded with a floating 1. the final result in ac3 should be a
2309 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2310
2311 001207 SN=SN+1
2312 000100 ZZ=ZZ+ZZ
2313 IFE ZZ,<ZZ=1>
2314 031442 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2315 031443 201 01 0 00 000100 MOVEI 1,ZZ ;Preload ac1 with floating 1
2316 031444 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2317 031445 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2318 031446 302 03 0 00 000100 CAIE 3,ZZ ;Test indexing
2319 STOP^
2320 031447 254 04 0 00 031450 HALT .+1 ;Test failed if program halts here
2321 031450 324 00 0 00 031451 JUMPA .+1 ;To loop change this instruction^
2322
2323 ;**********
2324
2325
2326 ;This test verifies that index register addressing functions correctly.
2327 ;In this test, a move instruction using indexing is executed. the move
2328 ;Instruction should place the contents of the location specified by index
2329 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2330 ;Ac1 was preloaded with a floating 1. the final result in ac3 should be a
2331 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2332
2333 001210 SN=SN+1
2334 000200 ZZ=ZZ+ZZ
2335 IFE ZZ,<ZZ=1>
2336 031451 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2337 031452 201 01 0 00 000200 MOVEI 1,ZZ ;Preload ac1 with floating 1
2338 031453 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2339 031454 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2340 031455 302 03 0 00 000200 CAIE 3,ZZ ;Test indexing
2341 STOP^
2342 031456 254 04 0 00 031457 HALT .+1 ;Test failed if program halts here
2343 031457 324 00 0 00 031460 JUMPA .+1 ;To loop change this instruction^
2344
2345 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 8-4
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0058
2346
2347
2348 ;This test verifies that index register addressing functions correctly.
2349 ;In this test, a move instruction using indexing is executed. the move
2350 ;Instruction should place the contents of the location specified by index
2351 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2352 ;Ac1 was preloaded with a floating 1. the final result in ac3 should be a
2353 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2354
2355 001211 SN=SN+1
2356 000400 ZZ=ZZ+ZZ
2357 IFE ZZ,<ZZ=1>
2358 031460 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2359 031461 201 01 0 00 000400 MOVEI 1,ZZ ;Preload ac1 with floating 1
2360 031462 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2361 031463 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2362 031464 302 03 0 00 000400 CAIE 3,ZZ ;Test indexing
2363 STOP^
2364 031465 254 04 0 00 031466 HALT .+1 ;Test failed if program halts here
2365 031466 324 00 0 00 031467 JUMPA .+1 ;To loop change this instruction^
2366
2367 ;**********
2368
2369
2370 ;This test verifies that index register addressing functions correctly.
2371 ;In this test, a move instruction using indexing is executed. the move
2372 ;Instruction should place the contents of the location specified by index
2373 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2374 ;Ac1 was preloaded with a floating 1. the final result in ac3 should be a
2375 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2376
2377 001212 SN=SN+1
2378 001000 ZZ=ZZ+ZZ
2379 IFE ZZ,<ZZ=1>
2380 031467 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2381 031470 201 01 0 00 001000 MOVEI 1,ZZ ;Preload ac1 with floating 1
2382 031471 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2383 031472 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2384 031473 302 03 0 00 001000 CAIE 3,ZZ ;Test indexing
2385 STOP^
2386 031474 254 04 0 00 031475 HALT .+1 ;Test failed if program halts here
2387 031475 324 00 0 00 031476 JUMPA .+1 ;To loop change this instruction^
2388
2389 ;**********
2390
2391
2392 ;This test verifies that index register addressing functions correctly.
2393 ;In this test, a move instruction using indexing is executed. the move
2394 ;Instruction should place the contents of the location specified by index
2395 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2396 ;Ac1 was preloaded with a floating 1. the final result in ac3 should be a
2397 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2398
2399 001213 SN=SN+1
2400 002000 ZZ=ZZ+ZZ
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 8-5
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0059
2401 IFE ZZ,<ZZ=1>
2402 031476 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2403 031477 201 01 0 00 002000 MOVEI 1,ZZ ;Preload ac1 with floating 1
2404 031500 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2405 031501 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2406 031502 302 03 0 00 002000 CAIE 3,ZZ ;Test indexing
2407 STOP^
2408 031503 254 04 0 00 031504 HALT .+1 ;Test failed if program halts here
2409 031504 324 00 0 00 031505 JUMPA .+1 ;To loop change this instruction^
2410
2411 ;**********
2412
2413
2414 ;This test verifies that index register addressing functions correctly.
2415 ;In this test, a move instruction using indexing is executed. the move
2416 ;Instruction should place the contents of the location specified by index
2417 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2418 ;Ac1 was preloaded with a floating 1. the final result in ac3 should be a
2419 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2420
2421 001214 SN=SN+1
2422 004000 ZZ=ZZ+ZZ
2423 IFE ZZ,<ZZ=1>
2424 031505 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2425 031506 201 01 0 00 004000 MOVEI 1,ZZ ;Preload ac1 with floating 1
2426 031507 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2427 031510 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2428 031511 302 03 0 00 004000 CAIE 3,ZZ ;Test indexing
2429 STOP^
2430 031512 254 04 0 00 031513 HALT .+1 ;Test failed if program halts here
2431 031513 324 00 0 00 031514 JUMPA .+1 ;To loop change this instruction^
2432
2433 ;**********
2434
2435
2436 ;This test verifies that index register addressing functions correctly.
2437 ;In this test, a move instruction using indexing is executed. the move
2438 ;Instruction should place the contents of the location specified by index
2439 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2440 ;Ac1 was preloaded with a floating 1. the final result in ac3 should be a
2441 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2442
2443 001215 SN=SN+1
2444 010000 ZZ=ZZ+ZZ
2445 IFE ZZ,<ZZ=1>
2446 031514 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2447 031515 201 01 0 00 010000 MOVEI 1,ZZ ;Preload ac1 with floating 1
2448 031516 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2449 031517 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2450 031520 302 03 0 00 010000 CAIE 3,ZZ ;Test indexing
2451 STOP^
2452 031521 254 04 0 00 031522 HALT .+1 ;Test failed if program halts here
2453 031522 324 00 0 00 031523 JUMPA .+1 ;To loop change this instruction^
2454
2455 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 8-6
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0060
2456
2457
2458 ;This test verifies that index register addressing functions correctly.
2459 ;In this test, a move instruction using indexing is executed. the move
2460 ;Instruction should place the contents of the location specified by index
2461 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2462 ;Ac1 was preloaded with a floating 1. the final result in ac3 should be a
2463 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2464
2465 001216 SN=SN+1
2466 020000 ZZ=ZZ+ZZ
2467 IFE ZZ,<ZZ=1>
2468 031523 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2469 031524 201 01 0 00 020000 MOVEI 1,ZZ ;Preload ac1 with floating 1
2470 031525 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2471 031526 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2472 031527 302 03 0 00 020000 CAIE 3,ZZ ;Test indexing
2473 STOP^
2474 031530 254 04 0 00 031531 HALT .+1 ;Test failed if program halts here
2475 031531 324 00 0 00 031532 JUMPA .+1 ;To loop change this instruction^
2476
2477 ;**********
2478
2479
2480 ;This test verifies that index register addressing functions correctly.
2481 ;In this test, a move instruction using indexing is executed. the move
2482 ;Instruction should place the contents of the location specified by index
2483 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2484 ;Ac1 was preloaded with a floating 1. the final result in ac3 should be a
2485 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2486
2487 001217 SN=SN+1
2488 040000 ZZ=ZZ+ZZ
2489 IFE ZZ,<ZZ=1>
2490 031532 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2491 031533 201 01 0 00 040000 MOVEI 1,ZZ ;Preload ac1 with floating 1
2492 031534 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2493 031535 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2494 031536 302 03 0 00 040000 CAIE 3,ZZ ;Test indexing
2495 STOP^
2496 031537 254 04 0 00 031540 HALT .+1 ;Test failed if program halts here
2497 031540 324 00 0 00 031541 JUMPA .+1 ;To loop change this instruction^
2498
2499 ;**********
2500
2501
2502 ;This test verifies that index register addressing functions correctly.
2503 ;In this test, a move instruction using indexing is executed. the move
2504 ;Instruction should place the contents of the location specified by index
2505 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2506 ;Ac1 was preloaded with a floating 1. the final result in ac3 should be a
2507 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2508
2509 001220 SN=SN+1
2510 100000 ZZ=ZZ+ZZ
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 8-7
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0061
2511 IFE ZZ,<ZZ=1>
2512 031541 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2513 031542 201 01 0 00 100000 MOVEI 1,ZZ ;Preload ac1 with floating 1
2514 031543 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2515 031544 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2516 031545 302 03 0 00 100000 CAIE 3,ZZ ;Test indexing
2517 STOP^
2518 031546 254 04 0 00 031547 HALT .+1 ;Test failed if program halts here
2519 031547 324 00 0 00 031550 JUMPA .+1 ;To loop change this instruction^
2520
2521 ;**********
2522
2523
2524 ;This test verifies that index register addressing functions correctly.
2525 ;In this test, a move instruction using indexing is executed. the move
2526 ;Instruction should place the contents of the location specified by index
2527 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2528 ;Ac1 was preloaded with a floating 1. the final result in ac3 should be a
2529 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2530
2531 001221 SN=SN+1
2532 200000 ZZ=ZZ+ZZ
2533 IFE ZZ,<ZZ=1>
2534 031550 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2535 031551 201 01 0 00 200000 MOVEI 1,ZZ ;Preload ac1 with floating 1
2536 031552 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2537 031553 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2538 031554 302 03 0 00 200000 CAIE 3,ZZ ;Test indexing
2539 STOP^
2540 031555 254 04 0 00 031556 HALT .+1 ;Test failed if program halts here
2541 031556 324 00 0 00 031557 JUMPA .+1 ;To loop change this instruction^
2542
2543 ;**********
2544
2545
2546 ;This test verifies that index register addressing functions correctly.
2547 ;In this test, a move instruction using indexing is executed. the move
2548 ;Instruction should place the contents of the location specified by index
2549 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2550 ;Ac1 was preloaded with a floating 1. the final result in ac3 should be a
2551 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2552
2553 001222 SN=SN+1
2554 400000 ZZ=ZZ+ZZ
2555 IFE ZZ,<ZZ=1>
2556 031557 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2557 031560 201 01 0 00 400000 MOVEI 1,ZZ ;Preload ac1 with floating 1
2558 031561 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2559 031562 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2560 031563 302 03 0 00 400000 CAIE 3,ZZ ;Test indexing
2561 STOP^
2562 031564 254 04 0 00 031565 HALT .+1 ;Test failed if program halts here
2563 031565 324 00 0 00 031566 JUMPA .+1 ;To loop change this instruction^
2564
2565 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 8-8
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0062
2566
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 9
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0063
2567 001300 SN=1300
2568 000000 ZZ=0
2569
2570 C1300: REPEAT ^D18,<
2571 ;This test verifies that index register addressing functions correctly.
2572 ;In this test, a move instruction using indexing is executed. the move
2573 ;Instruction should place the contents of the location specified by index
2574 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2575 ;Ac1 was preloaded with a floating 1, the final result in ac3 should be a
2576 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2577
2578 SN=SN+1
2579 ZZ=ZZ+ZZ
2580 IFE ZZ,<ZZ=1>
2581 SETOM 3 ;Preload ac3 with -1,,-1
2582 MOVSI 1,ZZ ;Preload ac1 with floating 1
2583 MOVEI 2,1 ;Setup index register
2584 MOVE 3,(2) ;*Fwt from indexed location
2585 CAME 3,[ZZ,,0] ;Test indexing
2586 STOP
2587
2588 ;**********
2589 >
2590
2591 ;This test verifies that index register addressing functions correctly.
2592 ;In this test, a move instruction using indexing is executed. the move
2593 ;Instruction should place the contents of the location specified by index
2594 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2595 ;Ac1 was preloaded with a floating 1, the final result in ac3 should be a
2596 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2597
2598 001301 SN=SN+1
2599 000000 ZZ=ZZ+ZZ
2600 000001 IFE ZZ,<ZZ=1>
2601 031566 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2602 031567 205 01 0 00 000001 MOVSI 1,ZZ ;Preload ac1 with floating 1
2603 031570 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2604 031571 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2605 031572 312 03 0 00 034421 CAME 3,[ZZ,,0] ;Test indexing
2606 STOP^
2607 031573 254 04 0 00 031574 HALT .+1 ;Test failed if program halts here
2608 031574 324 00 0 00 031575 JUMPA .+1 ;To loop change this instruction^
2609
2610 ;**********
2611
2612
2613 ;This test verifies that index register addressing functions correctly.
2614 ;In this test, a move instruction using indexing is executed. the move
2615 ;Instruction should place the contents of the location specified by index
2616 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2617 ;Ac1 was preloaded with a floating 1, the final result in ac3 should be a
2618 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2619
2620 001302 SN=SN+1
2621 000002 ZZ=ZZ+ZZ
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 9-1
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0064
2622 IFE ZZ,<ZZ=1>
2623 031575 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2624 031576 205 01 0 00 000002 MOVSI 1,ZZ ;Preload ac1 with floating 1
2625 031577 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2626 031600 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2627 031601 312 03 0 00 034422 CAME 3,[ZZ,,0] ;Test indexing
2628 STOP^
2629 031602 254 04 0 00 031603 HALT .+1 ;Test failed if program halts here
2630 031603 324 00 0 00 031604 JUMPA .+1 ;To loop change this instruction^
2631
2632 ;**********
2633
2634
2635 ;This test verifies that index register addressing functions correctly.
2636 ;In this test, a move instruction using indexing is executed. the move
2637 ;Instruction should place the contents of the location specified by index
2638 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2639 ;Ac1 was preloaded with a floating 1, the final result in ac3 should be a
2640 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2641
2642 001303 SN=SN+1
2643 000004 ZZ=ZZ+ZZ
2644 IFE ZZ,<ZZ=1>
2645 031604 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2646 031605 205 01 0 00 000004 MOVSI 1,ZZ ;Preload ac1 with floating 1
2647 031606 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2648 031607 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2649 031610 312 03 0 00 034423 CAME 3,[ZZ,,0] ;Test indexing
2650 STOP^
2651 031611 254 04 0 00 031612 HALT .+1 ;Test failed if program halts here
2652 031612 324 00 0 00 031613 JUMPA .+1 ;To loop change this instruction^
2653
2654 ;**********
2655
2656
2657 ;This test verifies that index register addressing functions correctly.
2658 ;In this test, a move instruction using indexing is executed. the move
2659 ;Instruction should place the contents of the location specified by index
2660 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2661 ;Ac1 was preloaded with a floating 1, the final result in ac3 should be a
2662 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2663
2664 001304 SN=SN+1
2665 000010 ZZ=ZZ+ZZ
2666 IFE ZZ,<ZZ=1>
2667 031613 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2668 031614 205 01 0 00 000010 MOVSI 1,ZZ ;Preload ac1 with floating 1
2669 031615 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2670 031616 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2671 031617 312 03 0 00 034424 CAME 3,[ZZ,,0] ;Test indexing
2672 STOP^
2673 031620 254 04 0 00 031621 HALT .+1 ;Test failed if program halts here
2674 031621 324 00 0 00 031622 JUMPA .+1 ;To loop change this instruction^
2675
2676 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 9-2
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0065
2677
2678
2679 ;This test verifies that index register addressing functions correctly.
2680 ;In this test, a move instruction using indexing is executed. the move
2681 ;Instruction should place the contents of the location specified by index
2682 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2683 ;Ac1 was preloaded with a floating 1, the final result in ac3 should be a
2684 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2685
2686 001305 SN=SN+1
2687 000020 ZZ=ZZ+ZZ
2688 IFE ZZ,<ZZ=1>
2689 031622 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2690 031623 205 01 0 00 000020 MOVSI 1,ZZ ;Preload ac1 with floating 1
2691 031624 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2692 031625 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2693 031626 312 03 0 00 034425 CAME 3,[ZZ,,0] ;Test indexing
2694 STOP^
2695 031627 254 04 0 00 031630 HALT .+1 ;Test failed if program halts here
2696 031630 324 00 0 00 031631 JUMPA .+1 ;To loop change this instruction^
2697
2698 ;**********
2699
2700
2701 ;This test verifies that index register addressing functions correctly.
2702 ;In this test, a move instruction using indexing is executed. the move
2703 ;Instruction should place the contents of the location specified by index
2704 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2705 ;Ac1 was preloaded with a floating 1, the final result in ac3 should be a
2706 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2707
2708 001306 SN=SN+1
2709 000040 ZZ=ZZ+ZZ
2710 IFE ZZ,<ZZ=1>
2711 031631 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2712 031632 205 01 0 00 000040 MOVSI 1,ZZ ;Preload ac1 with floating 1
2713 031633 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2714 031634 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2715 031635 312 03 0 00 034426 CAME 3,[ZZ,,0] ;Test indexing
2716 STOP^
2717 031636 254 04 0 00 031637 HALT .+1 ;Test failed if program halts here
2718 031637 324 00 0 00 031640 JUMPA .+1 ;To loop change this instruction^
2719
2720 ;**********
2721
2722
2723 ;This test verifies that index register addressing functions correctly.
2724 ;In this test, a move instruction using indexing is executed. the move
2725 ;Instruction should place the contents of the location specified by index
2726 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2727 ;Ac1 was preloaded with a floating 1, the final result in ac3 should be a
2728 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2729
2730 001307 SN=SN+1
2731 000100 ZZ=ZZ+ZZ
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 9-3
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0066
2732 IFE ZZ,<ZZ=1>
2733 031640 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2734 031641 205 01 0 00 000100 MOVSI 1,ZZ ;Preload ac1 with floating 1
2735 031642 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2736 031643 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2737 031644 312 03 0 00 034427 CAME 3,[ZZ,,0] ;Test indexing
2738 STOP^
2739 031645 254 04 0 00 031646 HALT .+1 ;Test failed if program halts here
2740 031646 324 00 0 00 031647 JUMPA .+1 ;To loop change this instruction^
2741
2742 ;**********
2743
2744
2745 ;This test verifies that index register addressing functions correctly.
2746 ;In this test, a move instruction using indexing is executed. the move
2747 ;Instruction should place the contents of the location specified by index
2748 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2749 ;Ac1 was preloaded with a floating 1, the final result in ac3 should be a
2750 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2751
2752 001310 SN=SN+1
2753 000200 ZZ=ZZ+ZZ
2754 IFE ZZ,<ZZ=1>
2755 031647 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2756 031650 205 01 0 00 000200 MOVSI 1,ZZ ;Preload ac1 with floating 1
2757 031651 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2758 031652 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2759 031653 312 03 0 00 034430 CAME 3,[ZZ,,0] ;Test indexing
2760 STOP^
2761 031654 254 04 0 00 031655 HALT .+1 ;Test failed if program halts here
2762 031655 324 00 0 00 031656 JUMPA .+1 ;To loop change this instruction^
2763
2764 ;**********
2765
2766
2767 ;This test verifies that index register addressing functions correctly.
2768 ;In this test, a move instruction using indexing is executed. the move
2769 ;Instruction should place the contents of the location specified by index
2770 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2771 ;Ac1 was preloaded with a floating 1, the final result in ac3 should be a
2772 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2773
2774 001311 SN=SN+1
2775 000400 ZZ=ZZ+ZZ
2776 IFE ZZ,<ZZ=1>
2777 031656 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2778 031657 205 01 0 00 000400 MOVSI 1,ZZ ;Preload ac1 with floating 1
2779 031660 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2780 031661 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2781 031662 312 03 0 00 034431 CAME 3,[ZZ,,0] ;Test indexing
2782 STOP^
2783 031663 254 04 0 00 031664 HALT .+1 ;Test failed if program halts here
2784 031664 324 00 0 00 031665 JUMPA .+1 ;To loop change this instruction^
2785
2786 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 9-4
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0067
2787
2788
2789 ;This test verifies that index register addressing functions correctly.
2790 ;In this test, a move instruction using indexing is executed. the move
2791 ;Instruction should place the contents of the location specified by index
2792 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2793 ;Ac1 was preloaded with a floating 1, the final result in ac3 should be a
2794 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2795
2796 001312 SN=SN+1
2797 001000 ZZ=ZZ+ZZ
2798 IFE ZZ,<ZZ=1>
2799 031665 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2800 031666 205 01 0 00 001000 MOVSI 1,ZZ ;Preload ac1 with floating 1
2801 031667 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2802 031670 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2803 031671 312 03 0 00 034432 CAME 3,[ZZ,,0] ;Test indexing
2804 STOP^
2805 031672 254 04 0 00 031673 HALT .+1 ;Test failed if program halts here
2806 031673 324 00 0 00 031674 JUMPA .+1 ;To loop change this instruction^
2807
2808 ;**********
2809
2810
2811 ;This test verifies that index register addressing functions correctly.
2812 ;In this test, a move instruction using indexing is executed. the move
2813 ;Instruction should place the contents of the location specified by index
2814 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2815 ;Ac1 was preloaded with a floating 1, the final result in ac3 should be a
2816 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2817
2818 001313 SN=SN+1
2819 002000 ZZ=ZZ+ZZ
2820 IFE ZZ,<ZZ=1>
2821 031674 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2822 031675 205 01 0 00 002000 MOVSI 1,ZZ ;Preload ac1 with floating 1
2823 031676 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2824 031677 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2825 031700 312 03 0 00 034433 CAME 3,[ZZ,,0] ;Test indexing
2826 STOP^
2827 031701 254 04 0 00 031702 HALT .+1 ;Test failed if program halts here
2828 031702 324 00 0 00 031703 JUMPA .+1 ;To loop change this instruction^
2829
2830 ;**********
2831
2832
2833 ;This test verifies that index register addressing functions correctly.
2834 ;In this test, a move instruction using indexing is executed. the move
2835 ;Instruction should place the contents of the location specified by index
2836 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2837 ;Ac1 was preloaded with a floating 1, the final result in ac3 should be a
2838 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2839
2840 001314 SN=SN+1
2841 004000 ZZ=ZZ+ZZ
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 9-5
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0068
2842 IFE ZZ,<ZZ=1>
2843 031703 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2844 031704 205 01 0 00 004000 MOVSI 1,ZZ ;Preload ac1 with floating 1
2845 031705 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2846 031706 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2847 031707 312 03 0 00 034434 CAME 3,[ZZ,,0] ;Test indexing
2848 STOP^
2849 031710 254 04 0 00 031711 HALT .+1 ;Test failed if program halts here
2850 031711 324 00 0 00 031712 JUMPA .+1 ;To loop change this instruction^
2851
2852 ;**********
2853
2854
2855 ;This test verifies that index register addressing functions correctly.
2856 ;In this test, a move instruction using indexing is executed. the move
2857 ;Instruction should place the contents of the location specified by index
2858 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2859 ;Ac1 was preloaded with a floating 1, the final result in ac3 should be a
2860 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2861
2862 001315 SN=SN+1
2863 010000 ZZ=ZZ+ZZ
2864 IFE ZZ,<ZZ=1>
2865 031712 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2866 031713 205 01 0 00 010000 MOVSI 1,ZZ ;Preload ac1 with floating 1
2867 031714 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2868 031715 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2869 031716 312 03 0 00 034435 CAME 3,[ZZ,,0] ;Test indexing
2870 STOP^
2871 031717 254 04 0 00 031720 HALT .+1 ;Test failed if program halts here
2872 031720 324 00 0 00 031721 JUMPA .+1 ;To loop change this instruction^
2873
2874 ;**********
2875
2876
2877 ;This test verifies that index register addressing functions correctly.
2878 ;In this test, a move instruction using indexing is executed. the move
2879 ;Instruction should place the contents of the location specified by index
2880 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2881 ;Ac1 was preloaded with a floating 1, the final result in ac3 should be a
2882 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2883
2884 001316 SN=SN+1
2885 020000 ZZ=ZZ+ZZ
2886 IFE ZZ,<ZZ=1>
2887 031721 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2888 031722 205 01 0 00 020000 MOVSI 1,ZZ ;Preload ac1 with floating 1
2889 031723 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2890 031724 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2891 031725 312 03 0 00 034436 CAME 3,[ZZ,,0] ;Test indexing
2892 STOP^
2893 031726 254 04 0 00 031727 HALT .+1 ;Test failed if program halts here
2894 031727 324 00 0 00 031730 JUMPA .+1 ;To loop change this instruction^
2895
2896 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 9-6
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0069
2897
2898
2899 ;This test verifies that index register addressing functions correctly.
2900 ;In this test, a move instruction using indexing is executed. the move
2901 ;Instruction should place the contents of the location specified by index
2902 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2903 ;Ac1 was preloaded with a floating 1, the final result in ac3 should be a
2904 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2905
2906 001317 SN=SN+1
2907 040000 ZZ=ZZ+ZZ
2908 IFE ZZ,<ZZ=1>
2909 031730 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2910 031731 205 01 0 00 040000 MOVSI 1,ZZ ;Preload ac1 with floating 1
2911 031732 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2912 031733 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2913 031734 312 03 0 00 034437 CAME 3,[ZZ,,0] ;Test indexing
2914 STOP^
2915 031735 254 04 0 00 031736 HALT .+1 ;Test failed if program halts here
2916 031736 324 00 0 00 031737 JUMPA .+1 ;To loop change this instruction^
2917
2918 ;**********
2919
2920
2921 ;This test verifies that index register addressing functions correctly.
2922 ;In this test, a move instruction using indexing is executed. the move
2923 ;Instruction should place the contents of the location specified by index
2924 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2925 ;Ac1 was preloaded with a floating 1, the final result in ac3 should be a
2926 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2927
2928 001320 SN=SN+1
2929 100000 ZZ=ZZ+ZZ
2930 IFE ZZ,<ZZ=1>
2931 031737 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2932 031740 205 01 0 00 100000 MOVSI 1,ZZ ;Preload ac1 with floating 1
2933 031741 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2934 031742 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2935 031743 312 03 0 00 034440 CAME 3,[ZZ,,0] ;Test indexing
2936 STOP^
2937 031744 254 04 0 00 031745 HALT .+1 ;Test failed if program halts here
2938 031745 324 00 0 00 031746 JUMPA .+1 ;To loop change this instruction^
2939
2940 ;**********
2941
2942
2943 ;This test verifies that index register addressing functions correctly.
2944 ;In this test, a move instruction using indexing is executed. the move
2945 ;Instruction should place the contents of the location specified by index
2946 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2947 ;Ac1 was preloaded with a floating 1, the final result in ac3 should be a
2948 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2949
2950 001321 SN=SN+1
2951 200000 ZZ=ZZ+ZZ
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 9-7
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0070
2952 IFE ZZ,<ZZ=1>
2953 031746 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2954 031747 205 01 0 00 200000 MOVSI 1,ZZ ;Preload ac1 with floating 1
2955 031750 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2956 031751 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2957 031752 312 03 0 00 034441 CAME 3,[ZZ,,0] ;Test indexing
2958 STOP^
2959 031753 254 04 0 00 031754 HALT .+1 ;Test failed if program halts here
2960 031754 324 00 0 00 031755 JUMPA .+1 ;To loop change this instruction^
2961
2962 ;**********
2963
2964
2965 ;This test verifies that index register addressing functions correctly.
2966 ;In this test, a move instruction using indexing is executed. the move
2967 ;Instruction should place the contents of the location specified by index
2968 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2969 ;Ac1 was preloaded with a floating 1, the final result in ac3 should be a
2970 ;Floating 1. if c(ac3)=a floating 1, this test passes.
2971
2972 001322 SN=SN+1
2973 400000 ZZ=ZZ+ZZ
2974 IFE ZZ,<ZZ=1>
2975 031755 476 00 0 00 000003 SETOM 3 ;Preload ac3 with -1,,-1
2976 031756 205 01 0 00 400000 MOVSI 1,ZZ ;Preload ac1 with floating 1
2977 031757 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2978 031760 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2979 031761 312 03 0 00 034442 CAME 3,[ZZ,,0] ;Test indexing
2980 STOP^
2981 031762 254 04 0 00 031763 HALT .+1 ;Test failed if program halts here
2982 031763 324 00 0 00 031764 JUMPA .+1 ;To loop change this instruction^
2983
2984 ;**********
2985
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 10
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0071
2986 ;This test verifies that index register addressing functions correctly.
2987 ;In this test, a move instruction using indexing is executed. the move
2988 ;Instruction should place the contents of the location specified by index
2989 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
2990 ;Ac1 was preloaded with -1,,-1, the final result in ac3 should be -1,,-1.
2991 ;If c(ac3)=-1,,-1, this test passes.
2992
2993 031764 402 00 0 00 000003 C1400: SETZM 3 ;Preload ac3 with 0
2994 031765 476 00 0 00 000001 SETOM 1 ;Preload ac1 with -1,,-1
2995 031766 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
2996 031767 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
2997 031770 312 03 0 00 034443 CAME 3,[-1,,-1] ;Test indexing
2998 STOP^
2999 031771 254 04 0 00 031772 HALT .+1 ;Test failed if program halts here
3000 031772 324 00 0 00 031773 JUMPA .+1 ;To loop change this instruction^
3001
3002 ;**********
3003
3004 001500 SN=1500
3005 000000 ZZ=0
3006
3007 C1500: REPEAT ^D18,<
3008 ;This test verifies that index register addressing functions correctly.
3009 ;In this test, a move instruction using indexing is executed. the move
3010 ;Instruction should place the contents of the location specified by index
3011 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3012 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3013 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3014
3015 SN=SN+1
3016 ZZ=<ZZ+ZZ+1>&777777
3017 IFE <ZZ-1>,<ZZ=777776>
3018 SETZM 3 ;Preload ac3 with 0
3019 HRROI 1,ZZ ;Preload ac1 with floating 0
3020 MOVEI 2,1 ;Setup index register
3021 MOVE 3,(2) ;*Fwt from indexed location
3022 CAME 3,[-1,,ZZ] ;Test indexing
3023 STOP
3024
3025 ;**********
3026 >
3027
3028 ;This test verifies that index register addressing functions correctly.
3029 ;In this test, a move instruction using indexing is executed. the move
3030 ;Instruction should place the contents of the location specified by index
3031 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3032 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3033 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3034
3035 001501 SN=SN+1
3036 000001 ZZ=<ZZ+ZZ+1>&777777
3037 777776 IFE <ZZ-1>,<ZZ=777776>
3038 031773 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3039 031774 561 01 0 00 777776 HRROI 1,ZZ ;Preload ac1 with floating 0
3040 031775 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 10-1
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0072
3041 031776 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3042 031777 312 03 0 00 034444 CAME 3,[-1,,ZZ] ;Test indexing
3043 STOP^
3044 032000 254 04 0 00 032001 HALT .+1 ;Test failed if program halts here
3045 032001 324 00 0 00 032002 JUMPA .+1 ;To loop change this instruction^
3046
3047 ;**********
3048
3049
3050 ;This test verifies that index register addressing functions correctly.
3051 ;In this test, a move instruction using indexing is executed. the move
3052 ;Instruction should place the contents of the location specified by index
3053 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3054 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3055 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3056
3057 001502 SN=SN+1
3058 777775 ZZ=<ZZ+ZZ+1>&777777
3059 IFE <ZZ-1>,<ZZ=777776>
3060 032002 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3061 032003 561 01 0 00 777775 HRROI 1,ZZ ;Preload ac1 with floating 0
3062 032004 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
3063 032005 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3064 032006 312 03 0 00 034445 CAME 3,[-1,,ZZ] ;Test indexing
3065 STOP^
3066 032007 254 04 0 00 032010 HALT .+1 ;Test failed if program halts here
3067 032010 324 00 0 00 032011 JUMPA .+1 ;To loop change this instruction^
3068
3069 ;**********
3070
3071
3072 ;This test verifies that index register addressing functions correctly.
3073 ;In this test, a move instruction using indexing is executed. the move
3074 ;Instruction should place the contents of the location specified by index
3075 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3076 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3077 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3078
3079 001503 SN=SN+1
3080 777773 ZZ=<ZZ+ZZ+1>&777777
3081 IFE <ZZ-1>,<ZZ=777776>
3082 032011 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3083 032012 561 01 0 00 777773 HRROI 1,ZZ ;Preload ac1 with floating 0
3084 032013 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
3085 032014 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3086 032015 312 03 0 00 034446 CAME 3,[-1,,ZZ] ;Test indexing
3087 STOP^
3088 032016 254 04 0 00 032017 HALT .+1 ;Test failed if program halts here
3089 032017 324 00 0 00 032020 JUMPA .+1 ;To loop change this instruction^
3090
3091 ;**********
3092
3093
3094 ;This test verifies that index register addressing functions correctly.
3095 ;In this test, a move instruction using indexing is executed. the move
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 10-2
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0073
3096 ;Instruction should place the contents of the location specified by index
3097 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3098 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3099 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3100
3101 001504 SN=SN+1
3102 777767 ZZ=<ZZ+ZZ+1>&777777
3103 IFE <ZZ-1>,<ZZ=777776>
3104 032020 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3105 032021 561 01 0 00 777767 HRROI 1,ZZ ;Preload ac1 with floating 0
3106 032022 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
3107 032023 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3108 032024 312 03 0 00 034447 CAME 3,[-1,,ZZ] ;Test indexing
3109 STOP^
3110 032025 254 04 0 00 032026 HALT .+1 ;Test failed if program halts here
3111 032026 324 00 0 00 032027 JUMPA .+1 ;To loop change this instruction^
3112
3113 ;**********
3114
3115
3116 ;This test verifies that index register addressing functions correctly.
3117 ;In this test, a move instruction using indexing is executed. the move
3118 ;Instruction should place the contents of the location specified by index
3119 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3120 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3121 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3122
3123 001505 SN=SN+1
3124 777757 ZZ=<ZZ+ZZ+1>&777777
3125 IFE <ZZ-1>,<ZZ=777776>
3126 032027 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3127 032030 561 01 0 00 777757 HRROI 1,ZZ ;Preload ac1 with floating 0
3128 032031 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
3129 032032 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3130 032033 312 03 0 00 034450 CAME 3,[-1,,ZZ] ;Test indexing
3131 STOP^
3132 032034 254 04 0 00 032035 HALT .+1 ;Test failed if program halts here
3133 032035 324 00 0 00 032036 JUMPA .+1 ;To loop change this instruction^
3134
3135 ;**********
3136
3137
3138 ;This test verifies that index register addressing functions correctly.
3139 ;In this test, a move instruction using indexing is executed. the move
3140 ;Instruction should place the contents of the location specified by index
3141 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3142 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3143 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3144
3145 001506 SN=SN+1
3146 777737 ZZ=<ZZ+ZZ+1>&777777
3147 IFE <ZZ-1>,<ZZ=777776>
3148 032036 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3149 032037 561 01 0 00 777737 HRROI 1,ZZ ;Preload ac1 with floating 0
3150 032040 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 10-3
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0074
3151 032041 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3152 032042 312 03 0 00 034451 CAME 3,[-1,,ZZ] ;Test indexing
3153 STOP^
3154 032043 254 04 0 00 032044 HALT .+1 ;Test failed if program halts here
3155 032044 324 00 0 00 032045 JUMPA .+1 ;To loop change this instruction^
3156
3157 ;**********
3158
3159
3160 ;This test verifies that index register addressing functions correctly.
3161 ;In this test, a move instruction using indexing is executed. the move
3162 ;Instruction should place the contents of the location specified by index
3163 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3164 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3165 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3166
3167 001507 SN=SN+1
3168 777677 ZZ=<ZZ+ZZ+1>&777777
3169 IFE <ZZ-1>,<ZZ=777776>
3170 032045 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3171 032046 561 01 0 00 777677 HRROI 1,ZZ ;Preload ac1 with floating 0
3172 032047 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
3173 032050 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3174 032051 312 03 0 00 034452 CAME 3,[-1,,ZZ] ;Test indexing
3175 STOP^
3176 032052 254 04 0 00 032053 HALT .+1 ;Test failed if program halts here
3177 032053 324 00 0 00 032054 JUMPA .+1 ;To loop change this instruction^
3178
3179 ;**********
3180
3181
3182 ;This test verifies that index register addressing functions correctly.
3183 ;In this test, a move instruction using indexing is executed. the move
3184 ;Instruction should place the contents of the location specified by index
3185 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3186 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3187 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3188
3189 001510 SN=SN+1
3190 777577 ZZ=<ZZ+ZZ+1>&777777
3191 IFE <ZZ-1>,<ZZ=777776>
3192 032054 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3193 032055 561 01 0 00 777577 HRROI 1,ZZ ;Preload ac1 with floating 0
3194 032056 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
3195 032057 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3196 032060 312 03 0 00 034453 CAME 3,[-1,,ZZ] ;Test indexing
3197 STOP^
3198 032061 254 04 0 00 032062 HALT .+1 ;Test failed if program halts here
3199 032062 324 00 0 00 032063 JUMPA .+1 ;To loop change this instruction^
3200
3201 ;**********
3202
3203
3204 ;This test verifies that index register addressing functions correctly.
3205 ;In this test, a move instruction using indexing is executed. the move
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 10-4
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0075
3206 ;Instruction should place the contents of the location specified by index
3207 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3208 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3209 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3210
3211 001511 SN=SN+1
3212 777377 ZZ=<ZZ+ZZ+1>&777777
3213 IFE <ZZ-1>,<ZZ=777776>
3214 032063 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3215 032064 561 01 0 00 777377 HRROI 1,ZZ ;Preload ac1 with floating 0
3216 032065 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
3217 032066 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3218 032067 312 03 0 00 034454 CAME 3,[-1,,ZZ] ;Test indexing
3219 STOP^
3220 032070 254 04 0 00 032071 HALT .+1 ;Test failed if program halts here
3221 032071 324 00 0 00 032072 JUMPA .+1 ;To loop change this instruction^
3222
3223 ;**********
3224
3225
3226 ;This test verifies that index register addressing functions correctly.
3227 ;In this test, a move instruction using indexing is executed. the move
3228 ;Instruction should place the contents of the location specified by index
3229 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3230 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3231 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3232
3233 001512 SN=SN+1
3234 776777 ZZ=<ZZ+ZZ+1>&777777
3235 IFE <ZZ-1>,<ZZ=777776>
3236 032072 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3237 032073 561 01 0 00 776777 HRROI 1,ZZ ;Preload ac1 with floating 0
3238 032074 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
3239 032075 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3240 032076 312 03 0 00 034455 CAME 3,[-1,,ZZ] ;Test indexing
3241 STOP^
3242 032077 254 04 0 00 032100 HALT .+1 ;Test failed if program halts here
3243 032100 324 00 0 00 032101 JUMPA .+1 ;To loop change this instruction^
3244
3245 ;**********
3246
3247
3248 ;This test verifies that index register addressing functions correctly.
3249 ;In this test, a move instruction using indexing is executed. the move
3250 ;Instruction should place the contents of the location specified by index
3251 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3252 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3253 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3254
3255 001513 SN=SN+1
3256 775777 ZZ=<ZZ+ZZ+1>&777777
3257 IFE <ZZ-1>,<ZZ=777776>
3258 032101 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3259 032102 561 01 0 00 775777 HRROI 1,ZZ ;Preload ac1 with floating 0
3260 032103 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 10-5
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0076
3261 032104 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3262 032105 312 03 0 00 034456 CAME 3,[-1,,ZZ] ;Test indexing
3263 STOP^
3264 032106 254 04 0 00 032107 HALT .+1 ;Test failed if program halts here
3265 032107 324 00 0 00 032110 JUMPA .+1 ;To loop change this instruction^
3266
3267 ;**********
3268
3269
3270 ;This test verifies that index register addressing functions correctly.
3271 ;In this test, a move instruction using indexing is executed. the move
3272 ;Instruction should place the contents of the location specified by index
3273 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3274 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3275 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3276
3277 001514 SN=SN+1
3278 773777 ZZ=<ZZ+ZZ+1>&777777
3279 IFE <ZZ-1>,<ZZ=777776>
3280 032110 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3281 032111 561 01 0 00 773777 HRROI 1,ZZ ;Preload ac1 with floating 0
3282 032112 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
3283 032113 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3284 032114 312 03 0 00 034457 CAME 3,[-1,,ZZ] ;Test indexing
3285 STOP^
3286 032115 254 04 0 00 032116 HALT .+1 ;Test failed if program halts here
3287 032116 324 00 0 00 032117 JUMPA .+1 ;To loop change this instruction^
3288
3289 ;**********
3290
3291
3292 ;This test verifies that index register addressing functions correctly.
3293 ;In this test, a move instruction using indexing is executed. the move
3294 ;Instruction should place the contents of the location specified by index
3295 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3296 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3297 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3298
3299 001515 SN=SN+1
3300 767777 ZZ=<ZZ+ZZ+1>&777777
3301 IFE <ZZ-1>,<ZZ=777776>
3302 032117 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3303 032120 561 01 0 00 767777 HRROI 1,ZZ ;Preload ac1 with floating 0
3304 032121 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
3305 032122 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3306 032123 312 03 0 00 034460 CAME 3,[-1,,ZZ] ;Test indexing
3307 STOP^
3308 032124 254 04 0 00 032125 HALT .+1 ;Test failed if program halts here
3309 032125 324 00 0 00 032126 JUMPA .+1 ;To loop change this instruction^
3310
3311 ;**********
3312
3313
3314 ;This test verifies that index register addressing functions correctly.
3315 ;In this test, a move instruction using indexing is executed. the move
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 10-6
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0077
3316 ;Instruction should place the contents of the location specified by index
3317 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3318 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3319 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3320
3321 001516 SN=SN+1
3322 757777 ZZ=<ZZ+ZZ+1>&777777
3323 IFE <ZZ-1>,<ZZ=777776>
3324 032126 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3325 032127 561 01 0 00 757777 HRROI 1,ZZ ;Preload ac1 with floating 0
3326 032130 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
3327 032131 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3328 032132 312 03 0 00 034461 CAME 3,[-1,,ZZ] ;Test indexing
3329 STOP^
3330 032133 254 04 0 00 032134 HALT .+1 ;Test failed if program halts here
3331 032134 324 00 0 00 032135 JUMPA .+1 ;To loop change this instruction^
3332
3333 ;**********
3334
3335
3336 ;This test verifies that index register addressing functions correctly.
3337 ;In this test, a move instruction using indexing is executed. the move
3338 ;Instruction should place the contents of the location specified by index
3339 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3340 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3341 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3342
3343 001517 SN=SN+1
3344 737777 ZZ=<ZZ+ZZ+1>&777777
3345 IFE <ZZ-1>,<ZZ=777776>
3346 032135 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3347 032136 561 01 0 00 737777 HRROI 1,ZZ ;Preload ac1 with floating 0
3348 032137 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
3349 032140 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3350 032141 312 03 0 00 034462 CAME 3,[-1,,ZZ] ;Test indexing
3351 STOP^
3352 032142 254 04 0 00 032143 HALT .+1 ;Test failed if program halts here
3353 032143 324 00 0 00 032144 JUMPA .+1 ;To loop change this instruction^
3354
3355 ;**********
3356
3357
3358 ;This test verifies that index register addressing functions correctly.
3359 ;In this test, a move instruction using indexing is executed. the move
3360 ;Instruction should place the contents of the location specified by index
3361 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3362 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3363 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3364
3365 001520 SN=SN+1
3366 677777 ZZ=<ZZ+ZZ+1>&777777
3367 IFE <ZZ-1>,<ZZ=777776>
3368 032144 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3369 032145 561 01 0 00 677777 HRROI 1,ZZ ;Preload ac1 with floating 0
3370 032146 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 10-7
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0078
3371 032147 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3372 032150 312 03 0 00 034463 CAME 3,[-1,,ZZ] ;Test indexing
3373 STOP^
3374 032151 254 04 0 00 032152 HALT .+1 ;Test failed if program halts here
3375 032152 324 00 0 00 032153 JUMPA .+1 ;To loop change this instruction^
3376
3377 ;**********
3378
3379
3380 ;This test verifies that index register addressing functions correctly.
3381 ;In this test, a move instruction using indexing is executed. the move
3382 ;Instruction should place the contents of the location specified by index
3383 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3384 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3385 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3386
3387 001521 SN=SN+1
3388 577777 ZZ=<ZZ+ZZ+1>&777777
3389 IFE <ZZ-1>,<ZZ=777776>
3390 032153 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3391 032154 561 01 0 00 577777 HRROI 1,ZZ ;Preload ac1 with floating 0
3392 032155 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
3393 032156 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3394 032157 312 03 0 00 034464 CAME 3,[-1,,ZZ] ;Test indexing
3395 STOP^
3396 032160 254 04 0 00 032161 HALT .+1 ;Test failed if program halts here
3397 032161 324 00 0 00 032162 JUMPA .+1 ;To loop change this instruction^
3398
3399 ;**********
3400
3401
3402 ;This test verifies that index register addressing functions correctly.
3403 ;In this test, a move instruction using indexing is executed. the move
3404 ;Instruction should place the contents of the location specified by index
3405 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3406 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3407 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3408
3409 001522 SN=SN+1
3410 377777 ZZ=<ZZ+ZZ+1>&777777
3411 IFE <ZZ-1>,<ZZ=777776>
3412 032162 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3413 032163 561 01 0 00 377777 HRROI 1,ZZ ;Preload ac1 with floating 0
3414 032164 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
3415 032165 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3416 032166 312 03 0 00 034465 CAME 3,[-1,,ZZ] ;Test indexing
3417 STOP^
3418 032167 254 04 0 00 032170 HALT .+1 ;Test failed if program halts here
3419 032170 324 00 0 00 032171 JUMPA .+1 ;To loop change this instruction^
3420
3421 ;**********
3422
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 11
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0079
3423 001600 SN=1600
3424 000000 ZZ=0
3425
3426 C1600: REPEAT ^D18,<
3427 ;This test verifies that index register addressing functions correctly.
3428 ;In this test, a move instruction using indexing is executed. the move
3429 ;Instruction should place the contents of the location specified by index
3430 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3431 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3432 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3433
3434 SN=SN+1
3435 ZZ=<ZZ+ZZ+1>&777777
3436 IFE <ZZ-1>,<ZZ=777776>
3437 SETZM 3 ;Preload ac3 with 0
3438 HRLOI 1,ZZ ;Preload ac1 with floating 0
3439 MOVEI 2,1 ;Setup index register
3440 MOVE 3,(2) ;*Fwt from indexed location
3441 CAME 3,[ZZ,,-1] ;Test indexing
3442 STOP
3443
3444 ;**********
3445 >
3446
3447 ;This test verifies that index register addressing functions correctly.
3448 ;In this test, a move instruction using indexing is executed. the move
3449 ;Instruction should place the contents of the location specified by index
3450 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3451 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3452 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3453
3454 001601 SN=SN+1
3455 000001 ZZ=<ZZ+ZZ+1>&777777
3456 777776 IFE <ZZ-1>,<ZZ=777776>
3457 032171 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3458 032172 525 01 0 00 777776 HRLOI 1,ZZ ;Preload ac1 with floating 0
3459 032173 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
3460 032174 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3461 032175 312 03 0 00 034466 CAME 3,[ZZ,,-1] ;Test indexing
3462 STOP^
3463 032176 254 04 0 00 032177 HALT .+1 ;Test failed if program halts here
3464 032177 324 00 0 00 032200 JUMPA .+1 ;To loop change this instruction^
3465
3466 ;**********
3467
3468
3469 ;This test verifies that index register addressing functions correctly.
3470 ;In this test, a move instruction using indexing is executed. the move
3471 ;Instruction should place the contents of the location specified by index
3472 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3473 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3474 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3475
3476 001602 SN=SN+1
3477 777775 ZZ=<ZZ+ZZ+1>&777777
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 11-1
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0080
3478 IFE <ZZ-1>,<ZZ=777776>
3479 032200 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3480 032201 525 01 0 00 777775 HRLOI 1,ZZ ;Preload ac1 with floating 0
3481 032202 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
3482 032203 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3483 032204 312 03 0 00 034467 CAME 3,[ZZ,,-1] ;Test indexing
3484 STOP^
3485 032205 254 04 0 00 032206 HALT .+1 ;Test failed if program halts here
3486 032206 324 00 0 00 032207 JUMPA .+1 ;To loop change this instruction^
3487
3488 ;**********
3489
3490
3491 ;This test verifies that index register addressing functions correctly.
3492 ;In this test, a move instruction using indexing is executed. the move
3493 ;Instruction should place the contents of the location specified by index
3494 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3495 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3496 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3497
3498 001603 SN=SN+1
3499 777773 ZZ=<ZZ+ZZ+1>&777777
3500 IFE <ZZ-1>,<ZZ=777776>
3501 032207 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3502 032210 525 01 0 00 777773 HRLOI 1,ZZ ;Preload ac1 with floating 0
3503 032211 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
3504 032212 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3505 032213 312 03 0 00 034470 CAME 3,[ZZ,,-1] ;Test indexing
3506 STOP^
3507 032214 254 04 0 00 032215 HALT .+1 ;Test failed if program halts here
3508 032215 324 00 0 00 032216 JUMPA .+1 ;To loop change this instruction^
3509
3510 ;**********
3511
3512
3513 ;This test verifies that index register addressing functions correctly.
3514 ;In this test, a move instruction using indexing is executed. the move
3515 ;Instruction should place the contents of the location specified by index
3516 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3517 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3518 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3519
3520 001604 SN=SN+1
3521 777767 ZZ=<ZZ+ZZ+1>&777777
3522 IFE <ZZ-1>,<ZZ=777776>
3523 032216 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3524 032217 525 01 0 00 777767 HRLOI 1,ZZ ;Preload ac1 with floating 0
3525 032220 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
3526 032221 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3527 032222 312 03 0 00 034471 CAME 3,[ZZ,,-1] ;Test indexing
3528 STOP^
3529 032223 254 04 0 00 032224 HALT .+1 ;Test failed if program halts here
3530 032224 324 00 0 00 032225 JUMPA .+1 ;To loop change this instruction^
3531
3532 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 11-2
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0081
3533
3534
3535 ;This test verifies that index register addressing functions correctly.
3536 ;In this test, a move instruction using indexing is executed. the move
3537 ;Instruction should place the contents of the location specified by index
3538 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3539 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3540 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3541
3542 001605 SN=SN+1
3543 777757 ZZ=<ZZ+ZZ+1>&777777
3544 IFE <ZZ-1>,<ZZ=777776>
3545 032225 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3546 032226 525 01 0 00 777757 HRLOI 1,ZZ ;Preload ac1 with floating 0
3547 032227 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
3548 032230 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3549 032231 312 03 0 00 034472 CAME 3,[ZZ,,-1] ;Test indexing
3550 STOP^
3551 032232 254 04 0 00 032233 HALT .+1 ;Test failed if program halts here
3552 032233 324 00 0 00 032234 JUMPA .+1 ;To loop change this instruction^
3553
3554 ;**********
3555
3556
3557 ;This test verifies that index register addressing functions correctly.
3558 ;In this test, a move instruction using indexing is executed. the move
3559 ;Instruction should place the contents of the location specified by index
3560 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3561 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3562 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3563
3564 001606 SN=SN+1
3565 777737 ZZ=<ZZ+ZZ+1>&777777
3566 IFE <ZZ-1>,<ZZ=777776>
3567 032234 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3568 032235 525 01 0 00 777737 HRLOI 1,ZZ ;Preload ac1 with floating 0
3569 032236 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
3570 032237 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3571 032240 312 03 0 00 034473 CAME 3,[ZZ,,-1] ;Test indexing
3572 STOP^
3573 032241 254 04 0 00 032242 HALT .+1 ;Test failed if program halts here
3574 032242 324 00 0 00 032243 JUMPA .+1 ;To loop change this instruction^
3575
3576 ;**********
3577
3578
3579 ;This test verifies that index register addressing functions correctly.
3580 ;In this test, a move instruction using indexing is executed. the move
3581 ;Instruction should place the contents of the location specified by index
3582 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3583 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3584 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3585
3586 001607 SN=SN+1
3587 777677 ZZ=<ZZ+ZZ+1>&777777
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 11-3
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0082
3588 IFE <ZZ-1>,<ZZ=777776>
3589 032243 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3590 032244 525 01 0 00 777677 HRLOI 1,ZZ ;Preload ac1 with floating 0
3591 032245 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
3592 032246 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3593 032247 312 03 0 00 034474 CAME 3,[ZZ,,-1] ;Test indexing
3594 STOP^
3595 032250 254 04 0 00 032251 HALT .+1 ;Test failed if program halts here
3596 032251 324 00 0 00 032252 JUMPA .+1 ;To loop change this instruction^
3597
3598 ;**********
3599
3600
3601 ;This test verifies that index register addressing functions correctly.
3602 ;In this test, a move instruction using indexing is executed. the move
3603 ;Instruction should place the contents of the location specified by index
3604 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3605 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3606 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3607
3608 001610 SN=SN+1
3609 777577 ZZ=<ZZ+ZZ+1>&777777
3610 IFE <ZZ-1>,<ZZ=777776>
3611 032252 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3612 032253 525 01 0 00 777577 HRLOI 1,ZZ ;Preload ac1 with floating 0
3613 032254 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
3614 032255 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3615 032256 312 03 0 00 034475 CAME 3,[ZZ,,-1] ;Test indexing
3616 STOP^
3617 032257 254 04 0 00 032260 HALT .+1 ;Test failed if program halts here
3618 032260 324 00 0 00 032261 JUMPA .+1 ;To loop change this instruction^
3619
3620 ;**********
3621
3622
3623 ;This test verifies that index register addressing functions correctly.
3624 ;In this test, a move instruction using indexing is executed. the move
3625 ;Instruction should place the contents of the location specified by index
3626 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3627 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3628 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3629
3630 001611 SN=SN+1
3631 777377 ZZ=<ZZ+ZZ+1>&777777
3632 IFE <ZZ-1>,<ZZ=777776>
3633 032261 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3634 032262 525 01 0 00 777377 HRLOI 1,ZZ ;Preload ac1 with floating 0
3635 032263 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
3636 032264 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3637 032265 312 03 0 00 034476 CAME 3,[ZZ,,-1] ;Test indexing
3638 STOP^
3639 032266 254 04 0 00 032267 HALT .+1 ;Test failed if program halts here
3640 032267 324 00 0 00 032270 JUMPA .+1 ;To loop change this instruction^
3641
3642 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 11-4
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0083
3643
3644
3645 ;This test verifies that index register addressing functions correctly.
3646 ;In this test, a move instruction using indexing is executed. the move
3647 ;Instruction should place the contents of the location specified by index
3648 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3649 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3650 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3651
3652 001612 SN=SN+1
3653 776777 ZZ=<ZZ+ZZ+1>&777777
3654 IFE <ZZ-1>,<ZZ=777776>
3655 032270 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3656 032271 525 01 0 00 776777 HRLOI 1,ZZ ;Preload ac1 with floating 0
3657 032272 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
3658 032273 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3659 032274 312 03 0 00 034477 CAME 3,[ZZ,,-1] ;Test indexing
3660 STOP^
3661 032275 254 04 0 00 032276 HALT .+1 ;Test failed if program halts here
3662 032276 324 00 0 00 032277 JUMPA .+1 ;To loop change this instruction^
3663
3664 ;**********
3665
3666
3667 ;This test verifies that index register addressing functions correctly.
3668 ;In this test, a move instruction using indexing is executed. the move
3669 ;Instruction should place the contents of the location specified by index
3670 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3671 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3672 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3673
3674 001613 SN=SN+1
3675 775777 ZZ=<ZZ+ZZ+1>&777777
3676 IFE <ZZ-1>,<ZZ=777776>
3677 032277 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3678 032300 525 01 0 00 775777 HRLOI 1,ZZ ;Preload ac1 with floating 0
3679 032301 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
3680 032302 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3681 032303 312 03 0 00 034500 CAME 3,[ZZ,,-1] ;Test indexing
3682 STOP^
3683 032304 254 04 0 00 032305 HALT .+1 ;Test failed if program halts here
3684 032305 324 00 0 00 032306 JUMPA .+1 ;To loop change this instruction^
3685
3686 ;**********
3687
3688
3689 ;This test verifies that index register addressing functions correctly.
3690 ;In this test, a move instruction using indexing is executed. the move
3691 ;Instruction should place the contents of the location specified by index
3692 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3693 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3694 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3695
3696 001614 SN=SN+1
3697 773777 ZZ=<ZZ+ZZ+1>&777777
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 11-5
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0084
3698 IFE <ZZ-1>,<ZZ=777776>
3699 032306 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3700 032307 525 01 0 00 773777 HRLOI 1,ZZ ;Preload ac1 with floating 0
3701 032310 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
3702 032311 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3703 032312 312 03 0 00 034501 CAME 3,[ZZ,,-1] ;Test indexing
3704 STOP^
3705 032313 254 04 0 00 032314 HALT .+1 ;Test failed if program halts here
3706 032314 324 00 0 00 032315 JUMPA .+1 ;To loop change this instruction^
3707
3708 ;**********
3709
3710
3711 ;This test verifies that index register addressing functions correctly.
3712 ;In this test, a move instruction using indexing is executed. the move
3713 ;Instruction should place the contents of the location specified by index
3714 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3715 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3716 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3717
3718 001615 SN=SN+1
3719 767777 ZZ=<ZZ+ZZ+1>&777777
3720 IFE <ZZ-1>,<ZZ=777776>
3721 032315 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3722 032316 525 01 0 00 767777 HRLOI 1,ZZ ;Preload ac1 with floating 0
3723 032317 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
3724 032320 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3725 032321 312 03 0 00 034502 CAME 3,[ZZ,,-1] ;Test indexing
3726 STOP^
3727 032322 254 04 0 00 032323 HALT .+1 ;Test failed if program halts here
3728 032323 324 00 0 00 032324 JUMPA .+1 ;To loop change this instruction^
3729
3730 ;**********
3731
3732
3733 ;This test verifies that index register addressing functions correctly.
3734 ;In this test, a move instruction using indexing is executed. the move
3735 ;Instruction should place the contents of the location specified by index
3736 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3737 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3738 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3739
3740 001616 SN=SN+1
3741 757777 ZZ=<ZZ+ZZ+1>&777777
3742 IFE <ZZ-1>,<ZZ=777776>
3743 032324 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3744 032325 525 01 0 00 757777 HRLOI 1,ZZ ;Preload ac1 with floating 0
3745 032326 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
3746 032327 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3747 032330 312 03 0 00 034503 CAME 3,[ZZ,,-1] ;Test indexing
3748 STOP^
3749 032331 254 04 0 00 032332 HALT .+1 ;Test failed if program halts here
3750 032332 324 00 0 00 032333 JUMPA .+1 ;To loop change this instruction^
3751
3752 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 11-6
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0085
3753
3754
3755 ;This test verifies that index register addressing functions correctly.
3756 ;In this test, a move instruction using indexing is executed. the move
3757 ;Instruction should place the contents of the location specified by index
3758 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3759 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3760 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3761
3762 001617 SN=SN+1
3763 737777 ZZ=<ZZ+ZZ+1>&777777
3764 IFE <ZZ-1>,<ZZ=777776>
3765 032333 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3766 032334 525 01 0 00 737777 HRLOI 1,ZZ ;Preload ac1 with floating 0
3767 032335 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
3768 032336 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3769 032337 312 03 0 00 034504 CAME 3,[ZZ,,-1] ;Test indexing
3770 STOP^
3771 032340 254 04 0 00 032341 HALT .+1 ;Test failed if program halts here
3772 032341 324 00 0 00 032342 JUMPA .+1 ;To loop change this instruction^
3773
3774 ;**********
3775
3776
3777 ;This test verifies that index register addressing functions correctly.
3778 ;In this test, a move instruction using indexing is executed. the move
3779 ;Instruction should place the contents of the location specified by index
3780 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3781 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3782 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3783
3784 001620 SN=SN+1
3785 677777 ZZ=<ZZ+ZZ+1>&777777
3786 IFE <ZZ-1>,<ZZ=777776>
3787 032342 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3788 032343 525 01 0 00 677777 HRLOI 1,ZZ ;Preload ac1 with floating 0
3789 032344 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
3790 032345 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3791 032346 312 03 0 00 034505 CAME 3,[ZZ,,-1] ;Test indexing
3792 STOP^
3793 032347 254 04 0 00 032350 HALT .+1 ;Test failed if program halts here
3794 032350 324 00 0 00 032351 JUMPA .+1 ;To loop change this instruction^
3795
3796 ;**********
3797
3798
3799 ;This test verifies that index register addressing functions correctly.
3800 ;In this test, a move instruction using indexing is executed. the move
3801 ;Instruction should place the contents of the location specified by index
3802 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3803 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3804 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3805
3806 001621 SN=SN+1
3807 577777 ZZ=<ZZ+ZZ+1>&777777
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 11-7
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0086
3808 IFE <ZZ-1>,<ZZ=777776>
3809 032351 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3810 032352 525 01 0 00 577777 HRLOI 1,ZZ ;Preload ac1 with floating 0
3811 032353 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
3812 032354 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3813 032355 312 03 0 00 034506 CAME 3,[ZZ,,-1] ;Test indexing
3814 STOP^
3815 032356 254 04 0 00 032357 HALT .+1 ;Test failed if program halts here
3816 032357 324 00 0 00 032360 JUMPA .+1 ;To loop change this instruction^
3817
3818 ;**********
3819
3820
3821 ;This test verifies that index register addressing functions correctly.
3822 ;In this test, a move instruction using indexing is executed. the move
3823 ;Instruction should place the contents of the location specified by index
3824 ;Register 2 into ac3. since index register 2 was preloaded with a 1 and
3825 ;Ac1 was preloaded with a floating 0, the final result in ac3 should be a
3826 ;Floating 0. if c(ac3)=a floating 0, this test passes.
3827
3828 001622 SN=SN+1
3829 377777 ZZ=<ZZ+ZZ+1>&777777
3830 IFE <ZZ-1>,<ZZ=777776>
3831 032360 402 00 0 00 000003 SETZM 3 ;Preload ac3 with 0
3832 032361 525 01 0 00 377777 HRLOI 1,ZZ ;Preload ac1 with floating 0
3833 032362 201 02 0 00 000001 MOVEI 2,1 ;Setup index register
3834 032363 200 03 0 02 000000 MOVE 3,(2) ;*Fwt from indexed location
3835 032364 312 03 0 00 034507 CAME 3,[ZZ,,-1] ;Test indexing
3836 STOP^
3837 032365 254 04 0 00 032366 HALT .+1 ;Test failed if program halts here
3838 032366 324 00 0 00 032367 JUMPA .+1 ;To loop change this instruction^
3839
3840 ;**********
3841
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 12
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0087
3842 ;Verify indexing where 'e' is non-zero
3843
3844 001700 SN=1700
3845 777777 777777 ZZ=-1
3846 777777 777770 XX=-10
3847
3848 ;This test verifies that index register addressing functions correctly. in
3849 ;This test, the index reg is set-up with movei zz+1,zz-xx, where zz+1 is the
3850 ;Index reg. the ac is preloaded with its own address, 0,,zz. caie is used to
3851 ;Test the indexing operation. if the result in c(ac)=xx+c(zz+1 - right), this
3852 ;Test passes. xx+c(zz+1 - right) should = zz.
3853
3854 C1700: REPEAT ^D15,
3855 <SN=SN+1
3856 ZZ=ZZ+1
3857 XX=XX+3
3858 MOVEI ZZ+1,ZZ-XX ;Setup index register
3859 MOVEI ZZ,ZZ ;Preload ac with 0,,zz
3860 CAIE ZZ,XX(ZZ+1) ;*Test indexing
3861 STOP
3862
3863 ;**********
3864 >
3865 001701 SN=SN+1
3866 000000 ZZ=ZZ+1
3867 777777 777773 XX=XX+3
3868 032367 201 01 0 00 000005 MOVEI ZZ+1,ZZ-XX ;Setup index register
3869 032370 201 00 0 00 000000 MOVEI ZZ,ZZ ;Preload ac with 0,,zz
3870 032371 302 00 0 01 777773 CAIE ZZ,XX(ZZ+1) ;*Test indexing
3871 STOP^
3872 032372 254 04 0 00 032373 HALT .+1 ;Test failed if program halts here
3873 032373 324 00 0 00 032374 JUMPA .+1 ;To loop change this instruction^
3874
3875 ;**********
3876
3877 001702 SN=SN+1
3878 000001 ZZ=ZZ+1
3879 777777 777776 XX=XX+3
3880 032374 201 02 0 00 000003 MOVEI ZZ+1,ZZ-XX ;Setup index register
3881 032375 201 01 0 00 000001 MOVEI ZZ,ZZ ;Preload ac with 0,,zz
3882 032376 302 01 0 02 777776 CAIE ZZ,XX(ZZ+1) ;*Test indexing
3883 STOP^
3884 032377 254 04 0 00 032400 HALT .+1 ;Test failed if program halts here
3885 032400 324 00 0 00 032401 JUMPA .+1 ;To loop change this instruction^
3886
3887 ;**********
3888
3889 001703 SN=SN+1
3890 000002 ZZ=ZZ+1
3891 000001 XX=XX+3
3892 032401 201 03 0 00 000001 MOVEI ZZ+1,ZZ-XX ;Setup index register
3893 032402 201 02 0 00 000002 MOVEI ZZ,ZZ ;Preload ac with 0,,zz
3894 032403 302 02 0 03 000001 CAIE ZZ,XX(ZZ+1) ;*Test indexing
3895 STOP^
3896 032404 254 04 0 00 032405 HALT .+1 ;Test failed if program halts here
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 12-1
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0088
3897 032405 324 00 0 00 032406 JUMPA .+1 ;To loop change this instruction^
3898
3899 ;**********
3900
3901 001704 SN=SN+1
3902 000003 ZZ=ZZ+1
3903 000004 XX=XX+3
3904 032406 201 04 0 00 777777 MOVEI ZZ+1,ZZ-XX ;Setup index register
3905 032407 201 03 0 00 000003 MOVEI ZZ,ZZ ;Preload ac with 0,,zz
3906 032410 302 03 0 04 000004 CAIE ZZ,XX(ZZ+1) ;*Test indexing
3907 STOP^
3908 032411 254 04 0 00 032412 HALT .+1 ;Test failed if program halts here
3909 032412 324 00 0 00 032413 JUMPA .+1 ;To loop change this instruction^
3910
3911 ;**********
3912
3913 001705 SN=SN+1
3914 000004 ZZ=ZZ+1
3915 000007 XX=XX+3
3916 032413 201 05 0 00 777775 MOVEI ZZ+1,ZZ-XX ;Setup index register
3917 032414 201 04 0 00 000004 MOVEI ZZ,ZZ ;Preload ac with 0,,zz
3918 032415 302 04 0 05 000007 CAIE ZZ,XX(ZZ+1) ;*Test indexing
3919 STOP^
3920 032416 254 04 0 00 032417 HALT .+1 ;Test failed if program halts here
3921 032417 324 00 0 00 032420 JUMPA .+1 ;To loop change this instruction^
3922
3923 ;**********
3924
3925 001706 SN=SN+1
3926 000005 ZZ=ZZ+1
3927 000012 XX=XX+3
3928 032420 201 06 0 00 777773 MOVEI ZZ+1,ZZ-XX ;Setup index register
3929 032421 201 05 0 00 000005 MOVEI ZZ,ZZ ;Preload ac with 0,,zz
3930 032422 302 05 0 06 000012 CAIE ZZ,XX(ZZ+1) ;*Test indexing
3931 STOP^
3932 032423 254 04 0 00 032424 HALT .+1 ;Test failed if program halts here
3933 032424 324 00 0 00 032425 JUMPA .+1 ;To loop change this instruction^
3934
3935 ;**********
3936
3937 001707 SN=SN+1
3938 000006 ZZ=ZZ+1
3939 000015 XX=XX+3
3940 032425 201 07 0 00 777771 MOVEI ZZ+1,ZZ-XX ;Setup index register
3941 032426 201 06 0 00 000006 MOVEI ZZ,ZZ ;Preload ac with 0,,zz
3942 032427 302 06 0 07 000015 CAIE ZZ,XX(ZZ+1) ;*Test indexing
3943 STOP^
3944 032430 254 04 0 00 032431 HALT .+1 ;Test failed if program halts here
3945 032431 324 00 0 00 032432 JUMPA .+1 ;To loop change this instruction^
3946
3947 ;**********
3948
3949 001710 SN=SN+1
3950 000007 ZZ=ZZ+1
3951 000020 XX=XX+3
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 12-2
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0089
3952 032432 201 10 0 00 777767 MOVEI ZZ+1,ZZ-XX ;Setup index register
3953 032433 201 07 0 00 000007 MOVEI ZZ,ZZ ;Preload ac with 0,,zz
3954 032434 302 07 0 10 000020 CAIE ZZ,XX(ZZ+1) ;*Test indexing
3955 STOP^
3956 032435 254 04 0 00 032436 HALT .+1 ;Test failed if program halts here
3957 032436 324 00 0 00 032437 JUMPA .+1 ;To loop change this instruction^
3958
3959 ;**********
3960
3961 001711 SN=SN+1
3962 000010 ZZ=ZZ+1
3963 000023 XX=XX+3
3964 032437 201 11 0 00 777765 MOVEI ZZ+1,ZZ-XX ;Setup index register
3965 032440 201 10 0 00 000010 MOVEI ZZ,ZZ ;Preload ac with 0,,zz
3966 032441 302 10 0 11 000023 CAIE ZZ,XX(ZZ+1) ;*Test indexing
3967 STOP^
3968 032442 254 04 0 00 032443 HALT .+1 ;Test failed if program halts here
3969 032443 324 00 0 00 032444 JUMPA .+1 ;To loop change this instruction^
3970
3971 ;**********
3972
3973 001712 SN=SN+1
3974 000011 ZZ=ZZ+1
3975 000026 XX=XX+3
3976 032444 201 12 0 00 777763 MOVEI ZZ+1,ZZ-XX ;Setup index register
3977 032445 201 11 0 00 000011 MOVEI ZZ,ZZ ;Preload ac with 0,,zz
3978 032446 302 11 0 12 000026 CAIE ZZ,XX(ZZ+1) ;*Test indexing
3979 STOP^
3980 032447 254 04 0 00 032450 HALT .+1 ;Test failed if program halts here
3981 032450 324 00 0 00 032451 JUMPA .+1 ;To loop change this instruction^
3982
3983 ;**********
3984
3985 001713 SN=SN+1
3986 000012 ZZ=ZZ+1
3987 000031 XX=XX+3
3988 032451 201 13 0 00 777761 MOVEI ZZ+1,ZZ-XX ;Setup index register
3989 032452 201 12 0 00 000012 MOVEI ZZ,ZZ ;Preload ac with 0,,zz
3990 032453 302 12 0 13 000031 CAIE ZZ,XX(ZZ+1) ;*Test indexing
3991 STOP^
3992 032454 254 04 0 00 032455 HALT .+1 ;Test failed if program halts here
3993 032455 324 00 0 00 032456 JUMPA .+1 ;To loop change this instruction^
3994
3995 ;**********
3996
3997 001714 SN=SN+1
3998 000013 ZZ=ZZ+1
3999 000034 XX=XX+3
4000 032456 201 14 0 00 777757 MOVEI ZZ+1,ZZ-XX ;Setup index register
4001 032457 201 13 0 00 000013 MOVEI ZZ,ZZ ;Preload ac with 0,,zz
4002 032460 302 13 0 14 000034 CAIE ZZ,XX(ZZ+1) ;*Test indexing
4003 STOP^
4004 032461 254 04 0 00 032462 HALT .+1 ;Test failed if program halts here
4005 032462 324 00 0 00 032463 JUMPA .+1 ;To loop change this instruction^
4006
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 12-3
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0090
4007 ;**********
4008
4009 001715 SN=SN+1
4010 000014 ZZ=ZZ+1
4011 000037 XX=XX+3
4012 032463 201 15 0 00 777755 MOVEI ZZ+1,ZZ-XX ;Setup index register
4013 032464 201 14 0 00 000014 MOVEI ZZ,ZZ ;Preload ac with 0,,zz
4014 032465 302 14 0 15 000037 CAIE ZZ,XX(ZZ+1) ;*Test indexing
4015 STOP^
4016 032466 254 04 0 00 032467 HALT .+1 ;Test failed if program halts here
4017 032467 324 00 0 00 032470 JUMPA .+1 ;To loop change this instruction^
4018
4019 ;**********
4020
4021 001716 SN=SN+1
4022 000015 ZZ=ZZ+1
4023 000042 XX=XX+3
4024 032470 201 16 0 00 777753 MOVEI ZZ+1,ZZ-XX ;Setup index register
4025 032471 201 15 0 00 000015 MOVEI ZZ,ZZ ;Preload ac with 0,,zz
4026 032472 302 15 0 16 000042 CAIE ZZ,XX(ZZ+1) ;*Test indexing
4027 STOP^
4028 032473 254 04 0 00 032474 HALT .+1 ;Test failed if program halts here
4029 032474 324 00 0 00 032475 JUMPA .+1 ;To loop change this instruction^
4030
4031 ;**********
4032
4033 001717 SN=SN+1
4034 000016 ZZ=ZZ+1
4035 000045 XX=XX+3
4036 032475 201 17 0 00 777751 MOVEI ZZ+1,ZZ-XX ;Setup index register
4037 032476 201 16 0 00 000016 MOVEI ZZ,ZZ ;Preload ac with 0,,zz
4038 032477 302 16 0 17 000045 CAIE ZZ,XX(ZZ+1) ;*Test indexing
4039 STOP^
4040 032500 254 04 0 00 032501 HALT .+1 ;Test failed if program halts here
4041 032501 324 00 0 00 032502 JUMPA .+1 ;To loop change this instruction^
4042
4043 ;**********
4044
4045 PAGE
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 12-4
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0091
4046 002000 SN=2000
4047 777777 777777 ZZ=-1
4048 777777 777760 XX=-20
4049
4050 ;This test verifies that index register addressing functions correctly. in
4051 ;This test, the index reg is set-up with movei zz+1,zz-xx, where zz+1 is the
4052 ;Index reg. indexing is tested by loading the ac via movei zz,xx(zz+1),
4053 ;Where xx+c(zz+1)=zz. if the result in the ac equals 0,,zz, this test passes.
4054
4055 C2000: REPEAT ^D15,
4056 <SN=SN+1
4057 ZZ=ZZ+1
4058 XX=XX+5
4059 MOVEI ZZ+1,ZZ-XX ;Setup index register
4060 MOVEI ZZ,XX(ZZ+1) ;*Test indexing
4061 CAIE ZZ,ZZ ;Pass if c(ac)=0,,address of ac
4062 STOP
4063
4064 ;**********
4065 >
4066 002001 SN=SN+1
4067 000000 ZZ=ZZ+1
4068 777777 777765 XX=XX+5
4069 032502 201 01 0 00 000013 MOVEI ZZ+1,ZZ-XX ;Setup index register
4070 032503 201 00 0 01 777765 MOVEI ZZ,XX(ZZ+1) ;*Test indexing
4071 032504 302 00 0 00 000000 CAIE ZZ,ZZ ;Pass if c(ac)=0,,address of ac
4072 STOP^
4073 032505 254 04 0 00 032506 HALT .+1 ;Test failed if program halts here
4074 032506 324 00 0 00 032507 JUMPA .+1 ;To loop change this instruction^
4075
4076 ;**********
4077
4078 002002 SN=SN+1
4079 000001 ZZ=ZZ+1
4080 777777 777772 XX=XX+5
4081 032507 201 02 0 00 000007 MOVEI ZZ+1,ZZ-XX ;Setup index register
4082 032510 201 01 0 02 777772 MOVEI ZZ,XX(ZZ+1) ;*Test indexing
4083 032511 302 01 0 00 000001 CAIE ZZ,ZZ ;Pass if c(ac)=0,,address of ac
4084 STOP^
4085 032512 254 04 0 00 032513 HALT .+1 ;Test failed if program halts here
4086 032513 324 00 0 00 032514 JUMPA .+1 ;To loop change this instruction^
4087
4088 ;**********
4089
4090 002003 SN=SN+1
4091 000002 ZZ=ZZ+1
4092 777777 777777 XX=XX+5
4093 032514 201 03 0 00 000003 MOVEI ZZ+1,ZZ-XX ;Setup index register
4094 032515 201 02 0 03 777777 MOVEI ZZ,XX(ZZ+1) ;*Test indexing
4095 032516 302 02 0 00 000002 CAIE ZZ,ZZ ;Pass if c(ac)=0,,address of ac
4096 STOP^
4097 032517 254 04 0 00 032520 HALT .+1 ;Test failed if program halts here
4098 032520 324 00 0 00 032521 JUMPA .+1 ;To loop change this instruction^
4099
4100 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 12-5
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0092
4101
4102 002004 SN=SN+1
4103 000003 ZZ=ZZ+1
4104 000004 XX=XX+5
4105 032521 201 04 0 00 777777 MOVEI ZZ+1,ZZ-XX ;Setup index register
4106 032522 201 03 0 04 000004 MOVEI ZZ,XX(ZZ+1) ;*Test indexing
4107 032523 302 03 0 00 000003 CAIE ZZ,ZZ ;Pass if c(ac)=0,,address of ac
4108 STOP^
4109 032524 254 04 0 00 032525 HALT .+1 ;Test failed if program halts here
4110 032525 324 00 0 00 032526 JUMPA .+1 ;To loop change this instruction^
4111
4112 ;**********
4113
4114 002005 SN=SN+1
4115 000004 ZZ=ZZ+1
4116 000011 XX=XX+5
4117 032526 201 05 0 00 777773 MOVEI ZZ+1,ZZ-XX ;Setup index register
4118 032527 201 04 0 05 000011 MOVEI ZZ,XX(ZZ+1) ;*Test indexing
4119 032530 302 04 0 00 000004 CAIE ZZ,ZZ ;Pass if c(ac)=0,,address of ac
4120 STOP^
4121 032531 254 04 0 00 032532 HALT .+1 ;Test failed if program halts here
4122 032532 324 00 0 00 032533 JUMPA .+1 ;To loop change this instruction^
4123
4124 ;**********
4125
4126 002006 SN=SN+1
4127 000005 ZZ=ZZ+1
4128 000016 XX=XX+5
4129 032533 201 06 0 00 777767 MOVEI ZZ+1,ZZ-XX ;Setup index register
4130 032534 201 05 0 06 000016 MOVEI ZZ,XX(ZZ+1) ;*Test indexing
4131 032535 302 05 0 00 000005 CAIE ZZ,ZZ ;Pass if c(ac)=0,,address of ac
4132 STOP^
4133 032536 254 04 0 00 032537 HALT .+1 ;Test failed if program halts here
4134 032537 324 00 0 00 032540 JUMPA .+1 ;To loop change this instruction^
4135
4136 ;**********
4137
4138 002007 SN=SN+1
4139 000006 ZZ=ZZ+1
4140 000023 XX=XX+5
4141 032540 201 07 0 00 777763 MOVEI ZZ+1,ZZ-XX ;Setup index register
4142 032541 201 06 0 07 000023 MOVEI ZZ,XX(ZZ+1) ;*Test indexing
4143 032542 302 06 0 00 000006 CAIE ZZ,ZZ ;Pass if c(ac)=0,,address of ac
4144 STOP^
4145 032543 254 04 0 00 032544 HALT .+1 ;Test failed if program halts here
4146 032544 324 00 0 00 032545 JUMPA .+1 ;To loop change this instruction^
4147
4148 ;**********
4149
4150 002010 SN=SN+1
4151 000007 ZZ=ZZ+1
4152 000030 XX=XX+5
4153 032545 201 10 0 00 777757 MOVEI ZZ+1,ZZ-XX ;Setup index register
4154 032546 201 07 0 10 000030 MOVEI ZZ,XX(ZZ+1) ;*Test indexing
4155 032547 302 07 0 00 000007 CAIE ZZ,ZZ ;Pass if c(ac)=0,,address of ac
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 12-6
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0093
4156 STOP^
4157 032550 254 04 0 00 032551 HALT .+1 ;Test failed if program halts here
4158 032551 324 00 0 00 032552 JUMPA .+1 ;To loop change this instruction^
4159
4160 ;**********
4161
4162 002011 SN=SN+1
4163 000010 ZZ=ZZ+1
4164 000035 XX=XX+5
4165 032552 201 11 0 00 777753 MOVEI ZZ+1,ZZ-XX ;Setup index register
4166 032553 201 10 0 11 000035 MOVEI ZZ,XX(ZZ+1) ;*Test indexing
4167 032554 302 10 0 00 000010 CAIE ZZ,ZZ ;Pass if c(ac)=0,,address of ac
4168 STOP^
4169 032555 254 04 0 00 032556 HALT .+1 ;Test failed if program halts here
4170 032556 324 00 0 00 032557 JUMPA .+1 ;To loop change this instruction^
4171
4172 ;**********
4173
4174 002012 SN=SN+1
4175 000011 ZZ=ZZ+1
4176 000042 XX=XX+5
4177 032557 201 12 0 00 777747 MOVEI ZZ+1,ZZ-XX ;Setup index register
4178 032560 201 11 0 12 000042 MOVEI ZZ,XX(ZZ+1) ;*Test indexing
4179 032561 302 11 0 00 000011 CAIE ZZ,ZZ ;Pass if c(ac)=0,,address of ac
4180 STOP^
4181 032562 254 04 0 00 032563 HALT .+1 ;Test failed if program halts here
4182 032563 324 00 0 00 032564 JUMPA .+1 ;To loop change this instruction^
4183
4184 ;**********
4185
4186 002013 SN=SN+1
4187 000012 ZZ=ZZ+1
4188 000047 XX=XX+5
4189 032564 201 13 0 00 777743 MOVEI ZZ+1,ZZ-XX ;Setup index register
4190 032565 201 12 0 13 000047 MOVEI ZZ,XX(ZZ+1) ;*Test indexing
4191 032566 302 12 0 00 000012 CAIE ZZ,ZZ ;Pass if c(ac)=0,,address of ac
4192 STOP^
4193 032567 254 04 0 00 032570 HALT .+1 ;Test failed if program halts here
4194 032570 324 00 0 00 032571 JUMPA .+1 ;To loop change this instruction^
4195
4196 ;**********
4197
4198 002014 SN=SN+1
4199 000013 ZZ=ZZ+1
4200 000054 XX=XX+5
4201 032571 201 14 0 00 777737 MOVEI ZZ+1,ZZ-XX ;Setup index register
4202 032572 201 13 0 14 000054 MOVEI ZZ,XX(ZZ+1) ;*Test indexing
4203 032573 302 13 0 00 000013 CAIE ZZ,ZZ ;Pass if c(ac)=0,,address of ac
4204 STOP^
4205 032574 254 04 0 00 032575 HALT .+1 ;Test failed if program halts here
4206 032575 324 00 0 00 032576 JUMPA .+1 ;To loop change this instruction^
4207
4208 ;**********
4209
4210 002015 SN=SN+1
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 12-7
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INDEX REGISTER ADDRESSING SEQ 0094
4211 000014 ZZ=ZZ+1
4212 000061 XX=XX+5
4213 032576 201 15 0 00 777733 MOVEI ZZ+1,ZZ-XX ;Setup index register
4214 032577 201 14 0 15 000061 MOVEI ZZ,XX(ZZ+1) ;*Test indexing
4215 032600 302 14 0 00 000014 CAIE ZZ,ZZ ;Pass if c(ac)=0,,address of ac
4216 STOP^
4217 032601 254 04 0 00 032602 HALT .+1 ;Test failed if program halts here
4218 032602 324 00 0 00 032603 JUMPA .+1 ;To loop change this instruction^
4219
4220 ;**********
4221
4222 002016 SN=SN+1
4223 000015 ZZ=ZZ+1
4224 000066 XX=XX+5
4225 032603 201 16 0 00 777727 MOVEI ZZ+1,ZZ-XX ;Setup index register
4226 032604 201 15 0 16 000066 MOVEI ZZ,XX(ZZ+1) ;*Test indexing
4227 032605 302 15 0 00 000015 CAIE ZZ,ZZ ;Pass if c(ac)=0,,address of ac
4228 STOP^
4229 032606 254 04 0 00 032607 HALT .+1 ;Test failed if program halts here
4230 032607 324 00 0 00 032610 JUMPA .+1 ;To loop change this instruction^
4231
4232 ;**********
4233
4234 002017 SN=SN+1
4235 000016 ZZ=ZZ+1
4236 000073 XX=XX+5
4237 032610 201 17 0 00 777723 MOVEI ZZ+1,ZZ-XX ;Setup index register
4238 032611 201 16 0 17 000073 MOVEI ZZ,XX(ZZ+1) ;*Test indexing
4239 032612 302 16 0 00 000016 CAIE ZZ,ZZ ;Pass if c(ac)=0,,address of ac
4240 STOP^
4241 032613 254 04 0 00 032614 HALT .+1 ;Test failed if program halts here
4242 032614 324 00 0 00 032615 JUMPA .+1 ;To loop change this instruction^
4243
4244 ;**********
4245
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 13
DFKAD1 MAC 1-Oct-84 16:01 TEST OF EXCH INSTRUCTION SEQ 0095
4246 SUBTTL TEST OF EXCH INSTRUCTION
4247
4248 ;**********
4249
4250 ;This test verifies that exch moves c(e) into ac and moves c(ac) into e.
4251 ;In this case, ac=e=0 and c(ac)=c(e). hence, the final result in ac0
4252 ;Should be 0. if c(ac)=0, the test passes.
4253
4254 032615 400 00 0 00 000000 C2100: SETZ ;Preload ac,e with 0
4255 032616 250 00 0 00 000000 EXCH ;*Exch should place 0 into ac0
4256 032617 332 00 0 00 000000 SKIPE ;Pass if c(ac0)=0
4257 STOP^
4258 032620 254 04 0 00 032621 HALT .+1 ;Test failed if program halts here
4259 032621 324 00 0 00 032622 JUMPA .+1 ;To loop change this instruction^
4260
4261 ;**********
4262
4263 ;This test verifies that exch moves c(e) into ac and moves c(ac) into e.
4264 ;In this case, ac=e=-1,,-1 and c(ac)=c(e). hence, the final result in
4265 ;Ac0 should be -1,,-1. if c(ac)=-1,,-1, the test passes.
4266
4267 032622 474 00 0 00 000000 C2200: SETO ;Preload ac,e with -1,,-1
4268 032623 250 00 0 00 000000 EXCH ;*Exch should place -1,,-1 into ac0
4269 032624 312 00 0 00 034443 CAME [-1] ;Pass if c(ac0)=-1,,-1
4270 STOP^
4271 032625 254 04 0 00 032626 HALT .+1 ;Test failed if program halts here
4272 032626 324 00 0 00 032627 JUMPA .+1 ;To loop change this instruction^
4273
4274 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 14
DFKAD1 MAC 1-Oct-84 16:01 TEST OF EXCH INSTRUCTION SEQ 0096
4275 ;This test verifies that exch moves c(e) into ac and moves c(ac) into e.
4276 ;In this case, c(ac)=-1,,0 and c(e)=0,,-1. hence, the final result in
4277 ;The ac should be 0,,-1 and the result in e should be -1,,0. if these
4278 ;Results occur, the test passes.
4279
4280 032627 205 00 0 00 777777 C2400: MOVSI -1 ;Preload ac with -1,,0
4281 032630 201 01 0 00 777777 MOVEI 1,-1 ;Preload e with 0,,-1
4282 032631 250 00 0 00 000001 EXCH 1 ;*Exch should place 0,,-1 into ac and -1,,0 into e
4283 032632 312 01 0 00 034510 CAME 1,[-1,,0] ;Pass if c(e)=-1,,0
4284 STOP^
4285 032633 254 04 0 00 032634 HALT .+1 ;Test failed if program halts here
4286 032634 324 00 0 00 032635 JUMPA .+1 ;To loop change this instruction^
4287 032635 312 00 0 00 034511 C2410: CAME 0,[0,,-1] ;Pass if c(ac)=0,,-1
4288 STOP^
4289 032636 254 04 0 00 032637 HALT .+1 ;Test failed if program halts here
4290 032637 324 00 0 00 032640 JUMPA .+1 ;To loop change this instruction^
4291
4292 ;**********
4293
4294 ;This test verifies that exch moves c(e) into ac and moves c(ac) into e.
4295 ;In this case, c(ac)=0,,-1 and c(e)=-1,,0. hence, the final result in
4296 ;The ac should be -1,,0 and the result in e should be 0,,-1. if these
4297 ;Results occur, the test passes.
4298
4299 032640 201 00 0 00 777777 C2700: MOVEI -1 ;Preload ac with 0,,-1
4300 032641 205 01 0 00 777777 MOVSI 1,-1 ;Preload e with -1,,0
4301 032642 250 00 0 00 000001 EXCH 1 ;*Exch should place -1,,0 into ac and 0,,-1 into e
4302 032643 302 01 0 00 777777 CAIE 1,-1 ;Pass if c(e)=0,,-1
4303 STOP^
4304 032644 254 04 0 00 032645 HALT .+1 ;Test failed if program halts here
4305 032645 324 00 0 00 032646 JUMPA .+1 ;To loop change this instruction^
4306 032646 312 00 0 00 034510 C2710: CAME ,[XWD -1,0] ;Pass if c(ac)=-1,,0
4307 STOP^
4308 032647 254 04 0 00 032650 HALT .+1 ;Test failed if program halts here
4309 032650 324 00 0 00 032651 JUMPA .+1 ;To loop change this instruction^
4310
4311 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 15
DFKAD1 MAC 1-Oct-84 16:01 TEST OF EXCH INSTRUCTION SEQ 0097
4312 ;This test is a reliability check of exch. first, ac, e are preloaded
4313 ;With 252525,,252525. there, exch is executed 7 times. the ac is then
4314 ;Checked for 252525,,252525. if c(ac)=c(e)=252525,,252525, this test
4315 ;Passes. in this test ac=e=ac0.
4316
4317 032651 200 00 0 00 034512 C3000: MOVE [252525252525] ;Preload ac,e with 252525,,252525
4318 REPEAT 7,
4319 < EXCH ;*Exch should place 252525,,252525 into ac0>
4320 032652 250 00 0 00 000000 EXCH ;*Exch should place 252525,,252525 into ac0
4321 032653 250 00 0 00 000000 EXCH ;*Exch should place 252525,,252525 into ac0
4322 032654 250 00 0 00 000000 EXCH ;*Exch should place 252525,,252525 into ac0
4323 032655 250 00 0 00 000000 EXCH ;*Exch should place 252525,,252525 into ac0
4324 032656 250 00 0 00 000000 EXCH ;*Exch should place 252525,,252525 into ac0
4325 032657 250 00 0 00 000000 EXCH ;*Exch should place 252525,,252525 into ac0
4326 032660 250 00 0 00 000000 EXCH ;*Exch should place 252525,,252525 into ac0
4327 032661 312 00 0 00 034512 CAME [252525252525] ;Pass if c(ac0)=252525,,252525
4328 STOP^
4329 032662 254 04 0 00 032663 HALT .+1 ;Test failed if program halts here
4330 032663 324 00 0 00 032664 JUMPA .+1 ;To loop change this instruction^
4331
4332 ;**********
4333
4334 ;This test verifies that exch moves c(ac) into e and c(e) into the ac.
4335 ;In this case, c(ac)=0 and c(e)=-1,,-1. exch is executed 7 times; then,
4336 ;The ac is checked for -1,,-1 and e is checked for 0. if either of these
4337 ;Results are not found, this test fails.
4338
4339 032664 400 00 0 00 000000 C3100: SETZ ;Preload ac with 0
4340 032665 474 01 0 00 000000 SETO 1,0 ;Preload e with -1,,-1
4341 REPEAT 7,
4342 < EXCH 1 ;*Exch should exchange c(ac) and c(e)>
4343 032666 250 00 0 00 000001 EXCH 1 ;*Exch should exchange c(ac) and c(e)
4344 032667 250 00 0 00 000001 EXCH 1 ;*Exch should exchange c(ac) and c(e)
4345 032670 250 00 0 00 000001 EXCH 1 ;*Exch should exchange c(ac) and c(e)
4346 032671 250 00 0 00 000001 EXCH 1 ;*Exch should exchange c(ac) and c(e)
4347 032672 250 00 0 00 000001 EXCH 1 ;*Exch should exchange c(ac) and c(e)
4348 032673 250 00 0 00 000001 EXCH 1 ;*Exch should exchange c(ac) and c(e)
4349 032674 250 00 0 00 000001 EXCH 1 ;*Exch should exchange c(ac) and c(e)
4350 032675 312 00 0 00 034443 CAME [-1] ;Pass if c(ac)=-1,,-1
4351 STOP^
4352 032676 254 04 0 00 032677 HALT .+1 ;Test failed if program halts here
4353 032677 324 00 0 00 032700 JUMPA .+1 ;To loop change this instruction^
4354 032700 312 01 0 00 034513 C3110: CAME 1,[0] ;Pass if c(e)=0
4355 STOP^
4356 032701 254 04 0 00 032702 HALT .+1 ;Test failed if program halts here
4357 032702 324 00 0 00 032703 JUMPA .+1 ;To loop change this instruction^
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 16
DFKAD1 MAC 1-Oct-84 16:01 TEST OF MOVEM INSTRUCTION SEQ 0098
4358 SUBTTL TEST OF MOVEM INSTRUCTION
4359
4360 ;This test verifies that movem places c(ac) into e and does not modify c(ac)
4361 ;In this case, c(ac)=-1,,-1 and c(e)=0. hence, the result in ac and e should
4362 ;Be -1,,-1. if c(ac) and c(e)=-1,,-1, this test passes
4363
4364 032703 474 00 0 00 000000 C3200: SETO ;Preload ac with -1,,-1
4365 032704 400 01 0 00 000000 SETZ 1,0 ;Preload e with 0
4366 032705 202 00 0 00 000001 MOVEM 1 ;*Movem should place -1,,-1 into e
4367 032706 312 01 0 00 034443 CAME 1,[-1] ;Pass if c(e)=-1,,-1
4368 STOP^
4369 032707 254 04 0 00 032710 HALT .+1 ;Test failed if program halts here
4370 032710 324 00 0 00 032711 JUMPA .+1 ;To loop change this instruction^
4371 032711 312 00 0 00 034443 C3210: CAME 0,[-1] ;Pass if c(ac)=-1,,-1
4372 STOP^
4373 032712 254 04 0 00 032713 HALT .+1 ;Test failed if program halts here
4374 032713 324 00 0 00 032714 JUMPA .+1 ;To loop change this instruction^
4375
4376 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 17
DFKAD1 MAC 1-Oct-84 16:01 TEST OF JFCL INSTRUCTION AND ARITHMETIC FLAGS SEQ 0099
4377 SUBTTL TEST OF JFCL INSTRUCTION AND ARITHMETIC FLAGS
4378
4379 ;**********
4380
4381 ;This test verifies that jfcl 17,.+1 always returns to the next sequential
4382 ;Instruction. if jfcl skips the next instruction, this test fails.
4383
4384 032714 200 00 0 00 034514 C3300: MOVE [HALT .+3] ;This instruction should not affect the test
4385 032715 255 17 0 00 032716 JFCL 17,.+1 ;*Jfcl should return to next sequential instruction
4386 032716 304 00 0 00 000000 CAIA ;Skip halt instruction if jfcl passes
4387 STOP^
4388 032717 254 04 0 00 032720 HALT .+1 ;Test failed if program halts here
4389 032720 324 00 0 00 032721 JUMPA .+1 ;To loop change this instruction^
4390
4391 ;**********
4392
4393 ;This test verifies that jfcl 17,.+1 always clears the cry0 flag. addi is
4394 ;Used to set cry0. then, jfcl 17,.+1 is executed to clear cry0. jfcl 4,.+2
4395 ;Is executed to determine whether cry0 was reset by the previous jfcl. this
4396 ;Test fails if jfcl 17,.+1 did not clear cry0.
4397
4398 032721 200 00 0 00 034443 C3400: MOVE [-1] ;Preload ac with -1,,-1
4399 032722 271 00 0 00 000001 ADDI 1 ;Set cry0 flag
4400 032723 255 17 0 00 032724 JFCL 17,.+1 ;*Clear arithmetic flags
4401 032724 255 04 0 00 032726 JFCL 4,.+2 ;Pass if cry0 was reset by previous instruction
4402 032725 334 00 0 00 000000 SKIPA ;Skip halt if cry0 was cleared
4403 STOP^
4404 032726 254 04 0 00 032727 HALT .+1 ;Test failed if program halts here
4405 032727 324 00 0 00 032730 JUMPA .+1 ;To loop change this instruction^
4406
4407 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 18
DFKAD1 MAC 1-Oct-84 16:01 TEST OF JFCL INSTRUCTION AND ARITHMETIC FLAGS SEQ 0100
4408 ;This test verifies that jfcl 17,.+1 always clears the cry1 flag.
4409 ;Addi is used to set cry1. then, jfcl 17,.+1 is executed to clear cry1.
4410 ;Jfcl 4,.+2 is executed to determine whether cry1 was reset by the previous jfcl.
4411 ;This test fails if jfcl 17,.+1 did not clear cry1.
4412
4413 032730 200 00 0 00 034443 C3500: MOVE [-1] ;Preload ac with -1,,-1
4414 032731 271 00 0 00 000001 ADDI 1 ;Set cry1 flag
4415 032732 255 17 0 00 032733 JFCL 17,.+1 ;*Clear arithmetic flags
4416 032733 255 02 0 00 032735 JFCL 2,.+2 ;Pass if cry1 was reset by previous instruction
4417 032734 334 00 0 00 000000 SKIPA ;Skip halt if cry1 was cleared
4418 STOP^
4419 032735 254 04 0 00 032736 HALT .+1 ;Test failed if program halts here
4420 032736 324 00 0 00 032737 JUMPA .+1 ;To loop change this instruction^
4421
4422 ;**********
4423
4424 ;This test verifies that jfcl 17,.+1 always clears the arov flag.
4425 ;Addi is used to set arov. then, jfcl 17,.+1 is executed to clear arov.
4426 ;Jfcl 4,.+2 is executed to determine whether arov was reset by the previous jfcl.
4427 ;This test fails if jfcl 17,.+1 did not clear arov.
4428
4429 032737 205 00 0 00 400000 C3600: MOVSI 400000 ;Preload ac with -1,,-1
4430 032740 270 00 0 00 034442 ADD [XWD 400000,0] ;Set arov flag
4431 032741 255 17 0 00 032742 JFCL 17,.+1 ;*Clear arithmetic flags
4432 032742 255 10 0 00 032744 JFCL 10,.+2 ;Pass if arov was reset by previous instruction
4433 032743 334 00 0 00 000000 SKIPA ;Skip halt if arov was cleared
4434 STOP^
4435 032744 254 04 0 00 032745 HALT .+1 ;Test failed if program halts here
4436 032745 324 00 0 00 032746 JUMPA .+1 ;To loop change this instruction^
4437
4438 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 19
DFKAD1 MAC 1-Oct-84 16:01 TEST OF JFCL INSTRUCTION AND ARITHMETIC FLAGS SEQ 0101
4439 ;This test verifies that jfcl 0, is a no-op.
4440 ;In this test, add is used to set cry0. then jfcl 0,.+2 is executed.
4441 ;If jfcl 0,.+2 does not skip the next instruction, this test passes.
4442
4443 032746 205 00 0 00 400000 C3700: MOVSI 400000 ;Preload ac with most negative number
4444 032747 270 00 0 00 034443 ADD [-1] ;Set cry0 flag
4445 032750 255 00 0 00 032752 JFCL .+2 ;*Jfcl should return to next sequential instruction
4446 032751 334 00 0 00 000000 SKIPA ;Pass if jfcl did not skip
4447 STOP^
4448 032752 254 04 0 00 032753 HALT .+1 ;Test failed if program halts here
4449 032753 324 00 0 00 032754 JUMPA .+1 ;To loop change this instruction^
4450
4451 ;**********
4452
4453 ;This test verifies that jfcl 0, is a no-op.
4454 ;In this test, add is used to set cry1. then jfcl 0,.+2 is executed.
4455 ;If jfcl 0,.+2 does not skip the next instruction, this test passes.
4456
4457 032754 205 00 0 00 200000 C4000: MOVSI 200000 ;Preload ac with most negative number
4458 032755 270 00 0 00 034441 ADD [XWD 200000,0] ;Set cry1 flag
4459 032756 255 00 0 00 032760 JFCL .+2 ;*Jfcl should return to next sequential instruction
4460 032757 334 00 0 00 000000 SKIPA ;Pass if jfcl did not skip
4461 STOP^
4462 032760 254 04 0 00 032761 HALT .+1 ;Test failed if program halts here
4463 032761 324 00 0 00 032762 JUMPA .+1 ;To loop change this instruction^
4464
4465 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 20
DFKAD1 MAC 1-Oct-84 16:01 TEST OF JFCL INSTRUCTION AND ARITHMETIC FLAGS SEQ 0102
4466 ;This test verifies that addi has the ability to set an arithmetic flag and
4467 ;That 'jfcl 17,.+2' jumps whenever any arithmetic flag is set. in this test,
4468 ;Addi should set cry0 and cry1. then, jfcl should skip because a flag was set
4469 ;By addi. if this test fails, addi could have failed to set a flag or jfcl
4470 ;Could have failed to jump when a flag was set.
4471
4472 032762 200 00 0 00 034443 C4100: MOVE [-1] ;Preload ac with all ones
4473 032763 271 00 0 00 000001 ADDI 1 ;*Addi should set cry0/1 flags
4474 032764 255 17 0 00 032766 JFCL 17,.+2 ;*Jfcl should jump because flags are set
4475 STOP^
4476 032765 254 04 0 00 032766 HALT .+1 ;Test failed if program halts here
4477 032766 324 00 0 00 032767 JUMPA .+1 ;To loop change this instruction^
4478
4479 ;**********
4480
4481 ;This test verifies that cai does not clear any arithmetic flags.
4482 ;First, cry0 and cry1 are set by addi; then cai is executed.
4483 ;Jfcl should jump because flags are set. if jfcl does not jump,
4484 ;The flags were cleared by cai. hence, cai failed.
4485
4486 032767 200 00 0 00 034443 C4200: MOVE [-1] ;Preload ac with -1,,-1
4487 032770 271 00 0 00 000001 ADDI 1 ;Set cyr0/1 flags
4488 032771 300 17 0 00 000017 CAI 17,17 ;*Cai should not clear flags
4489 032772 255 17 0 00 032774 JFCL 17,.+2 ;Pass if cai cleared flags
4490 STOP^
4491 032773 254 04 0 00 032774 HALT .+1 ;Test failed if program halts here
4492 032774 324 00 0 00 032775 JUMPA .+1 ;To loop change this instruction^
4493
4494 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 21
DFKAD1 MAC 1-Oct-84 16:01 TEST OF JFCL INSTRUCTION AND ARITHMETIC FLAGS SEQ 0103
4495 ;This test verifies that addi has the ability to set an arithmetic flag and
4496 ;That 'jfcl 17,.+2' jumps whenever any arithmetic flag is set. in this test,
4497 ;Addi should set cry0 and cry1. then jfcl should skip because a flag was set
4498 ;By addi. if this test fails, addi could have failed to set a flag or jfcl
4499 ;Could have failed to jump when a flag was set.
4500
4501 032775 200 00 0 00 034443 C4300: MOVE [-1] ;Preload ac with all ones
4502 032776 271 00 0 00 000001 ADDI 1 ;*Addi should set cry1 flags
4503 032777 255 02 0 00 033001 JFCL 2,.+2 ;*Jfcl should jump because cry1 flag is set
4504 STOP^
4505 033000 254 04 0 00 033001 HALT .+1 ;Test failed if program halts here
4506 033001 324 00 0 00 033002 JUMPA .+1 ;To loop change this instruction^
4507
4508 ;**********
4509
4510 ;This test verifies that addi has the ability to set an arithmetic flag and
4511 ;That 'jfcl 17,.+2' jumps whenever any arithmetic flag is set. in this test,
4512 ;Addi should set cry0 and cry1. then, jfcl should skip because a flag was
4513 ;Set by addi. if this test fails, addi could have failed to set a flag or
4514 ;Jfcl could have failed to jump when a flag was set.
4515
4516 033002 200 00 0 00 034443 C4400: MOVE [-1] ;Preload ac with all ones
4517 033003 271 00 0 00 000001 ADDI 1 ;*Addi should set cry0 flag
4518 033004 255 04 0 00 033006 JFCL 4,.+2 ;*Jfcl should jump because cry0 flag is set
4519 STOP^
4520 033005 254 04 0 00 033006 HALT .+1 ;Test failed if program halts here
4521 033006 324 00 0 00 033007 JUMPA .+1 ;To loop change this instruction^
4522
4523 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 22
DFKAD1 MAC 1-Oct-84 16:01 TEST OF JFCL INSTRUCTION AND ARITHMETIC FLAGS SEQ 0104
4524 ;This test verifies that addi has the ability to set an arithmetic flag and
4525 ;That 'jfcl 17,.+2' jumps whenever any arithmetic flag is set. because a flag
4526 ;Was set by add. if this test fails, addi could have failed to set a flag or
4527 ;Jfcl could have failed to jump when a flag was set.
4528
4529 033007 205 00 0 00 400000 C4500: MOVSI 400000 ;Preload ac with all ones
4530 033010 270 00 0 00 034442 ADD [XWD 400000,0] ;*Add should set arov flag
4531 033011 255 10 0 00 033013 JFCL 10,.+2 ;*Jfcl should jump because arov flag is set
4532 STOP^
4533 033012 254 04 0 00 033013 HALT .+1 ;Test failed if program halts here
4534 033013 324 00 0 00 033014 JUMPA .+1 ;To loop change this instruction^
4535
4536 ;**********
4537
4538 ;This test verifies that jfcl 17,.+1 always clears the floating overflow
4539 ;Flag (fov). first jfcl 17,.+1 is executed to clear fov. then, jfcl 1,.+2
4540 ;Is executed to determine whether fov was cleared. if fov was clear, this
4541 ;Test passes.
4542
4543 033014 255 17 0 00 033015 C4600: JFCL 17,.+1 ;*Clear arithmetic flags
4544 033015 255 01 0 00 033017 JFCL 1,.+2 ;Pass if fov was cleared
4545 033016 334 00 0 00 000000 SKIPA ;Skip halt if test passed
4546 STOP^
4547 033017 254 04 0 00 033020 HALT .+1 ;Test failed if program halts here
4548 033020 324 00 0 00 033021 JUMPA .+1 ;To loop change this instruction^
4549
4550 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 23
DFKAD1 MAC 1-Oct-84 16:01 TEST OF JFCL INSTRUCTION AND ARITHMETIC FLAGS SEQ 0105
4551 ;This test verifies that jfcl 13, does not reset cry0.
4552 ;First cry0 and cry1 are set by addi; then, jfcl 13,.+2 is executed
4553 ;To clear all arithmetic flags except cry0.
4554 ;This test passes if jfcl 13,.+1 did not reset cry0.
4555
4556 033021 200 00 0 00 034443 C4700: MOVE [-1] ;Reload ac with -1,,-1
4557 033022 271 00 0 00 000001 ADDI 1 ;Set cry0/1
4558 033023 255 13 0 00 033024 JFCL 13,.+1 ;*Jfcl 13, should not reset cry0
4559 033024 255 04 0 00 033026 JFCL 4,.+2 ;Fail if cry 0 was reset
4560 STOP^
4561 033025 254 04 0 00 033026 HALT .+1 ;Test failed if program halts here
4562 033026 324 00 0 00 033027 JUMPA .+1 ;To loop change this instruction^
4563
4564 ;**********
4565
4566 ;This test verifies that jfcl 15, does not reset cry1.
4567 ;First cry0 and cry1 are set by addi; then, jfcl15,.+2 is executed
4568 ;To clear all arithmetic flags except cry1.
4569 ;This test passes if jfcl 15,.+1 did not reset cry1.
4570
4571 033027 200 00 0 00 034443 C5000: MOVE [-1] ;Preload ac with -1,,-1
4572 033030 271 00 0 00 000001 ADDI 1 ;Set cry0/1
4573 033031 255 15 0 00 033032 JFCL 15,.+1 ;*Jfcl15, should not reset cry0
4574 033032 255 02 0 00 033034 JFCL 2,.+2 ;Fail if cry1 was reset
4575 STOP^
4576 033033 254 04 0 00 033034 HALT .+1 ;Test failed if program halts here
4577 033034 324 00 0 00 033035 JUMPA .+1 ;To loop change this instruction^
4578
4579 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 24
DFKAD1 MAC 1-Oct-84 16:01 TEST OF JFCL INSTRUCTION AND ARITHMETIC FLAGS SEQ 0106
4580 ;This test verifies that jfcl 17, does not reset arov.
4581 ;First arov is set by add; then, jfcl 17,.+2 is executed
4582 ;To clear all arithmetic flags except arov.
4583 ;This test passes if jfcl 17,.+1 did not reset arov.
4584
4585 033035 205 00 0 00 400000 C5100: MOVSI 400000 ;Preload ac with -1,,-1
4586 033036 270 00 0 00 034442 ADD [XWD 400000,0] ;Set arov
4587 033037 255 07 0 00 033040 JFCL 7,.+1 ;*Jfcl 17, should not reset arov
4588 033040 255 10 0 00 033042 JFCL 10,.+2 ;Fail if arov was reset
4589 STOP^
4590 033041 254 04 0 00 033042 HALT .+1 ;Test failed if program halts here
4591 033042 324 00 0 00 033043 JUMPA .+1 ;To loop change this instruction^
4592
4593 ;**********
4594
4595 ;This test verifies that add of 0 to 0 will not set arov.
4596 ;First, all flags are reset, then 0 is added to 0 via add.
4597 ;Arov is then checked. if arov is set, this test fails.
4598
4599 033043 255 17 0 00 033044 C5200: JFCL 17,.+1 ;Reset arithmetic flags
4600 033044 400 00 0 00 000000 SETZ ;Preload ac,e with 0
4601 033045 270 00 0 00 000000 ADD ;*Add should not set arov
4602 033046 255 10 0 00 033050 JFCL 10,.+2 ;Pass if arov was reset
4603 033047 334 00 0 00 000000 SKIPA ;Skip halt if add passed
4604 STOP^
4605 033050 254 04 0 00 033051 HALT .+1 ;Test failed if program halts here
4606 033051 324 00 0 00 033052 JUMPA .+1 ;To loop change this instruction^
4607
4608 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 25
DFKAD1 MAC 1-Oct-84 16:01 TEST OF JFCL INSTRUCTION AND ARITHMETIC FLAGS SEQ 0107
4609 ;This test verifies that add of 0 to 0 will not set cry0.
4610 ;First, all flags are reset, then 0 is added to 0 via add.
4611 ;Cry0 is then checked. if cry0 is set, this test fails.
4612
4613
4614 033052 400 00 0 00 000000 C5300: SETZ ;Reset arithmetic flags
4615 033053 255 17 0 00 033054 JFCL 17,.+1 ;Preload ac,e with 0
4616 033054 270 00 0 00 000000 ADD ;*Add should not set cry0
4617 033055 255 04 0 00 033057 JFCL 4,.+2 ;Pass if cry0 was reset
4618 033056 334 00 0 00 000000 SKIPA ;Skip halt if add passed
4619 STOP^
4620 033057 254 04 0 00 033060 HALT .+1 ;Test failed if program halts here
4621 033060 324 00 0 00 033061 JUMPA .+1 ;To loop change this instruction^
4622
4623 ;**********
4624
4625 ;This test verifies that add of 0 to 0 will not set cry1.
4626 ;First, all flags are reset, then 0 is added to 0 via add.
4627 ;Cry1 is then checked. if cry1 is set, this test fails.
4628
4629 033061 400 00 0 00 000000 C5400: SETZ ;Reset arithmetic flags
4630 033062 255 17 0 00 033063 JFCL 17,.+1 ;Preload ac,e with 0
4631 033063 270 00 0 00 000000 ADD ;*Add should not set cry1
4632 033064 255 02 0 00 033066 JFCL 2,.+2 ;Pass if cry1 was reset
4633 033065 334 00 0 00 000000 SKIPA ;Skip halt if add passed
4634 STOP^
4635 033066 254 04 0 00 033067 HALT .+1 ;Test failed if program halts here
4636 033067 324 00 0 00 033070 JUMPA .+1 ;To loop change this instruction^
4637
4638 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 26
DFKAD1 MAC 1-Oct-84 16:01 TEST OF JFCL INSTRUCTION AND ARITHMETIC FLAGS SEQ 0108
4639 ;This test verifies that the 30x and the 31x instruction groups do not affect
4640 ;The arithmetic flags. first, the flags are cleared and ac0 is cleared; then,
4641 ;Cai and cam are executed. the flags are then checked. if any of the flags
4642 ;Are set, this test fails and cai or cam is considered to have erroneously set
4643 ;The flags.
4644
4645 033070 255 17 0 00 033071 C5500: JFCL 17,.+1 ;Clear all flags
4646 033071 400 00 0 00 000000 SETZ ;Clear ac,0
4647 033072 300 00 0 00 000000 CAI ;*Cai should not set any arithmetic flag
4648 033073 310 00 0 00 034443 CAM [-1] ;*Cam should not set any arithmetic flag
4649 033074 255 17 0 00 033076 JFCL 17,.+2 ;Fail if any flag was set
4650 033075 334 00 0 00 000000 SKIPA ;Skip halt if test passed
4651 STOP^
4652 033076 254 04 0 00 033077 HALT .+1 ;Test failed if program halts here
4653 033077 324 00 0 00 033100 JUMPA .+1 ;To loop change this instruction^
4654
4655 ;**********
4656
4657 ;This test verifies that the boolean instruction groups do not affect the
4658 ;Arithmetic flags. first the flags are cleared and ac0 is cleared; then,
4659 ;Xor [0] and xor [-1] are executed. the flags are then checked. if any
4660 ;Of the flags are set, this test fails and xor is considered to have
4661 ;Erroneously set the flags.
4662
4663 033100 255 17 0 00 033101 C5600: JFCL 17,.+1 ;Clear all flags
4664 033101 474 00 0 00 000000 SETO ;Clear ac,0
4665 033102 430 00 0 00 034513 XOR [0] ;*Xor should not set any arithmetic flag
4666 033103 430 00 0 00 034443 XOR [-1] ;*Xor should not set any arithmetic flag
4667 033104 255 17 0 00 033106 JFCL 17,.+2 ;Fail if any flag was set
4668 033105 334 00 0 00 000000 SKIPA ;Skip halt if test passed
4669 STOP^
4670 033106 254 04 0 00 033107 HALT .+1 ;Test failed if program halts here
4671 033107 324 00 0 00 033110 JUMPA .+1 ;To loop change this instruction^
4672
4673 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 27
DFKAD1 MAC 1-Oct-84 16:01 TEST OF JFCL INSTRUCTION AND ARITHMETIC FLAGS SEQ 0109
4674 ;This test verifies that the aobjx instruction group does do not affect the
4675 ;Arithmetic flags. first the flags are cleared and ac0 is cleared; then, aobjn
4676 ;And aobjp are executed. the flags are then checked. if any of the flags are
4677 ;Set, this test fails and aobjn or aobjp is considered to have erroneously set
4678 ;The flags.
4679
4680 033110 474 00 0 00 000000 C5700: SETO ;Clear all flags
4681 033111 255 17 0 00 033112 JFCL 17,.+1 ;Clear ac,0
4682 033112 253 00 0 00 033113 AOBJN .+1 ;*Aobjn should not set any arithmetic arithmetic
4683 033113 252 00 0 00 033114 AOBJP .+1 ;*Aobjp should not set any arithmetic flag
4684 033114 255 17 0 00 033116 JFCL 17,.+2 ;Fail if any flag was set
4685 033115 334 00 0 00 000000 SKIPA ;Skip halt if tst passed
4686 STOP^
4687 033116 254 04 0 00 033117 HALT .+1 ;Test failed if program halts here
4688 033117 324 00 0 00 033120 JUMPA .+1 ;To loop change this instruction^
4689
4690 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 28
DFKAD1 MAC 1-Oct-84 16:01 TEST OF JFCL INSTRUCTION AND ARITHMETIC FLAGS SEQ 0110
4691 ;This test verifies that skip does not affect the flags.
4692 ;First, the arithmetic flags are cleared; then, skip is executed.
4693 ;If skip sets arov, cryo, cry1 or fov, this test fails.
4694
4695 033120 255 17 0 00 033121 C5701: JFCL 17,.+1 ;Clear all flags
4696 033121 330 00 0 00 034443 SKIP 0,[-1] ;*Skip should not set any flags
4697 033122 255 17 0 00 033124 JFCL 17,.+2 ;Fail if any flag is set
4698 033123 334 00 0 00 000000 SKIPA ;Pass if no flag is set
4699 STOP^
4700 033124 254 04 0 00 033125 HALT .+1 ;Test failed if program halts here
4701 033125 324 00 0 00 033126 JUMPA .+1 ;To loop change this instruction^
4702
4703 ;**********
4704
4705 ;This test verifies that jump does not affect the flags.
4706 ;First, the arithmetic flags are cleared; then, jump is executed.
4707 ;If jump sets arov, cryo, cry1 or fov, this test fails.
4708
4709 033126 255 17 0 00 033127 C5702: JFCL 17,.+1 ;Clear all flags
4710 033127 320 00 0 00 034443 JUMP 0,[-1] ;*Jump should not set any flags
4711 033130 255 17 0 00 033132 JFCL 17,.+2 ;Fail if any flag is set
4712 033131 334 00 0 00 000000 SKIPA ;Pass if no flag is set
4713 STOP^
4714 033132 254 04 0 00 033133 HALT .+1 ;Test failed if program halts here
4715 033133 324 00 0 00 033134 JUMPA .+1 ;To loop change this instruction^
4716
4717 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 29
DFKAD1 MAC 1-Oct-84 16:01 TEST OF JRST INSTRUCTION AND ARITHMETIC FLAGS SEQ 0111
4718 SUBTTL TEST OF JRST INSTRUCTION AND ARITHMETIC FLAGS
4719
4720 ;**********
4721
4722 ;This test verifies that 'jrst, 0' does not set any flags.
4723 ;First the arithmetic flags are reset; then, 'jrst 0,.+1' is executed
4724 ;The arov,cry0 and cry1 flags are then checked. if any
4725 ;Of these flags are set, this test fails
4726
4727 033134 255 17 0 00 033135 C6000: JFCL 17,.+1 ;Reset all flags
4728 033135 254 00 0 00 033136 JRST .+1 ;*Jrst should not set any flags
4729 033136 255 16 0 00 033140 JFCL 16,.+2 ;Pass if no flags are set
4730 033137 334 00 0 00 000000 SKIPA ;Skip halt if jrst passes
4731 STOP^
4732 033140 254 04 0 00 033141 HALT .+1 ;Test failed if program halts here
4733 033141 324 00 0 00 033142 JUMPA .+1 ;To loop change this instruction^
4734
4735 ;**********
4736
4737 ;This test verifies that 'move 2,2' does not set any flags.
4738 ;First, the arithmetic flags are reset; then, 'move 2,2' is executed.
4739 ;The fov,arov,cry0 and cry1 flags are then checked. if any
4740 ;Of these flags are set, this test fails.
4741
4742 033142 255 17 0 00 033143 C6100: JFCL 17,.+1 ;Reset all flags
4743 033143 200 02 0 00 000002 MOVE 2,2 ;*Move should not set any flags
4744 033144 255 17 0 00 033146 JFCL 17,.+2 ;Pass if no flags are set
4745 033145 334 00 0 00 000000 SKIPA ;Skip halt if move passed
4746 STOP^
4747 033146 254 04 0 00 033147 HALT .+1 ;Test failed if program halts here
4748 033147 324 00 0 00 033150 JUMPA .+1 ;To loop change this instruction^
4749
4750 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 30
DFKAD1 MAC 1-Oct-84 16:01 TEST OF JRST INSTRUCTION AND ARITHMETIC FLAGS SEQ 0112
4751 ;This test verifies that jrst 2,.+1(1) will set the arithmetic flag
4752 ;Specified in ac1. in this case, ac1 specifies the cry0 flag.
4753 ;First, all flags are reset; then ac1 is set to specify cry0.
4754 ;Next, jrst 2,.+1(1) is executed to set cry0. cry0 is then checked. if
4755 ;Cry0 is set, this test passes. otherwise, jrst 2,.+1 is faulty.
4756
4757 033150 255 17 0 00 033151 C6200: JFCL 17,.+1 ;Clear all flags
4758 SFLAG CRY0 ^;Set cry0 flag
4759
4760 033151 205 01 0 00 200000 MOVSI 1,CRY0
4761 033152 255 17 0 00 033153 JFCL 17,.+1 ;Reset all flags
4762 033153 254 02 0 01 033154 JRST 2,.+1(1) ;Set CRY0 flag
4763 033154 255 04 0 00 033156 JFCL 4,.+2 ;Pass if cry0 is set
4764 STOP^
4765 033155 254 04 0 00 033156 HALT .+1 ;Test failed if program halts here
4766 033156 324 00 0 00 033157 JUMPA .+1 ;To loop change this instruction^
4767
4768 ;**********
4769
4770 ;This test verifies that jrst 2,.+(1) will set the arithmetic flag
4771 ;Specified in ac1. in this case, ac1 contain 0. hence, jrst 2,.+1(1)
4772 ;Should reset the arithmetic flags. first, the cry0/1, flags are set by addi;
4773 ;Then the flags should be cleared by jrst 2,.+1. if cry1 was cleared, the
4774 ;Test passes. otherwise, jrst 2,.+1 is faulty.
4775
4776 033157 200 00 0 00 034443 C6300: MOVE [-1] ;Preload ac0 with -1,,-1
4777 033160 271 00 0 00 000001 ADDI 1 ;Set cry0/1 flags
4778 SFLAG 0 ^;Reset all arithmetic flags
4779
4780 033161 205 01 0 00 000000 MOVSI 1,0
4781 033162 255 17 0 00 033163 JFCL 17,.+1 ;Reset all flags
4782 033163 254 02 0 01 033164 JRST 2,.+1(1) ;Set 0 flag
4783 033164 255 02 0 00 033166 JFCL 2,.+2 ;Pass if cry1 is reset
4784 033165 334 00 0 00 000000 SKIPA ;Skip halt instruction if test passed
4785 STOP^
4786 033166 254 04 0 00 033167 HALT .+1 ;Test failed if program halts here
4787 033167 324 00 0 00 033170 JUMPA .+1 ;To loop change this instruction^
4788
4789 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 31
DFKAD1 MAC 1-Oct-84 16:01 TEST OF JRST INSTRUCTION AND ARITHMETIC FLAGS SEQ 0113
4790
4791 ;This test verifies that jrst 2,.+(1) will set the arithmetic flag
4792 ;Specified in ac1. in this case, ac1 contain 0. hence, jrst 2,.+1(1)
4793 ;Should reset the arithmetic flags. first, the cry0/1, flags are set by add
4794 ;Then the flags should be cleared by jrst 2,.+1. if arov was cleared, the
4795 ;Test passes. otherwise, jrst 2,.+1 is faulty.
4796
4797 033170 205 00 0 00 400000 C6400: MOVSI 400000 ;Preload ac0 with -1,,-1
4798 033171 270 00 0 00 034443 ADD [-1] ;Set cry0 and arov flags
4799 SFLAG 0 ^;Reset all arithmetic flags
4800
4801 033172 205 01 0 00 000000 MOVSI 1,0
4802 033173 255 17 0 00 033174 JFCL 17,.+1 ;Reset all flags
4803 033174 254 02 0 01 033175 JRST 2,.+1(1) ;Set 0 flag
4804 033175 255 10 0 00 033177 JFCL 10,.+2 ;Pass if arov is reset
4805 033176 334 00 0 00 000000 SKIPA ;Skip halt instruction if test passed
4806 STOP^
4807 033177 254 04 0 00 033200 HALT .+1 ;Test failed if program halts here
4808 033200 324 00 0 00 033201 JUMPA .+1 ;To loop change this instruction^
4809
4810 ;**********
4811
4812 ;This test verifies that jrst 2,.+1(1) will set the arithmetic flag
4813 ;Specified in ac1. in this case, ac1 specifies the arov flag.
4814 ;First, all flags are reset; then ac1 set to specify arov.
4815 ;Next, jrst 2,.+1(1) is executed to set arov. arov is then checked. if
4816 ;Arov is set, this test passes. otherwise, jrst 2,.+1 is faulty.
4817
4818 033201 C6500: SFLAG AROV ^;Set arov flag
4819
4820 033201 205 01 0 00 400000 MOVSI 1,AROV
4821 033202 255 17 0 00 033203 JFCL 17,.+1 ;Reset all flags
4822 033203 254 02 0 01 033204 JRST 2,.+1(1) ;Set AROV flag
4823 033204 255 10 0 00 033206 JFCL 10,.+2 ;Pass if arov was set
4824 STOP^
4825 033205 254 04 0 00 033206 HALT .+1 ;Test failed if program halts here
4826 033206 324 00 0 00 033207 JUMPA .+1 ;To loop change this instruction^
4827
4828 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 32
DFKAD1 MAC 1-Oct-84 16:01 TEST OF JRST INSTRUCTION AND ARITHMETIC FLAGS SEQ 0114
4829 ;This test verifies that jrst 2,.+1(1) will set the arithmetic flag
4830 ;Specified in ac1. in this case, ac1 specifies the cry1 flag.
4831 ;First, all flags are reset; then ac1 set to specify cry1.
4832 ;Next, jrst 2,.+1(1) is executed to set cry1. cry1 is then checked. if
4833 ;Cry1 is set, this test passes. otherwise, jrst 2,.+1 is faulty.
4834
4835 033207 C6600: SFLAG CRY1 ^;Set cry1 flag
4836
4837 033207 205 01 0 00 100000 MOVSI 1,CRY1
4838 033210 255 17 0 00 033211 JFCL 17,.+1 ;Reset all flags
4839 033211 254 02 0 01 033212 JRST 2,.+1(1) ;Set CRY1 flag
4840 033212 255 02 0 00 033214 JFCL 2,.+2 ;Pass if cry1 was set
4841 STOP^
4842 033213 254 04 0 00 033214 HALT .+1 ;Test failed if program halts here
4843 033214 324 00 0 00 033215 JUMPA .+1 ;To loop change this instruction^
4844
4845 ;**********
4846
4847 ;This test verifies that jrst 2,.+1(1) will set the arithmetic flag
4848 ;Specified in ac1. in this case, ac1 specifies the fov flag.
4849 ;First, all flags are reset; then ac1 set to specify fov.
4850 ;Next, jrst 2,.+1(1) is executed to set fov. fov is then checked. if
4851 ;Fov is set, this test passes. otherwise, jrst 2,.+1 is faulty.
4852
4853 033215 C6700: SFLAG FOV ^;Set fov flag
4854
4855 033215 205 01 0 00 040000 MOVSI 1,FOV
4856 033216 255 17 0 00 033217 JFCL 17,.+1 ;Reset all flags
4857 033217 254 02 0 01 033220 JRST 2,.+1(1) ;Set FOV flag
4858 033220 255 01 0 00 033222 JFCL 1,.+2 ;Pass if fov was set
4859 STOP^
4860 033221 254 04 0 00 033222 HALT .+1 ;Test failed if program halts here
4861 033222 324 00 0 00 033223 JUMPA .+1 ;To loop change this instruction^
4862
4863 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 33
DFKAD1 MAC 1-Oct-84 16:01 TEST OF JRST INSTRUCTION AND ARITHMETIC FLAGS SEQ 0115
4864 ;This test verifies that jfcl 0, should never jump.
4865 ;First, fov is set via jrst2, ;then jfcl 0,
4866 ;Is executed. if jfcl 0, does not skip, this test passes.
4867
4868 033223 C7000: SFLAG FOV ^;Set fov flag
4869
4870 033223 205 01 0 00 040000 MOVSI 1,FOV
4871 033224 255 17 0 00 033225 JFCL 17,.+1 ;Reset all flags
4872 033225 254 02 0 01 033226 JRST 2,.+1(1) ;Set FOV flag
4873 033226 255 00 0 00 033230 JFCL ,.+2 ;*Jfcl should not jump
4874 033227 334 00 0 00 000000 SKIPA ;Pass if jfcl did not jump
4875 STOP^
4876 033230 254 04 0 00 033231 HALT .+1 ;Test failed if program halts here
4877 033231 324 00 0 00 033232 JUMPA .+1 ;To loop change this instruction^
4878
4879 ;**********
4880
4881 ;This test verifies that jrst 2,.+1(1) will set the arithmetic flag
4882 ;Specified in ac1. in this case, ac1 contains 0. hence, jrst 2,.+1(1)
4883 ;Should reset the arithmetic flags. first, the cry0, flag is set by
4884 ;Jrst 2,.+1(1) with c(ac1)=cry0. then, the flags should be cleared by
4885 ;Jrst 2,.+1 with c(ac1)=0. if cry0 was cleared, the test passes.
4886 ;Otherwise, jrst 2,.+1 is faulty.
4887
4888 033232 C7100: SFLAG CRY0 ^;Set cry0 flags
4889
4890 033232 205 01 0 00 200000 MOVSI 1,CRY0
4891 033233 255 17 0 00 033234 JFCL 17,.+1 ;Reset all flags
4892 033234 254 02 0 01 033235 JRST 2,.+1(1) ;Set CRY0 flag
4893 033235 400 01 0 00 000000 SETZ 1, ;Setup mask to clear arithmetic flags
4894 033236 254 02 0 01 033237 JRST 2,.+1(1) ;*Reset arithmetic flags
4895 033237 255 04 0 00 033241 JFCL 4,.+2 ;Pass if cry0 flag was reset
4896 033240 334 00 0 00 000000 SKIPA ;Skip halt instruction if test pssed
4897 STOP^
4898 033241 254 04 0 00 033242 HALT .+1 ;Test failed if program halts here
4899 033242 324 00 0 00 033243 JUMPA .+1 ;To loop change this instruction^
4900
4901 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 34
DFKAD1 MAC 1-Oct-84 16:01 TEST OF JRST INSTRUCTION AND ARITHMETIC FLAGS SEQ 0116
4902 ;This test verifies that jrst 2,.+1(1) will set the arithmetic flag
4903 ;Specified in ac1. in this case, ac1 contains 0. hence, jrst 2,.+1(1)
4904 ;Should reset the arithmetic flags. first, the fov, flag is set by
4905 ;Jrst 2,.+1(1) with c(ac1)=fov. then, the flags should be cleared by
4906 ;Jrst 2,.+1 with c(ac1)=0. if fov was cleared, the test passes.
4907 ;Otherwise, jrst 2,.+1 is faulty.
4908
4909 033243 C7200: SFLAG FOV ^;Set fov flag
4910
4911 033243 205 01 0 00 040000 MOVSI 1,FOV
4912 033244 255 17 0 00 033245 JFCL 17,.+1 ;Reset all flags
4913 033245 254 02 0 01 033246 JRST 2,.+1(1) ;Set FOV flag
4914 033246 400 01 0 00 000000 SETZ 1, ;Setup mask to clear arithmetic flags,
4915 033247 254 02 0 01 033250 JRST 2,.+1(1) ;*Reset arithmetic flags
4916 033250 255 01 0 00 033252 JFCL 1,.+2 ;Pass if fov flag was reset
4917 033251 334 00 0 00 000000 SKIPA ;Skip halt instruction if test pssed
4918 STOP^
4919 033252 254 04 0 00 033253 HALT .+1 ;Test failed if program halts here
4920 033253 324 00 0 00 033254 JUMPA .+1 ;To loop change this instruction^
4921
4922 ;**********
4923
4924 ;This test verifies that jrst 2,.+1(1) will set the arithmetic flag
4925 ;Specified in ac1. in this case, ac1 contains 0. hence, jrst 2,.+1(1)
4926 ;Should reset the arithmetic flags. first, the arithmetic flags are
4927 ;Reset by jfcl 17,.+1. then, the flags should be cleared by jrst 2,.+1.
4928 ;If all the arithmetic flags were cleared, the test passes. otherwise,
4929 ;Jrst 2,.+1 is faulty.
4930
4931 033254 255 17 0 00 033255 C7300: JFCL 17,.+1 ;Clear flags
4932 033255 400 01 0 00 000000 SETZ 1, ;Setup mask to clear aritmetic flags
4933 033256 254 02 0 01 033257 JRST 2,.+1(1) ;*Reset arithmetic flags
4934 033257 255 17 0 00 033261 JFCL 17,.+2 ;Pass if all flags are reset
4935 033260 334 00 0 00 000000 SKIPA ;Skip halt instruction if test passed
4936 STOP^
4937 033261 254 04 0 00 033262 HALT .+1 ;Test failed if program halts here
4938 033262 324 00 0 00 033263 JUMPA .+1 ;To loop change this instruction^
4939
4940 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 35
DFKAD1 MAC 1-Oct-84 16:01 TEST OF JSP INSTRUCTION SEQ 0117
4941 SUBTTL TEST OF JSP INSTRUCTION
4942
4943 ;**********
4944
4945 ;This test verifies that jsp always stores the flags and pc in the ac.
4946 ;In this case, the flags are reset; then, jsp is executed. the ac is then
4947 ;Checked for its contents non-zero. if c(ac)=0, it indicates
4948 ;That neither the flags nor the pc was saved. hence, this test fails.
4949
4950 033263 403 00 0 00 000001 C7400: SETZB 1 ;Clear ac and setup mask to reset flags
4951 033264 254 02 0 01 033265 JRST 2,.+1(1) ;Reset flags
4952 033265 265 00 0 00 033266 JSP .+1 ;*Jsp should store flags and pc in the ac
4953 033266 336 00 0 00 000000 SKIPN ;Pass if c(ac) is non-zero
4954 STOP ^;It did not store any flags or pc
4955
4956 033267 254 04 0 00 033270 HALT .+1 ;Test failed if program halts here
4957 033270 324 00 0 00 033271 JUMPA .+1 ;To loop change this instruction
4958
4959 ;**********
4960
4961 ;This test verifies that jsp always stores the pc in the right half of the ac.
4962 ;In this case, the ac is cleared, then, jsp is executed. the right half of
4963 ;The ac is then checked for its contents non-zero. if c(ac right half)
4964 ;Is non-zero, it indicated that the pc was saved; and this test passes.
4965
4966 033271 400 00 0 00 000000 C7500: SETZ ;Clean ac
4967 033272 265 00 0 00 033273 JSP .+1 ;*Jsp should store the pc in the ac
4968 033273 606 00 0 00 777777 TRNN -1 ;Pass if c(ac) in non-zero
4969 STOP^
4970 033274 254 04 0 00 033275 HALT .+1 ;Test failed if program halts here
4971 033275 324 00 0 00 033276 JUMPA .+1 ;To loop change this instruction^
4972
4973 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 36
DFKAD1 MAC 1-Oct-84 16:01 TEST OF JSP INSTRUCTION SEQ 0118
4974 ;This test verifies that jsp always stores the flags in the left half of the ac.
4975 ;Fist, the ac is cleared; then, some flags are set and jsp is executed.
4976 ;The left half of the ac is checked for its contents non-zero to determine
4977 ;Whether the flags were saved. if c(ac-left) is non-zero, this test passes.
4978
4979 033276 402 00 0 00 000000 C7600: SETZM 0 ;Clear ac
4980 033277 205 01 0 00 740000 MOVSI 1,740000 ;Set up mask to set flags
4981 033300 254 02 0 01 033301 JRST 2,.+1(1) ;Set some arithmetic flags
4982 033301 265 00 0 00 033302 JSP .+1 ;*Jsp should store flags in the ac
4983 033302 607 00 0 00 777777 TLNN -1 ;Pass if c(ac) is non-zero
4984 STOP^
4985 033303 254 04 0 00 033304 HALT .+1 ;Test failed if program halts here
4986 033304 324 00 0 00 033305 JUMPA .+1 ;To loop change this instruction^
4987
4988 ;**********
4989
4990 ;This test verifies that jsp always stores the flags in the left half of the
4991 ;Ac. first, the ac is cleared; then, the arov flag is set and jsp is executed.
4992 ;Then, the arov flag bit of the left half of the ac is checked for its contents
4993 ;Non-zero to determine whether the arov flag was saved. if the arov flag bit
4994 ;Of the ac is set, this test passes.
4995
4996 033305 402 00 0 00 000000 C7700: SETZM 0 ;Clear the ac
4997 SFLAG AROV ^;Set arov flag
4998
4999 033306 205 01 0 00 400000 MOVSI 1,AROV
5000 033307 255 17 0 00 033310 JFCL 17,.+1 ;Reset all flags
5001 033310 254 02 0 01 033311 JRST 2,.+1(1) ;Set AROV flag
5002 033311 265 00 0 00 033312 JSP .+1 ;*Jsp should save the flags in the ac-left
5003 033312 607 00 0 00 400000 TLNN AROV ;Pass if arov was saved
5004 STOP^
5005 033313 254 04 0 00 033314 HALT .+1 ;Test failed if program halts here
5006 033314 324 00 0 00 033315 JUMPA .+1 ;To loop change this instruction^
5007
5008 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 37
DFKAD1 MAC 1-Oct-84 16:01 TEST OF JSP INSTRUCTION SEQ 0119
5009 ;This test verifies that jsp always stores the flags in the left half of the
5010 ;Ac. first, the ac is cleared; then, the cry0 flag is set and jsp is executed.
5011 ;Then, the cry0 flag bit of the left half of the ac is checked for its contents
5012 ;Non-zero to determine whether the cry0 flag was saved. if the cry0 flag bit
5013 ;Of the ac is set, this test passes.
5014
5015 033315 402 00 0 00 000000 C10000: SETZM 0 ;Clear the ac
5016 SFLAG CRY0 ^;Set cry0 flag
5017
5018 033316 205 01 0 00 200000 MOVSI 1,CRY0
5019 033317 255 17 0 00 033320 JFCL 17,.+1 ;Reset all flags
5020 033320 254 02 0 01 033321 JRST 2,.+1(1) ;Set CRY0 flag
5021 033321 265 00 0 00 033322 JSP .+1 ;*Jsp should save the flags in the ac-left
5022 033322 607 00 0 00 200000 TLNN CRY0 ;Pass if cry0 was saved
5023 STOP^
5024 033323 254 04 0 00 033324 HALT .+1 ;Test failed if program halts here
5025 033324 324 00 0 00 033325 JUMPA .+1 ;To loop change this instruction^
5026
5027 ;**********
5028
5029 ;This test verifies that jsp always stores the flags in the left half of the
5030 ;Ac. first, the ac is cleared; then, the cry1 flag is set and jsp is executed.
5031 ;Then, the cry1 flag bit of the left half of the ac is checked for its contents
5032 ;Non-zero to determine whether the flag was saved. if the cry1 flag bit of the
5033 ;Ac is set, this test passes.
5034
5035 033325 400 00 0 00 000000 C10100: SETZ ;Clear ac
5036 SFLAG CRY1 ^;Set cry1 flag
5037
5038 033326 205 01 0 00 100000 MOVSI 1,CRY1
5039 033327 255 17 0 00 033330 JFCL 17,.+1 ;Reset all flags
5040 033330 254 02 0 01 033331 JRST 2,.+1(1) ;Set CRY1 flag
5041 033331 265 00 0 00 033332 JSP .+1 ;*Jsp should save the flags in the ac-left
5042 033332 607 00 0 00 100000 TLNN CRY1 ;Pass if arov was saved
5043 STOP^
5044 033333 254 04 0 00 033334 HALT .+1 ;Test failed if program halts here
5045 033334 324 00 0 00 033335 JUMPA .+1 ;To loop change this instruction^
5046
5047 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 38
DFKAD1 MAC 1-Oct-84 16:01 TEST OF JSP INSTRUCTION SEQ 0120
5048 ;This test verifies that jsp always stores the flags in the left half of the
5049 ;Ac. first, the ac is cleared; then, the fov flag is set and jsp is executed.
5050 ;Then, the fov flag bit of the left half of the ac is checked for its contents
5051 ;Non-zero to determine whether the fov flag was saved. if the fov flag bit of
5052 ;The ac is set, this test passes.
5053
5054 033335 400 00 0 00 000000 C10200: SETZ ;Clear the ac
5055 SFLAG FOV ^;Set fov flag
5056
5057 033336 205 01 0 00 040000 MOVSI 1,FOV
5058 033337 255 17 0 00 033340 JFCL 17,.+1 ;Reset all flags
5059 033340 254 02 0 01 033341 JRST 2,.+1(1) ;Set FOV flag
5060 033341 265 00 0 00 033342 JSP .+1 ;*Jsp should save the flags in the ac-left
5061 033342 607 00 0 00 040000 TLNN FOV ;Pass if fov was saved
5062 STOP^
5063 033343 254 04 0 00 033344 HALT .+1 ;Test failed if program halts here
5064 033344 324 00 0 00 033345 JUMPA .+1 ;To loop change this instruction^
5065
5066 ;**********
5067
5068 ;This test verifies that jsp will store only flags that exist. i.e. reset
5069 ;Flags will not be set in the ac. only flags that are clearable by jrstf
5070 ;Will be checked here. first all clearable flags are reset by jrstf. then
5071 ;Jsp is executed. the ac is then checked. if any clearable flags are set
5072 ;In the ac, this test fails.
5073
5074 033345 C10300: SFLAG 0 ^;Clear all clearable flags
5075
5076 033345 205 01 0 00 000000 MOVSI 1,0
5077 033346 255 17 0 00 033347 JFCL 17,.+1 ;Reset all flags
5078 033347 254 02 0 01 033350 JRST 2,.+1(1) ;Set 0 flag
5079 033350 265 00 0 00 033351 JSP .+1 ;*Jsp should not store clearable falgs
5080 033351 603 00 0 00 761777 TLNE 761777 ;Fail if any clearable flag is set
5081 STOP^
5082 033352 254 04 0 00 033353 HALT .+1 ;Test failed if program halts here
5083 033353 324 00 0 00 033354 JUMPA .+1 ;To loop change this instruction^
5084
5085 ;**********
5086
5087 ;This test verifies that jsp always jumps.
5088 ;In this test, jsp .+2 is executed. if jsp jumps, the
5089 ;Test passes. otherwise, this test halts.
5090
5091 033354 265 00 0 00 033356 C10400: JSP .+2 ;*Jsp should always jump
5092 STOP^
5093 033355 254 04 0 00 033356 HALT .+1 ;Test failed if program halts here
5094 033356 324 00 0 00 033357 JUMPA .+1 ;To loop change this instruction^
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 39
DFKAD1 MAC 1-Oct-84 16:01 TEST JRST INSTRUCTION SEQ 0121
5095 SUBTTL TEST JRST INSTRUCTION
5096
5097 ;**********
5098
5099 ;This test verifies that jrst always jumps.
5100 ;In this test, jrst .+2 is executed. if jrst jumps, the test passes;
5101 ;Otherwise, this test halts.
5102
5103 033357 254 00 0 00 033361 C10500: JRST .+2 ;*Jrst 0, should always jump
5104 STOP^
5105 033360 254 04 0 00 033361 HALT .+1 ;Test failed if program halts here
5106 033361 324 00 0 00 033362 JUMPA .+1 ;To loop change this instruction^
5107
5108 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 40
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AOBJX INSTRUCTIONS SEQ 0122
5109 SUBTTL TEST OF AOBJX INSTRUCTIONS
5110
5111 ;**********
5112
5113 ;This test verifies that aobjn always adds 1 to both halves of the ac.
5114 ;First, the ac is cleared; then, aobjn is executed and the ac is checked
5115 ;For 1,,1. if c(ac)=1,,1, this test passes.
5116
5117 033362 400 00 0 00 000000 C11200: SETZ ;Clear the ac
5118 033363 253 00 0 00 033364 AOBJN .+1 ;*Aobjn should add 1 to both halves of the ac
5119 033364 312 00 0 00 034417 CAME [XWD 1,1] ;Pass if c(ac)=1,,1
5120 STOP^
5121 033365 254 04 0 00 033366 HALT .+1 ;Test failed if program halts here
5122 033366 324 00 0 00 033367 JUMPA .+1 ;To loop change this instruction^
5123
5124 ;**********
5125
5126 ;This test verifies that aobjp always adds 1 to both halves of the ac.
5127 ;First, the ac is cleared; then aobjp is executed and the ac is checked
5128 ;For 1,,1. if c(ac)=1,,1, this test passes.
5129
5130 033367 200 00 0 00 034515 C11300: MOVE [XWD 377777,377777] ;Preload ac with 377777,,377777
5131 033370 252 00 0 00 033371 AOBJP .+1 ;*Aobjp should add, to both halves of the ac
5132 033371 312 00 0 00 034516 CAME [XWD 400000,400000] ;Pass if c(ac)=400000,400000
5133 STOP^
5134 033372 254 04 0 00 033373 HALT .+1 ;Test failed if program halts here
5135 033373 324 00 0 00 033374 JUMPA .+1 ;To loop change this instruction^
5136
5137 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 41
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AOBJX INSTRUCTIONS SEQ 0123
5138 ;This test verifies that aobjn will not jump when c(ac) is positive
5139 ;First, the ac is cleared; and aobjn is executed. aobjn should not jump
5140 ;Because c(ac) is positive. if aobjn jumps, this test fails.
5141
5142 033374 400 00 0 00 000000 C11400: SETZ ;Clear the ac
5143 033375 253 00 0 00 033377 AOBJN .+2 ;*Aobjn should not jump when c(ac) is positive
5144 033376 334 00 0 00 000000 SKIPA ;Pass if aobjn does not jump
5145 STOP^
5146 033377 254 04 0 00 033400 HALT .+1 ;Test failed if program halts here
5147 033400 324 00 0 00 033401 JUMPA .+1 ;To loop change this instruction^
5148
5149 ;**********
5150
5151 ;This test verifies that aobjp will jump when c(ac) is positive
5152 ;First, the ac is cleared; and aobjp is executed. aobjp should jump
5153 ;Because c(ac) is positive. if aobjp does not jump, this test fails.
5154
5155 033401 400 00 0 00 000000 C11500: SETZ ;Clear the ac
5156 033402 252 00 0 00 033404 AOBJP .+2 ;*Aobjp should jump because c(ac) is positive
5157 STOP^
5158 033403 254 04 0 00 033404 HALT .+1 ;Test failed if program halts here
5159 033404 324 00 0 00 033405 JUMPA .+1 ;To loop change this instruction^
5160
5161 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 42
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AOBJX INSTRUCTIONS SEQ 0124
5162 ;This test verifies that aobjn will jump when c(ac) is negative. first,
5163 ;The ac is preloaded with 400000,,0; and aobjn is executed. aobjn should
5164 ;Jump because c(ac) is negative. if aobjn does not jump, this test fails.
5165
5166 033405 200 00 0 00 034516 C11600: MOVE [XWD 400000,400000] ;Preload ac with 400000,,400000
5167 033406 253 00 0 00 033410 AOBJN .+2 ;*Aobjn should jump because c(ac) is negative
5168 STOP^
5169 033407 254 04 0 00 033410 HALT .+1 ;Test failed if program halts here
5170 033410 324 00 0 00 033411 JUMPA .+1 ;To loop change this instruction^
5171
5172 ;**********
5173
5174 ;This test verifies that aobjp will not jump when c(ac) is negative. first,
5175 ;The ac is preloaded with 400000,,0; and aobjp is executed. aobjp should not
5176 ;Jump because c(ac) is negative. if aobjp jumps, this test fails.
5177
5178 033411 200 00 0 00 034516 C11700: MOVE [XWD 400000,400000] ;Preload ac with 400000,,400000
5179 033412 252 00 0 00 033414 AOBJP .+2 ;*Aobjp should not jump because c(ac) is negative
5180 033413 334 00 0 00 000000 SKIPA ;Pass if aobjp does not jump
5181 STOP^
5182 033414 254 04 0 00 033415 HALT .+1 ;Test failed if program halts here
5183 033415 324 00 0 00 033416 JUMPA .+1 ;To loop change this instruction^
5184
5185 ;**********
5186
5187 ;This test verifies that there is no carry from bit 18 to bit 17 of the ac
5188 ;On aobjn. the ac is preloaded with -1,,-1; then aobjn is executed. aobjn
5189 ;Should add one to both halves of the ac without generating a carry from
5190 ;Bit 18 to bit 17. if no carry was generated, this test passes.
5191
5192 033416 474 00 0 00 000000 C12000: SETO ;Preload ac with -1,, -1
5193 033417 253 00 0 00 033420 AOBJN .+1 ;*Aobjn should not cause a carry from bit 18 to 17
5194 033420 332 00 0 00 000000 SKIPE ;Pass if c(ac)=0 (no carry was generated)
5195 STOP^
5196 033421 254 04 0 00 033422 HALT .+1 ;Test failed if program halts here
5197 033422 324 00 0 00 033423 JUMPA .+1 ;To loop change this instruction^
5198
5199 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 43
DFKAD1 MAC 1-Oct-84 16:01 TEST SETTING OF ARITHMETIC FLAGS VIA MOVNX AND MOVMX SEQ 0125
5200 SUBTTL TEST SETTING OF ARITHMETIC FLAGS VIA MOVNX AND MOVMX
5201
5202 ;This test verifies that movni sets cry0 and cry1 flags only when the data
5203 ;Is 0. first, the arithmetic flags are reset; then, movni is executed with
5204 ;Data of zeros. the arithmetic flags are checked. cry0/1 are set and arov
5205 ;And fov reset, this test passes.
5206
5207 033423 255 17 0 00 033424 C12100: JFCL 17,.+1 ;Clear flags
5208 033424 211 00 0 00 000000 MOVNI 0 ;* Movni 0 should set cry0/1
5209 033425 255 04 0 00 033427 JCRY0 .+2 ;Pass if cry0 is set
5210 STOP^
5211 033426 254 04 0 00 033427 HALT .+1 ;Test failed if program halts here
5212 033427 324 00 0 00 033430 JUMPA .+1 ;To loop change this instruction^
5213 033430 255 02 0 00 033432 JCRY1 .+2 ;Pass if cry1 is set
5214 STOP^
5215 033431 254 04 0 00 033432 HALT .+1 ;Test failed if program halts here
5216 033432 324 00 0 00 033433 JUMPA .+1 ;To loop change this instruction^
5217 033433 255 10 0 00 033435 JOV .+2 ;Pass if arov reset
5218 033434 334 00 0 00 000000 SKIPA
5219 STOP^
5220 033435 254 04 0 00 033436 HALT .+1 ;Test failed if program halts here
5221 033436 324 00 0 00 033437 JUMPA .+1 ;To loop change this instruction^
5222 033437 255 01 0 00 033441 JFOV .+2 ;Pass if fov reset
5223 033440 334 00 0 00 000000 SKIPA
5224 STOP^
5225 033441 254 04 0 00 033442 HALT .+1 ;Test failed if program halts here
5226 033442 324 00 0 00 033443 JUMPA .+1 ;To loop change this instruction^
5227
5228 ;**********
5229
5230 ;This test verifies that movn will not set arithmetic flags when the data
5231 ;Is -1,,-1. first, the flags are reset; then, movn [-1,,-1] is executed.
5232 ;The arithmetic flags are checked. if any arithmetic flag is set, this
5233 ;Test fails.
5234
5235 033443 255 17 0 00 033444 C12200: JFCL 17,.+1 ;Clear flags
5236 033444 210 00 0 00 034443 MOVN [-1] ;*Movn [-1,,-1] should set arithmetic flags
5237 033445 255 17 0 00 033447 JFCL 17,.+2 ;Fail if an arithmetic flag is set
5238 033446 334 00 0 00 000000 SKIPA ;Skip halt instruction if movn passed.
5239 STOP^
5240 033447 254 04 0 00 033450 HALT .+1 ;Test failed if program halts here
5241 033450 324 00 0 00 033451 JUMPA .+1 ;To loop change this instruction^
5242
5243 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 44
DFKAD1 MAC 1-Oct-84 16:01 TEST SETTING OF ARITHMETIC FLAGS VIA MOVNX AND MOVMX SEQ 0126
5244 ;This test verifies that movn will set the arov and
5245 ;Cry1 flags only when the data is 400000,,0
5246 ;First, the flags are reset; then, movn [400000,,0] is executed.
5247 ;The arithmetic flags are checked.
5248 ;If arov and cry1 are set and cry0 and fov are reset, this test passes.
5249
5250 033451 255 17 0 00 033452 C12300: JFCL 17,.+1 ;Clear arithmetic flags
5251 033452 210 00 0 00 034442 MOVN [XWD 400000,0] ;*Movn [400000,,0] should set arov and cry1 only
5252 033453 255 10 0 00 033455 JOV .+2 ;Pass if arov is set
5253 STOP^
5254 033454 254 04 0 00 033455 HALT .+1 ;Test failed if program halts here
5255 033455 324 00 0 00 033456 JUMPA .+1 ;To loop change this instruction^
5256 033456 255 02 0 00 033460 JCRY1 .+2 ;Pass if cry0 is set
5257 STOP^
5258 033457 254 04 0 00 033460 HALT .+1 ;Test failed if program halts here
5259 033460 324 00 0 00 033461 JUMPA .+1 ;To loop change this instruction^
5260 033461 255 04 0 00 033463 JCRY0 .+2 ;Pass if cry0 is reset
5261 033462 334 00 0 00 000000 SKIPA
5262 STOP^
5263 033463 254 04 0 00 033464 HALT .+1 ;Test failed if program halts here
5264 033464 324 00 0 00 033465 JUMPA .+1 ;To loop change this instruction^
5265 033465 255 01 0 00 033467 JFOV .+2 ;Pass if fov is reset
5266 033466 334 00 0 00 000000 SKIPA
5267 STOP^
5268 033467 254 04 0 00 033470 HALT .+1 ;Test failed if program halts here
5269 033470 324 00 0 00 033471 JUMPA .+1 ;To loop change this instruction^
5270
5271 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 45
DFKAD1 MAC 1-Oct-84 16:01 TEST SETTING OF ARITHMETIC FLAGS VIA MOVNX AND MOVMX SEQ 0127
5272 ;This test verifies that movm will set the arov and
5273 ;Cry1 flags only when the data is 400000,,0
5274 ;First, the flags are reset; then, movm [400000,,0] is executed.
5275 ;The arithmetic flags are checked.
5276 ;If arov and cry1 are set and cry0 and fov are reset, this test passes.
5277
5278 033471 255 17 0 00 033472 C12301: JFCL 17,.+1 ;Clear arithmetic flags
5279 033472 214 00 0 00 034442 MOVM [XWD 400000,0] ;*Movm [400000,,0] should set arov and cry1 only
5280 033473 255 10 0 00 033475 JOV .+2 ;Pass if arov is set
5281 STOP^
5282 033474 254 04 0 00 033475 HALT .+1 ;Test failed if program halts here
5283 033475 324 00 0 00 033476 JUMPA .+1 ;To loop change this instruction^
5284 033476 255 02 0 00 033500 JCRY1 .+2 ;Pass if cry0 is set
5285 STOP^
5286 033477 254 04 0 00 033500 HALT .+1 ;Test failed if program halts here
5287 033500 324 00 0 00 033501 JUMPA .+1 ;To loop change this instruction^
5288 033501 255 04 0 00 033503 JCRY0 .+2 ;Pass if cry0 is reset
5289 033502 334 00 0 00 000000 SKIPA
5290 STOP^
5291 033503 254 04 0 00 033504 HALT .+1 ;Test failed if program halts here
5292 033504 324 00 0 00 033505 JUMPA .+1 ;To loop change this instruction^
5293 033505 255 01 0 00 033507 JFOV .+2 ;Pass if fov is reset
5294 033506 334 00 0 00 000000 SKIPA
5295 STOP^
5296 033507 254 04 0 00 033510 HALT .+1 ;Test failed if program halts here
5297 033510 324 00 0 00 033511 JUMPA .+1 ;To loop change this instruction^
5298
5299 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 46
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AOS AND SOS INSTRUCTIONS SEQ 0128
5300 SUBTTL TEST OF AOS AND SOS INSTRUCTIONS
5301
5302 ;**********
5303
5304 ;This test verifies that aos adds 1 to memory and does not skip.
5305 ;First, e is cleared; then, aos is executed. next e is checked for 1.
5306 ;If c(e) is not 1 or aos skipped, this test fails.
5307
5308 033511 400 00 0 00 000000 C12600: SETZ ;Clear e
5309 033512 350 00 0 00 000000 AOS ;*Aos should add 1 to c(e) and not skip
5310 033513 302 00 0 00 000001 CAIE 1 ;Pass if c(e)=0,,1 andaos did not skip
5311 STOP^
5312 033514 254 04 0 00 033515 HALT .+1 ;Test failed if program halts here
5313 033515 324 00 0 00 033516 JUMPA .+1 ;To loop change this instruction^
5314
5315 ;**********
5316
5317 ;This test verifies that aos adds 1 to memory and does not skip. first,
5318 ;E is preloaded with -1,,-1; then, aos is executed. next e is checked for 0.
5319 ;If c(e) is not 0 or aos skipped, this test fails.
5320
5321 033516 474 00 0 00 000000 C12700: SETO ;Preload e with -1,,-1
5322 033517 350 00 0 00 000000 AOS ;*Aos should add 1 to c(e) and not skip
5323 033520 302 00 0 00 000000 CAIE ;Pass if c(e)=0,,0 and aos did not skip
5324 STOP^
5325 033521 254 04 0 00 033522 HALT .+1 ;Test failed if program halts here
5326 033522 324 00 0 00 033523 JUMPA .+1 ;To loop change this instruction^
5327
5328 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 47
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AOS AND SOS INSTRUCTIONS SEQ 0129
5329 ;This test verifies that sos subtracts 1 from memory and does not skip.
5330 ;First, e is cleared; then, sos is executed. next e is checked for -1,,-1.
5331 ;If c(e) is not -1,,-1 or sos skipped, this test fails.
5332
5333 033523 400 00 0 00 000000 C13100: SETZ ;Clear e
5334 033524 370 00 0 00 000000 SOS ;*Sos should subtract 1 from c(e) and not skip
5335 033525 312 00 0 00 034443 CAME [-1] ;Pass if c(e)=-1,,-1 and sos did not skip
5336 STOP^
5337 033526 254 04 0 00 033527 HALT .+1 ;Test failed if program halts here
5338 033527 324 00 0 00 033530 JUMPA .+1 ;To loop change this instruction^
5339
5340 ;**********
5341
5342 ;This test verifies that sos subtracts 1 from memory and does not skip.
5343 ;First, e is preloaded with a; then, sos is executed. next e is checked for 0.
5344 ;If c(e) is not 0 or sos skipped, this test fails.
5345
5346 033530 201 00 0 00 000001 C13200: MOVEI 1 ;Preload e with 1
5347 033531 370 00 0 00 000000 SOS ;*Sos should subtract 1 from c(e) and did not skip
5348 033532 302 00 0 00 000000 CAIE 0 ;Pass if c(e)=0 and sos did not skip
5349 STOP^
5350 033533 254 04 0 00 033534 HALT .+1 ;Test failed if program halts here
5351 033534 324 00 0 00 033535 JUMPA .+1 ;To loop change this instruction^
5352
5353 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 48
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AOS AND SOS INSTRUCTIONS SEQ 0130
5354 ;This test verifies that sos sets cry0/1 flags if c(e) is a non-zero number
5355 ;Other than 400000,,0. in this case, c(e)=1. first the flags are reset; then
5356 ;Sos is executed. the flags are checked. if cry0 and cry1 are set and arov
5357 ;And fov are reset, this test passes.
5358
5359 033535 255 17 0 00 033536 C13300: JFCL 17,.+1 ;Reset arithmetic flags
5360 033536 201 00 0 00 000001 MOVEI 1 ;Preload e with 1
5361 033537 370 00 0 00 000000 SOS ;*Sos should set cry0/1
5362 033540 255 04 0 00 033542 JCRY0 .+2 ;Pass if cry0 is set
5363 STOP^
5364 033541 254 04 0 00 033542 HALT .+1 ;Test failed if program halts here
5365 033542 324 00 0 00 033543 JUMPA .+1 ;To loop change this instruction^
5366 033543 255 02 0 00 033545 JCRY1 .+2 ;Pass if cry1 is set
5367 STOP^
5368 033544 254 04 0 00 033545 HALT .+1 ;Test failed if program halts here
5369 033545 324 00 0 00 033546 JUMPA .+1 ;To loop change this instruction^
5370 033546 255 10 0 00 033550 JOV .+2 ;Pass if arov is reset
5371 033547 334 00 0 00 000000 SKIPA
5372 STOP^
5373 033550 254 04 0 00 033551 HALT .+1 ;Test failed if program halts here
5374 033551 324 00 0 00 033552 JUMPA .+1 ;To loop change this instruction^
5375 033552 255 01 0 00 033554 JFOV .+2 ;Pass if fov is reset
5376 033553 334 00 0 00 000000 SKIPA
5377 STOP^
5378 033554 254 04 0 00 033555 HALT .+1 ;Test failed if program halts here
5379 033555 324 00 0 00 033556 JUMPA .+1 ;To loop change this instruction^
5380
5381 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 49
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AOS AND SOS INSTRUCTIONS SEQ 0131
5382 ;This test verifies that aos sets cry0 and cry1 flag if c(e) is -1,,-1
5383 ;First the flags are reset; then aos is executed. the flags are checked.
5384 ;If cry0 and cry1 are set and arov and fov are reset, this test passes.
5385
5386 033556 255 17 0 00 033557 C13400: JFCL 17,.+1 ;Reset arithmetic flags
5387 033557 474 00 0 00 000000 SETO ;Preload e with 1
5388 033560 350 00 0 00 000000 AOS ;*Aos should set cry0 and cry1
5389 033561 255 04 0 00 033563 JCRY0 .+2 ;Pass if cry0 is set
5390 STOP^
5391 033562 254 04 0 00 033563 HALT .+1 ;Test failed if program halts here
5392 033563 324 00 0 00 033564 JUMPA .+1 ;To loop change this instruction^
5393 033564 255 02 0 00 033566 JCRY1 .+2 ;Pass if cry1 is set
5394 STOP^
5395 033565 254 04 0 00 033566 HALT .+1 ;Test failed if program halts here
5396 033566 324 00 0 00 033567 JUMPA .+1 ;To loop change this instruction^
5397 033567 255 10 0 00 033571 JOV .+2 ;Pass if arov is reset
5398 033570 334 00 0 00 000000 SKIPA
5399 STOP^
5400 033571 254 04 0 00 033572 HALT .+1 ;Test failed if program halts here
5401 033572 324 00 0 00 033573 JUMPA .+1 ;To loop change this instruction^
5402 033573 255 01 0 00 033575 JFOV .+2 ;Pass if fov is reset
5403 033574 334 00 0 00 000000 SKIPA
5404 STOP^
5405 033575 254 04 0 00 033576 HALT .+1 ;Test failed if program halts here
5406 033576 324 00 0 00 033577 JUMPA .+1 ;To loop change this instruction^
5407
5408 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 50
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INTERACTION OF JFCL, JRST, AND JSP WITH ARITHMETIC FLAGS SEQ 0132
5409 SUBTTL TEST OF INTERACTION OF JFCL, JRST, AND JSP WITH ARITHMETIC FLAGS
5410
5411 ;**********
5412
5413 ;This test verifies that jfcl 1, will always clear fov flag.
5414 ;First, fov is set via jrst 2, ;then jfcl 1,.+1 is executed to clear fov.
5415 ;If fov was cleared, this test passes.
5416
5417 033577 C13600: SFLAG FOV ^;Set fov flag
5418
5419 033577 205 01 0 00 040000 MOVSI 1,FOV
5420 033600 255 17 0 00 033601 JFCL 17,.+1 ;Reset all flags
5421 033601 254 02 0 01 033602 JRST 2,.+1(1) ;Set FOV flag
5422 033602 255 01 0 00 033603 JFCL 1,.+1 ;*Jfcl should reset fov
5423 033603 255 01 0 00 033605 JFCL 1,.+2 ;Pass if fov is reset
5424 033604 334 00 0 00 000000 SKIPA ;Skip halt if jfcl 1,.+1 passed
5425 STOP^
5426 033605 254 04 0 00 033606 HALT .+1 ;Test failed if program halts here
5427 033606 324 00 0 00 033607 JUMPA .+1 ;To loop change this instruction^
5428
5429 ;**********
5430
5431 ;This test verifies that jrst 2, can set fxu and jsp can save fxu in the ac.
5432 ;First, fxu is set via jrst 2, ;then, jsp is executed. the ac is checked for
5433 ;Fxu. if fxu is set, this test passes; otherwise, either jrst 2, or jsp failed.
5434
5435 033607 C13700: SFLAG FXU ^;*Set fxu flag
5436
5437 033607 205 01 0 00 000100 MOVSI 1,FXU
5438 033610 255 17 0 00 033611 JFCL 17,.+1 ;Reset all flags
5439 033611 254 02 0 01 033612 JRST 2,.+1(1) ;Set FXU flag
5440 033612 265 00 0 00 033613 JSP .+1 ;*Store fxu flag in ac
5441 033613 607 00 0 00 000100 TLNN FXU ;Pass if fxu is set in the ac
5442 STOP^
5443 033614 254 04 0 00 033615 HALT .+1 ;Test failed if program halts here
5444 033615 324 00 0 00 033616 JUMPA .+1 ;To loop change this instruction^
5445
5446 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 51
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INTERACTION OF JFCL, JRST, AND JSP WITH ARITHMETIC FLAGS SEQ 0133
5447 ;This test verifies that jrst 2, can reset fxu and jsp can save fxu in the ac.
5448 ;First, fxu is set; then, fxu is reset via jrst 2,. next, jsp is executed; and
5449 ;The ac is checked for fxu reset. if fxu is reset in the ac, this test passes;
5450 ;Otherwise, jrst 2, failed to clear fxu or jsp stored fxu incorectly.
5451
5452 033616 C14000: SFLAG FXU ^;Set fxu flag
5453
5454 033616 205 01 0 00 000100 MOVSI 1,FXU
5455 033617 255 17 0 00 033620 JFCL 17,.+1 ;Reset all flags
5456 033620 254 02 0 01 033621 JRST 2,.+1(1) ;Set FXU flag
5457 SFLAG ^;*Reset fxu flag
5458
5459 033621 205 01 0 00 000000 MOVSI 1,
5460 033622 255 17 0 00 033623 JFCL 17,.+1 ;Reset all flags
5461 033623 254 02 0 01 033624 JRST 2,.+1(1) ;Set flag
5462 033624 265 00 0 00 033625 JSP .+1 ;*Store fxu flag in the ac
5463 033625 603 00 0 00 000100 TLNE FXU ;Pass if fxu is reset in the ac
5464 STOP^
5465 033626 254 04 0 00 033627 HALT .+1 ;Test failed if program halts here
5466 033627 324 00 0 00 033630 JUMPA .+1 ;To loop change this instruction^
5467
5468 ;**********
5469
5470 ;This test verifies that jrst 2, can set dck and jsp can save dck in the ac.
5471 ;First, dck is set via jrst 2, ;then jsp is executed. the ac is checked
5472 ;For dck. if dck is set, this test passes, otherwise jrst 2, or jsp failed.
5473
5474 033630 C14100: SFLAG DCK ^;*Set dck flag
5475
5476 033630 205 01 0 00 000040 MOVSI 1,DCK
5477 033631 255 17 0 00 033632 JFCL 17,.+1 ;Reset all flags
5478 033632 254 02 0 01 033633 JRST 2,.+1(1) ;Set DCK flag
5479 033633 265 00 0 00 033634 JSP .+1 ;*Store fxu flag in ac
5480 033634 607 00 0 00 000040 TLNN DCK ;Pass if fxu is set in the ac
5481 STOP^
5482 033635 254 04 0 00 033636 HALT .+1 ;Test failed if program halts here
5483 033636 324 00 0 00 033637 JUMPA .+1 ;To loop change this instruction^
5484
5485 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 52
DFKAD1 MAC 1-Oct-84 16:01 TEST OF INTERACTION OF JFCL, JRST, AND JSP WITH ARITHMETIC FLAGS SEQ 0134
5486 ;This test verifies that jrst 2, can reset dck and jsp can save dck in the ac.
5487 ;First, fxu is set; then, dck is reset via jrst 2,. next, jsp is expected; and
5488 ;The ac is checked for dck reset. if dck is reset in the ac, this test passes;
5489 ;Otherwise, jrst 2, failed to clear dck or jsp stored dck incorrectly.
5490
5491 033637 C14200: SFLAG DCK ^;Set dck flag
5492
5493 033637 205 01 0 00 000040 MOVSI 1,DCK
5494 033640 255 17 0 00 033641 JFCL 17,.+1 ;Reset all flags
5495 033641 254 02 0 01 033642 JRST 2,.+1(1) ;Set DCK flag
5496 SFLAG ^;*Reset dck flag
5497
5498 033642 205 01 0 00 000000 MOVSI 1,
5499 033643 255 17 0 00 033644 JFCL 17,.+1 ;Reset all flags
5500 033644 254 02 0 01 033645 JRST 2,.+1(1) ;Set flag
5501 033645 265 00 0 00 033646 JSP .+1 ;*Store dck flag in the ac
5502 033646 603 00 0 00 000040 TLNE DCK ;Pass if dck is reset in the ac
5503 STOP^
5504 033647 254 04 0 00 033650 HALT .+1 ;Test failed if program halts here
5505 033650 324 00 0 00 033651 JUMPA .+1 ;To loop change this instruction^
5506
5507 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 53
DFKAD1 MAC 1-Oct-84 16:01 TEST OF JUMPX INSTRUCTIONS SEQ 0135
5508 SUBTTL TEST OF JUMPX INSTRUCTIONS
5509
5510 ;**********
5511
5512 ;This test verifies that jumpl is data dependent. it will jump if and only
5513 ;If c(ac) is negative. in this test, the ac contains -1,,-1. hence, jumpl
5514 ;Should jump. if jumpl jumps, this test passes.
5515
5516 033651 474 00 0 00 000000 C14500: SETO ;Preload ac with -1,,-1
5517 033652 321 00 0 00 033654 JUMPL .+2 ;*Jumpl should jump because c(ac) is negative
5518 STOP^
5519 033653 254 04 0 00 033654 HALT .+1 ;Test failed if program halts here
5520 033654 324 00 0 00 033655 JUMPA .+1 ;To loop change this instruction^
5521
5522 ;**********
5523
5524 ;This test verifies that jumpl is data dependent. it will jump if and only
5525 ;If c(ac) is negative. in this test, the ac contains 0. hence, jumpl
5526 ;Should not jump. if jumpl does not jump, this test passes.
5527
5528 033655 400 00 0 00 000000 C14600: SETZ ;Preload ac with 0
5529 033656 321 00 0 00 033660 JUMPL .+2 ;*Jumpl should not jump
5530 033657 334 00 0 00 000000 SKIPA ;Pass if jumpl does not jump
5531 STOP^
5532 033660 254 04 0 00 033661 HALT .+1 ;Test failed if program halts here
5533 033661 324 00 0 00 033662 JUMPA .+1 ;To loop change this instruction^
5534
5535 ;**********
5536
5537 ;This test verifies that jumpe is data dependent. it will jump if and
5538 ;Only if c(ac)=0. in this test, the ac contains 0. hence, jumpe should
5539 ;Jump. if jumpe jumps, this test passes.
5540
5541 033662 400 00 0 00 000000 C14700: SETZ ;Preload ac with 0
5542 033663 322 00 0 00 033665 JUMPE .+2 ;*Jumpe should jump
5543 STOP^
5544 033664 254 04 0 00 033665 HALT .+1 ;Test failed if program halts here
5545 033665 324 00 0 00 033666 JUMPA .+1 ;To loop change this instruction^
5546
5547 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 54
DFKAD1 MAC 1-Oct-84 16:01 TEST OF JUMPX INSTRUCTIONS SEQ 0136
5548 ;This test verifies that jumpn is data dependent. it will jump if and
5549 ;Only if c(ac) is non-zero. in this test, the ac contains 1. hence,
5550 ;Jumpn should jump. if jumpn jumps, this test passes.
5551
5552 033666 201 00 0 00 000001 C15000: MOVEI 1 ;Preload ac with 1
5553 033667 326 00 0 00 033671 JUMPN .+2 ;*Jumpn should jump
5554 STOP^
5555 033670 254 04 0 00 033671 HALT .+1 ;Test failed if program halts here
5556 033671 324 00 0 00 033672 JUMPA .+1 ;To loop change this instruction^
5557
5558 ;**********
5559
5560 ;This test verifies that jumpe is data dependent. it will jump if and
5561 ;Only if c(ac)=0. in this test, the ac contains 2. hence, jumpl should
5562 ;Not jump. if jumpe does not jump, this test passes.
5563
5564 033672 201 00 0 00 000002 C15100: MOVEI 2 ;Preload ac with 2
5565 033673 322 00 0 00 033675 JUMPE .+2 ;*Jumpe should not jump
5566 033674 334 00 0 00 000000 SKIPA ;Pass if jumpe did not jump
5567 STOP^
5568 033675 254 04 0 00 033676 HALT .+1 ;Test failed if program halts here
5569 033676 324 00 0 00 033677 JUMPA .+1 ;To loop change this instruction^
5570
5571 ;**********
5572
5573 ;This test verifies that jumpn is data dependent. it will jump if and
5574 ;Only if c(ac) is non-zero. in this test, the ac contains 0. hence,
5575 ;Jumpn should not jump. if jumpn does not jump, this test passes.
5576
5577 033677 400 00 0 00 000000 C15200: SETZ ;Preload ac with 0
5578 033700 326 00 0 00 033702 JUMPN .+2 ;*Jumpn should not jump
5579 033701 334 00 0 00 000000 SKIPA ;Pass if jumpn did not jump
5580 STOP^
5581 033702 254 04 0 00 033703 HALT .+1 ;Test failed if program halts here
5582 033703 324 00 0 00 033704 JUMPA .+1 ;To loop change this instruction^
5583
5584 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 55
DFKAD1 MAC 1-Oct-84 16:01 TEST OF JUMPX INSTRUCTIONS SEQ 0137
5585 ;This test verifies that jumpg is data dependent. it will jump if and
5586 ;Only if c(ac) is greater than 0. in this test, the ac contains 1. hence,
5587 ;Jumpg should jump. if jumpg jumps, this test passes.
5588
5589 033704 201 00 0 00 000001 C15300: MOVEI 1 ;Preload ac with 1
5590 033705 327 00 0 00 033707 JUMPG .+2 ;*Jumpg should jump
5591 STOP^
5592 033706 254 04 0 00 033707 HALT .+1 ;Test failed if program halts here
5593 033707 324 00 0 00 033710 JUMPA .+1 ;To loop change this instruction^
5594
5595 ;**********
5596
5597 ;This test verifies that jumpg is data dependent. it will jump if and only
5598 ;If c(ac) is greater than 0. in this test, the ac contains -1,,0. hence,
5599 ;Jumpg should not jump. if jumpg does not jump, this test passes.
5600
5601 033710 205 00 0 00 777777 C15400: MOVSI -1 ;Preload ac with -1,,0
5602 033711 327 00 0 00 033713 JUMPG .+2 ;*Jumpg should not jump
5603 033712 334 00 0 00 000000 SKIPA ;Pass if jumpg did not jump
5604 STOP^
5605 033713 254 04 0 00 033714 HALT .+1 ;Test failed if program halts here
5606 033714 324 00 0 00 033715 JUMPA .+1 ;To loop change this instruction^
5607
5608 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 56
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AOJ AND SOJ INSTRUCTIONS SEQ 0138
5609 SUBTTL TEST OF AOJ AND SOJ INSTRUCTIONS
5610
5611 ;**********
5612
5613 ;This test verifies that aoj adds 1 to the ac and does not jump.
5614 ;First, the ac is preloaded with 0; then, aoj is executed. next, the
5615 ;Ac is checked for 1. if c(ac) is not 1 or aoj skipped, this test fails.
5616
5617 033715 400 00 0 00 000000 C15500: SETZ ;Preload ac with 0
5618 033716 340 00 0 00 033720 AOJ .+2 ;*Aoj should add 1 to the ac and not jump
5619 033717 302 00 0 00 000001 CAIE 1 ;Pass if c(ac)=1 and aoj did not jump
5620 STOP^
5621 033720 254 04 0 00 033721 HALT .+1 ;Test failed if program halts here
5622 033721 324 00 0 00 033722 JUMPA .+1 ;To loop change this instruction^
5623
5624 ;**********
5625
5626 ;This test verifies that aoj adds 1 to the ac and does not jump.
5627 ;First, the ac is preloaded with -1,,-1; then, aoj is executed. next, the
5628 ;Ac is checked for 0. if c(ac) is not 0 or aoj skipped, this test fails.
5629
5630 033722 474 00 0 00 000000 C15600: SETO ;Preload ac with 0
5631 033723 340 00 0 00 033725 AOJ .+2 ;*Aoj should add 1 to the ac and not jump
5632 033724 302 00 0 00 000000 CAIE 0 ;Pass if c(ac)=1 and aoj did not jump
5633 STOP^
5634 033725 254 04 0 00 033726 HALT .+1 ;Test failed if program halts here
5635 033726 324 00 0 00 033727 JUMPA .+1 ;To loop change this instruction^
5636
5637 ;**********
5638
5639 ;This test verifies that soj subtracts 1 from the ac and does not jump.
5640 ;First, the ac is preloaded with 0; then, soj is executed. next, the ac
5641 ;Is checked for -1,,-1. if c(ac) is not -1,,-1 or soj skipped, this test fails.
5642
5643 033727 400 00 0 00 000000 C15700: SETZ ;Preload ac with 0
5644 033730 360 00 0 00 033732 SOJ .+2 ;*Soj should subtract 1 from the ac and not jump
5645 033731 312 00 0 00 034443 CAME [-1] ;Pass if c(ac)=-1,,-1 and soj did not jump
5646 STOP^
5647 033732 254 04 0 00 033733 HALT .+1 ;Test failed if program halts here
5648 033733 324 00 0 00 033734 JUMPA .+1 ;To loop change this instruction^
5649
5650 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 57
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AOJ AND SOJ INSTRUCTIONS SEQ 0139
5651 ;This test verifies that soj subtracts 1 from the ac and does not jump.
5652 ;First, the ac is preloaded with -1,,-1; then, soj is executed. next, the ac
5653 ;Is checked for -1,,-2. if c(ac) is not -1,,-2 or soj skipped, this test fails.
5654
5655 033734 474 00 0 00 000000 C16000: SETO ;Preload ac with -1,,-1
5656 033735 360 00 0 00 033737 SOJ .+2 ;*Soj should subtract 1 from the ac and not jump
5657 033736 312 00 0 00 034444 CAME [-2] ;Pass if c(ac)=-1,,-2 and soj did not jump
5658 STOP^
5659 033737 254 04 0 00 033740 HALT .+1 ;Test failed if program halts here
5660 033740 324 00 0 00 033741 JUMPA .+1 ;To loop change this instruction^
5661
5662 ;**********
5663
5664 ;This test verifies that soj subtracts 1 from the ac and does not jump.
5665 ;First, the ac is preloaded with 0,,1; then, soj is executed. next, the
5666 ;Ac is checked for 0. if c(ac) is not 0 or soj skipped, this test fails.
5667
5668 033741 201 00 0 00 000001 C16100: MOVEI 1 ;Preload ac with 1
5669 033742 360 00 0 00 033744 SOJ .+2 ;*Soj should subtract 1 from the ac and not jump
5670 033743 302 00 0 00 000000 CAIE 0 ;Pass if c(ac)=0 and soj did not jump
5671 STOP^
5672 033744 254 04 0 00 033745 HALT .+1 ;Test failed if program halts here
5673 033745 324 00 0 00 033746 JUMPA .+1 ;To loop change this instruction^
5674
5675 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 58
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AOJ AND SOJ INSTRUCTIONS SEQ 0140
5676 ;This test verifies that soj ac, followed by aoj ac, has no net effect on c(ac).
5677 ;In this case, the ac is preloaded with 0; then, soj ac, followed by aoj.
5678 ;Ac, is repeated 7 times. the ac is then checked for its original contents, 0.
5679 ;If c(ac)=0, this test passes; otherwise aoj or soj failed.
5680
5681 000017 C16200: AC=17
5682 033746 400 17 0 00 000000 SETZ AC, ;Preload ac with 0
5683 REPEAT ^D10,<
5684 SOJ AC,. ;*Soj should subtract 1 from the ac
5685 AOJ AC,. ;*Aoj should add 1 to the ac>
5686
5687 033747 360 17 0 00 033747 SOJ AC,. ;*Soj should subtract 1 from the ac
5688 033750 340 17 0 00 033750 AOJ AC,. ;*Aoj should add 1 to the ac
5689
5690 033751 360 17 0 00 033751 SOJ AC,. ;*Soj should subtract 1 from the ac
5691 033752 340 17 0 00 033752 AOJ AC,. ;*Aoj should add 1 to the ac
5692
5693 033753 360 17 0 00 033753 SOJ AC,. ;*Soj should subtract 1 from the ac
5694 033754 340 17 0 00 033754 AOJ AC,. ;*Aoj should add 1 to the ac
5695
5696 033755 360 17 0 00 033755 SOJ AC,. ;*Soj should subtract 1 from the ac
5697 033756 340 17 0 00 033756 AOJ AC,. ;*Aoj should add 1 to the ac
5698
5699 033757 360 17 0 00 033757 SOJ AC,. ;*Soj should subtract 1 from the ac
5700 033760 340 17 0 00 033760 AOJ AC,. ;*Aoj should add 1 to the ac
5701
5702 033761 360 17 0 00 033761 SOJ AC,. ;*Soj should subtract 1 from the ac
5703 033762 340 17 0 00 033762 AOJ AC,. ;*Aoj should add 1 to the ac
5704
5705 033763 360 17 0 00 033763 SOJ AC,. ;*Soj should subtract 1 from the ac
5706 033764 340 17 0 00 033764 AOJ AC,. ;*Aoj should add 1 to the ac
5707
5708 033765 360 17 0 00 033765 SOJ AC,. ;*Soj should subtract 1 from the ac
5709 033766 340 17 0 00 033766 AOJ AC,. ;*Aoj should add 1 to the ac
5710
5711 033767 360 17 0 00 033767 SOJ AC,. ;*Soj should subtract 1 from the ac
5712 033770 340 17 0 00 033770 AOJ AC,. ;*Aoj should add 1 to the ac
5713
5714 033771 360 17 0 00 033771 SOJ AC,. ;*Soj should subtract 1 from the ac
5715 033772 340 17 0 00 033772 AOJ AC,. ;*Aoj should add 1 to the ac
5716 033773 332 00 0 00 000017 SKIPE AC ;Pass if c(ac) is unchanged. i.e. c(ac)=0
5717 STOP^
5718 033774 254 04 0 00 033775 HALT .+1 ;Test failed if program halts here
5719 033775 324 00 0 00 033776 JUMPA .+1 ;To loop change this instruction^
5720
5721 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 59
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AOJ AND SOJ INSTRUCTIONS SEQ 0141
5722 ;This test verifies that soj sets cry0/1 flags if c(e) is a non-zero number
5723 ;Other than 400000,,0. in this case, c(e)=1. first the flags are reset.
5724 ;Then soj is executed. the flags are checked. if cry0 and cry1 are set and
5725 ;Arov and fov are reset, this test passes.
5726
5727 033776 255 17 0 00 033777 C16201: JFCL 17,.+1 ;Reset arithmetic flags
5728 033777 201 00 0 00 000001 MOVEI 1 ;Preload e with 1
5729 034000 360 00 0 00 000000 SOJ ;*Soj should set cry0/1
5730 034001 255 04 0 00 034003 JCRY0 .+2 ;Pass if cry0 is set
5731 STOP^
5732 034002 254 04 0 00 034003 HALT .+1 ;Test failed if program halts here
5733 034003 324 00 0 00 034004 JUMPA .+1 ;To loop change this instruction^
5734 034004 255 02 0 00 034006 JCRY1 .+2 ;Pass if cry1 is set
5735 STOP^
5736 034005 254 04 0 00 034006 HALT .+1 ;Test failed if program halts here
5737 034006 324 00 0 00 034007 JUMPA .+1 ;To loop change this instruction^
5738 034007 255 10 0 00 034011 JOV .+2 ;Pass if arov is reset
5739 034010 334 00 0 00 000000 SKIPA
5740 STOP^
5741 034011 254 04 0 00 034012 HALT .+1 ;Test failed if program halts here
5742 034012 324 00 0 00 034013 JUMPA .+1 ;To loop change this instruction^
5743 034013 255 01 0 00 034015 JFOV .+2 ;Pass if fov is reset
5744 034014 334 00 0 00 000000 SKIPA
5745 STOP^
5746 034015 254 04 0 00 034016 HALT .+1 ;Test failed if program halts here
5747 034016 324 00 0 00 034017 JUMPA .+1 ;To loop change this instruction^
5748
5749 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 60
DFKAD1 MAC 1-Oct-84 16:01 TEST OF AOJ AND SOJ INSTRUCTIONS SEQ 0142
5750 ;This test verifies that aoj sets cry0 and cry1 flag if c(e) is -1,,-1.
5751 ;First the flags are reset; then aoj is executed. the flags are checked.
5752 ;If cry0 and cry1 are set and arov and fov are reset, this test passes.
5753
5754 034017 255 17 0 00 034020 C16202: JFCL 17,.+1 ;Reset arithmetic flags
5755 034020 474 00 0 00 000000 SETO ;Preload e with 1
5756 034021 340 00 0 00 000000 AOJ ;*Aoj should set cry0 and cry1
5757 034022 255 04 0 00 034024 JCRY0 .+2 ;Pass if cry0 is set
5758 STOP^
5759 034023 254 04 0 00 034024 HALT .+1 ;Test failed if program halts here
5760 034024 324 00 0 00 034025 JUMPA .+1 ;To loop change this instruction^
5761 034025 255 02 0 00 034027 JCRY1 .+2 ;Pass if cry1 is set
5762 STOP^
5763 034026 254 04 0 00 034027 HALT .+1 ;Test failed if program halts here
5764 034027 324 00 0 00 034030 JUMPA .+1 ;To loop change this instruction^
5765 034030 255 10 0 00 034032 JOV .+2 ;Pass if arov is reset
5766 034031 334 00 0 00 000000 SKIPA
5767 STOP^
5768 034032 254 04 0 00 034033 HALT .+1 ;Test failed if program halts here
5769 034033 324 00 0 00 034034 JUMPA .+1 ;To loop change this instruction^
5770 034034 255 01 0 00 034036 JFOV .+2 ;Pass if fov is reset
5771 034035 334 00 0 00 000000 SKIPA
5772 STOP^
5773 034036 254 04 0 00 034037 HALT .+1 ;Test failed if program halts here
5774 034037 324 00 0 00 034040 JUMPA .+1 ;To loop change this instruction^
5775
5776 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 61
DFKAD1 MAC 1-Oct-84 16:01 TEST OF MEMORY, BOTH AND SELF MODE INSTRUCTIONS SEQ 0143
5777 SUBTTL TEST OF MEMORY, BOTH AND SELF MODE INSTRUCTIONS
5778
5779 ;**********
5780
5781 ;This test verifies that addm does not modify c(ac)
5782 ;Both ac and e are preloaded with -1,,-1. then addm is executed.
5783 ;This test passes if c(ac) are unchanged.
5784
5785 034040 477 00 0 00 000001 C16400: SETOB 1 ;Preload ac, e with -1,,-1
5786 034041 272 00 0 00 000001 ADDM 1 ;*Addm should not affect c(ac)
5787 034042 312 00 0 00 034443 CAME [-1] ;Pass if c(ac) is unmodified by addm
5788 STOP^
5789 034043 254 04 0 00 034044 HALT .+1 ;Test failed if program halts here
5790 034044 324 00 0 00 034045 JUMPA .+1 ;To loop change this instruction^
5791
5792 ;**********
5793
5794 ;This test verifies that hrrem does not modify c(ac)
5795 ;The ac is preloaded with 0,,-1. then hrrm is executed.
5796 ;This test passes if c(ac) are unchanged.
5797
5798 034045 201 00 0 00 777777 C16500: MOVEI -1 ;Preload ac with 0,,-1
5799 034046 572 00 0 00 000001 HRREM 1 ;*Hrrm should not affect c(ac)
5800 034047 302 00 0 00 777777 CAIE -1 ;Pass if c(ac) is unmodified by hrrm
5801 STOP^
5802 034050 254 04 0 00 034051 HALT .+1 ;Test failed if program halts here
5803 034051 324 00 0 00 034052 JUMPA .+1 ;To loop change this instruction^
5804
5805 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 62
DFKAD1 MAC 1-Oct-84 16:01 TEST OF MEMORY, BOTH AND SELF MODE INSTRUCTIONS SEQ 0144
5806 ;This test verifies that movsm does not modify c(ac).
5807 ;The ac is preloaded with 0,,-1. then movsm is executed.
5808 ;This test passes if c(ac) are unchanged.
5809
5810 034052 201 00 0 00 777777 C16600: MOVEI -1 ;Preload ac with 0,,-1
5811 034053 206 00 0 00 000001 MOVSM 1 ;*Movsm should not affect c(ac)
5812 034054 302 00 0 00 777777 CAIE -1 ;Pass if c(ac) is unmodified by movsm
5813 STOP^
5814 034055 254 04 0 00 034056 HALT .+1 ;Test failed if program halts here
5815 034056 324 00 0 00 034057 JUMPA .+1 ;To loop change this instruction^
5816
5817 ;**********
5818
5819 ;This test verifies that xorm does not modify c(ac).
5820 ;Both ac and e are preloaded with -1,,-1. then xorm is executed.
5821 ;This test passes if c(ac) are unchanged.
5822
5823 034057 477 00 0 00 000001 C16700: SETOB 1 ;Preload ac, e with -1,,-1
5824 034060 432 00 0 00 000001 XORM 1 ;*Xorm should not affect c(ac)
5825 034061 312 00 0 00 034443 CAME [-1] ;Pass if c(ac) is unmodified by xorm
5826 STOP^
5827 034062 254 04 0 00 034063 HALT .+1 ;Test failed if program halts here
5828 034063 324 00 0 00 034064 JUMPA .+1 ;To loop change this instruction^
5829
5830 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 63
DFKAD1 MAC 1-Oct-84 16:01 TEST OF MEMORY, BOTH AND SELF MODE INSTRUCTIONS SEQ 0145
5831 ;This test verifies that addb adds c(ac) to c(e) and places the result
5832 ;In both ac and e. in this test, both ac and e are preloaded with -1,,-1,
5833 ;Then, addb is executed. c(ac) is then compared to c(e) and c(ac) is
5834 ;Compared to -2. if both of these comparisons succeed, this test passes.
5835 ;Otherwise, addb failed.
5836
5837 034064 477 00 0 00 000001 C17000: SETOB 1 ;Preload ac, e with -1,,-1
5838 034065 273 00 0 00 000001 ADDB 1 ;*Addb should add c(ac) to c(e) and place result
5839 ;Into both ac and e
5840 034066 312 00 0 00 000001 CAME 1 ;Pass if c(ac)=c(e)
5841 STOP^
5842 034067 254 04 0 00 034070 HALT .+1 ;Test failed if program halts here
5843 034070 324 00 0 00 034071 JUMPA .+1 ;To loop change this instruction^
5844 034071 312 00 0 00 034444 CAME [-2] ;Pass if c(ac)=-2
5845 STOP^
5846 034072 254 04 0 00 034073 HALT .+1 ;Test failed if program halts here
5847 034073 324 00 0 00 034074 JUMPA .+1 ;To loop change this instruction^
5848
5849 ;**********
5850
5851 ;This test verifies that addm adds c(ac) to c(e) and places the result in e
5852 ;In this case, ac, e are both preloaded with -1; then, addm is executed. e is
5853 ;Then checked for -2. if c(e)=-2, this test passes; otherwise, addm failed.
5854
5855 034074 477 00 0 00 000001 C17100: SETOB 1 ;Preload ac, e with -1,,-1
5856 034075 272 00 0 00 000001 ADDM 1 ;*Addm should add c(ac) to c(e)
5857 034076 312 01 0 00 034444 CAME 1,[-2] ;Pass if c(e)=-2
5858 STOP^
5859 034077 254 04 0 00 034100 HALT .+1 ;Test failed if program halts here
5860 034100 324 00 0 00 034101 JUMPA .+1 ;To loop change this instruction^
5861
5862 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 64
DFKAD1 MAC 1-Oct-84 16:01 TEST OF MEMORY, BOTH AND SELF MODE INSTRUCTIONS SEQ 0146
5863 ;This test verifies that hllos places ones on the right half of e
5864 ;But does not affect the left half of e. in this case,
5865 ;E is preloaded with 0; the, hllos is executed. the result
5866 ;In e should be 0,,-1. if c(e)=0,,-1, this test passes.
5867
5868 034101 402 00 0 00 000001 C17200: SETZM 1 ;Preload e with 0
5869 034102 523 00 0 00 000001 HLLOS 1 ;*Hllos should place 0,,-1 into e
5870 034103 302 01 0 00 777777 CAIE 1,-1 ;Pass if c(e)=0,,-1
5871 STOP^
5872 034104 254 04 0 00 034105 HALT .+1 ;Test failed if program halts here
5873 034105 324 00 0 00 034106 JUMPA .+1 ;To loop change this instruction^
5874
5875 ;**********
5876
5877 ;This test verifies that movss swaps boths halves of e and
5878 ;Places the result in e. in this case, e is preloaded with
5879 ;-1,,0; Then, movss is executed. the result in e should be 0,,-1.
5880 ;If c(e)=0,,-1, this test passes.
5881
5882 034106 205 01 0 00 777777 C17300: MOVSI 1,-1 ;Preload e with -1,,0
5883 034107 207 00 0 00 000001 MOVSS 1 ;*Movss should place 0,,-1 into e
5884 034110 302 01 0 00 777777 CAIE 1,-1 ;Pass if c(e)=0,,-1
5885 STOP^
5886 034111 254 04 0 00 034112 HALT .+1 ;Test failed if program halts here
5887 034112 324 00 0 00 034113 JUMPA .+1 ;To loop change this instruction^
5888
5889 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 65
DFKAD1 MAC 1-Oct-84 16:01 TEST OF MEMORY, BOTH AND SELF MODE INSTRUCTIONS SEQ 0147
5890 ;This test verifies that aos adds one to memory but does not skip. first,
5891 ;E is preloaded with -1,-1; then, aos is executed. next, e is checked for 0.
5892 ;If c(e) is not 0 or aos skipped, this test fails.
5893
5894 034113 477 00 0 00 000001 C17400: SETOB 1 ;Preload e with -1,,-1
5895 034114 350 00 0 00 000001 AOS 1 ;*Aos should add to c(e) and not skip
5896 034115 302 01 0 00 000000 CAIE 1,0 ;Pass if c(e)=0,,0 and aos did not skip
5897 STOP^
5898 034116 254 04 0 00 034117 HALT .+1 ;Test failed if program halts here
5899 034117 324 00 0 00 034120 JUMPA .+1 ;To loop change this instruction^
5900
5901 ;**********
5902
5903 ;This test verifies that hrlm places c(ac-right) into e-left and does not
5904 ;Modify e-right. in this case, ac is preloaded with 0 and e is preloaded
5905 ;With -1,,-1. then, hrlm is executed. e is then checked for 0,,-1. if
5906 ;C(e)=0,,-1, this test passes.
5907
5908 034120 400 00 0 00 000000 C17500: SETZ ;Preload ac with 0
5909 034121 474 01 0 00 000000 SETO 1, ;Preload e with -1,,-1
5910 034122 506 00 0 00 000001 HRLM 1 ;*Hrlm should place 0,,-1 into e
5911 034123 302 01 0 00 777777 CAIE 1,-1 ;Pass if c(e)=0,,-1
5912 STOP^
5913 034124 254 04 0 00 034125 HALT .+1 ;Test failed if program halts here
5914 034125 324 00 0 00 034126 JUMPA .+1 ;To loop change this instruction^
5915
5916 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 66
DFKAD1 MAC 1-Oct-84 16:01 TEST OF MEMORY, BOTH AND SELF MODE INSTRUCTIONS SEQ 0148
5917 ;This test verifies that hrrs does not modify e. e is preloaded
5918 ;With 0 and ac is preloaded with -1,,-1. hrrs is executed; then
5919 ;E is checked. if c(e) does not change, this test passes.
5920
5921 034126 474 00 0 00 000000 C17600: SETO ;Preload ac with -1,,-1
5922 034127 400 01 0 00 000000 SETZ 1, ;Preload e with 0,,0
5923 034130 543 00 0 00 000001 HRRS 1 ;*Hrrs should place 0,,0 into e
5924 034131 332 00 0 00 000001 SKIPE 1
5925 STOP^
5926 034132 254 04 0 00 034133 HALT .+1 ;Test failed if program halts here
5927 034133 324 00 0 00 034134 JUMPA .+1 ;To loop change this instruction^
5928
5929 ;**********
5930
5931 ;This test verifies that hrrzm places c(ac-right) into e-right and places
5932 ;Zeros into e-left. in this case, ac=e=ac1 and c(ac)=c(e)=-1,,0. hrrzm
5933 ;Is executed and ac1 is checked for 0. if ac1=0, this test passes.
5934
5935 034134 474 00 0 00 000000 C17700: SETO ;Preload ac0 with -1,,-1
5936 034135 205 01 0 00 777777 MOVSI 1,-1 ;Preload ac1 with -1,,0
5937 034136 552 01 0 00 000001 HRRZM 1,1 ;*Hrrzm should place 0 into ac1
5938 034137 332 00 0 00 000001 SKIPE 1 ;Pass if c(ac1)=0
5939 STOP^
5940 034140 254 04 0 00 034141 HALT .+1 ;Test failed if program halts here
5941 034141 324 00 0 00 034142 JUMPA .+1 ;To loop change this instruction^
5942
5943 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 67
DFKAD1 MAC 1-Oct-84 16:01 TEST OF MEMORY, BOTH AND SELF MODE INSTRUCTIONS SEQ 0149
5944 ;This test verifies that jfcl 17,.+1 never jumps and does not modify c(ac0).
5945 ;First, ac0 is preloaded; then, jfcl is executed. if ac0 is modified or
5946 ;Jfcl skips, this test fails.
5947
5948 034142 400 00 0 00 000000 C20000: SETZ ;Clear ac0
5949 034143 255 17 0 00 034144 JFCL 17,.+1 ;*Jfcl should not jump or modify c(ac0).
5950 034144 332 00 0 00 000000 SKIPE ;Pass if c(ac0)=0 and jfcl did not jump
5951 STOP^
5952 034145 254 04 0 00 034146 HALT .+1 ;Test failed if program halts here
5953 034146 324 00 0 00 034147 JUMPA .+1 ;To loop change this instruction^
5954
5955 ;**********
5956
5957 ;This test verifies that xorm performs the logical exclusive or function
5958 ;Between c(ac) and c(e) and places the result into e. in this case,
5959 ;Ac and e are preloaded with -1,,-1; then, xorm is executed. if the
5960 ;Result in e is 0, the test passes.
5961
5962 034147 477 00 0 00 000001 C20100: SETOB 1 ;Preload ac,e with -1,,-1
5963 034150 432 00 0 00 000001 XORM 1 ;*Xorm should place 0 into e
5964 034151 302 01 0 00 000000 CAIE 1,0 ;Pass if c(e)=0
5965 STOP^
5966 034152 254 04 0 00 034153 HALT .+1 ;Test failed if program halts here
5967 034153 324 00 0 00 034154 JUMPA .+1 ;To loop change this instruction^
5968
5969 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 68
DFKAD1 MAC 1-Oct-84 16:01 TEST OF MEMORY, BOTH AND SELF MODE INSTRUCTIONS SEQ 0150
5970 ;This test verifies that setzb places zeros into both ac and e.
5971 ;After setzb is executed, both ac and e are checked for 0. if
5972 ;Either ac or e contains any ones, this test fails.
5973
5974 034154 403 00 0 00 000001 C20200: SETZB 1 ;*Setzb should place zeroes in both ac and e
5975 034155 316 00 0 00 034513 CAMN [0] ;Fail if c(ac) is non-zero
5976 034156 312 00 0 00 000001 CAME 1 ;Fail if c(e) is non-zero
5977 STOP^
5978 034157 254 04 0 00 034160 HALT .+1 ;Test failed if program halts here
5979 034160 324 00 0 00 034161 JUMPA .+1 ;To loop change this instruction^
5980
5981 ;**********
5982
5983 ;This test verifies that setab places c(ac) into both ac and e.
5984 ;First, ac is preloaded with -1,,-1 and e is preloaded with 0;
5985 ;Then, setab is executed. both ac and e are checked for -1,,-1
5986 ;If either ac or e contain any zeros, this test fails.
5987
5988 034161 400 01 0 00 000000 C20300: SETZ 1, ;Preload e with 0
5989 034162 474 00 0 00 000000 SETO ;Preload ac with -1,,-1
5990 034163 427 00 0 00 000001 SETAB 1 ;*Setab should place -1,,-1 into both ac and e
5991 034164 316 00 0 00 034443 CAMN [-1] ;Fail if c(ac) is not -1,-1
5992 034165 312 00 0 00 000001 CAME 1 ;Fail if c(e) is not -1,,-1
5993 STOP^
5994 034166 254 04 0 00 034167 HALT .+1 ;Test failed if program halts here
5995 034167 324 00 0 00 034170 JUMPA .+1 ;To loop change this instruction^
5996
5997 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 69
DFKAD1 MAC 1-Oct-84 16:01 XCT INSTRUCTION - BASIC TESTS SEQ 0151
5998 SUBTTL XCT INSTRUCTION - BASIC TESTS
5999
6000 ;**********
6001
6002 ;This test verifies that xct will execute the instruction specified by c(e).
6003 ;In this case, c(e) specifies a movei instruction. after executing movei,
6004 ;Control should return to the next sequential instruction following xct. this
6005 ;Test passes if control returns to the next sequential instruction following xct.
6006
6007 034170 403 00 0 00 000001 C20400: SETZB 1 ;Clear ac0 and ac1
6008 034171 256 00 0 00 034517 XCT [MOVEI 1,.+2] ;*Xct should return control to next instruction
6009 034172 334 00 0 00 000000 SKIPA
6010 STOP^
6011 034173 254 04 0 00 034174 HALT .+1 ;Test failed if program halts here
6012 034174 324 00 0 00 034175 JUMPA .+1 ;To loop change this instruction^
6013
6014 ;**********
6015
6016 ;This test verifies that xct will execute the instruction specified by c(e)
6017 ;In this case, c(e) specifies a movei instruction. after executing movei,
6018 ;The ac specified by movei is checked for 0,,1 (the expected result). if
6019 ;C(ac)=0,,1, this test passes.
6020
6021 034175 403 00 0 00 000001 C20500: SETZB 1 ;Clear ac
6022 034176 256 00 0 00 034520 XCT [MOVEI 1,1] ;*Xct of movei should place 1 in the ac
6023 034177 302 01 0 00 000001 CAIE 1,1 ;Pass if c(ac)=1
6024 STOP^
6025 034200 254 04 0 00 034201 HALT .+1 ;Test failed if program halts here
6026 034201 324 00 0 00 034202 JUMPA .+1 ;To loop change this instruction^
6027
6028 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 70
DFKAD1 MAC 1-Oct-84 16:01 XCT INSTRUCTION - BASIC TESTS SEQ 0152
6029 ;This test verifies that a nest of xct instructions will execute the
6030 ;Instruction specified by the most nested xct and return control to the
6031 ;Next sequential instruction following the first xct. in this case, the
6032 ;Executed instruction is movei. after executing the movei, c(ac) is
6033 ;Checked for 0,,-1 (the expected result). if c(ac)=0,,-1, this test passes.
6034
6035 034202 403 00 0 00 000001 C20600: SETZB 1 ;Clear ac
6036 034203 256 00 0 00 034525 XCT [XCT[XCT[XCT[XCT[MOVEI 1,-1]]]]] ;*Nested xct of movei
6037 ;Should place 0,,-1 into ac
6038 034204 302 01 0 00 777777 CAIE 1,-1 ;Pass if c(ac)=0,,-1
6039 STOP^
6040 034205 254 04 0 00 034206 HALT .+1 ;Test failed if program halts here
6041 034206 324 00 0 00 034207 JUMPA .+1 ;To loop change this instruction^
6042
6043 ;**********
6044
6045 ;This test verifies that xct will not modify an ac which is not specified by
6046 ;The executed instruction. in this case, ac0 is cleared and then checked for
6047 ;Zero after the xct instruction is executed. ac0 should not be modified.
6048
6049 034207 403 00 0 00 000001 C20700: SETZB 1 ;Clear ac0,ac1
6050 034210 256 00 0 00 034526 XCT [MOVE 1,[-1]] ;*Xct should not modify ac0
6051 034211 332 00 0 00 000000 SKIPE ;Pass if ac0 was not modified
6052 STOP^
6053 034212 254 04 0 00 034213 HALT .+1 ;Test failed if program halts here
6054 034213 324 00 0 00 034214 JUMPA .+1 ;To loop change this instruction^
6055
6056 ;**********
6057
6058 ;This test verifies that xct of skipa should return control to
6059 ;The second sequential instruction following xct.
6060
6061 034214 256 00 0 00 034527 C21000: XCT [SKIPA] ;Xct of skipa should return control to .+2
6062 STOP^
6063 034215 254 04 0 00 034216 HALT .+1 ;Test failed if program halts here
6064 034216 324 00 0 00 034217 JUMPA .+1 ;To loop change this instruction^
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 71
DFKAD1 MAC 1-Oct-84 16:01 INDIRECT ADDRESSING - BASIC TESTS SEQ 0153
6065 SUBTTL INDIRECT ADDRESSING - BASIC TESTS
6066
6067 ;**********
6068
6069 ;This test verifies that indirect addressing works when both e and @e
6070 ;Are within the ac range. the instruction specifying indirect addressing
6071 ;Is a move. after move is executed, c(ac) is checked for 0, the initial
6072 ;Contents of the indirect address.
6073
6074 034217 476 00 0 00 000001 C21100: SETOM 1 ;Preload ac with -1,,-1
6075 034220 201 07 0 00 000003 MOVEI 7,3 ;Setup direct address with indirect address
6076 034221 402 00 0 00 000003 SETZM 3 ;Preload indirect address with 0
6077 034222 200 01 1 00 000007 MOVE 1,@7 ;*Fwt from indirect addresss should
6078 ;Place 0 into the ac
6079 034223 332 00 0 00 000001 SKIPE 1 ;Pass if c(ac)=0
6080 STOP^
6081 034224 254 04 0 00 034225 HALT .+1 ;Test failed if program halts here
6082 034225 324 00 0 00 034226 JUMPA .+1 ;To loop change this instruction^
6083
6084 ;**********
6085
6086 ;This test verifies that indirect addressing works when both e and @e
6087 ;Are within the ac range. the instruction specifying indirect addressing
6088 ;Is a move. after move is executed, c(ac) is checked for -1,,-1, the
6089 ;Initial contents of the indirect address.
6090
6091 034226 402 00 0 00 000001 C21200: SETZM 1 ;Preload ac with -1,,-1
6092 034227 201 07 0 00 000003 MOVEI 7,3 ;Setup direct address with indirect address
6093 034230 476 00 0 00 000003 SETOM 3 ;Preload indirect address with -1,,-1
6094 034231 200 01 1 00 000007 MOVE 1,@7 ;*Fwt from indirect address should
6095 ;Place -1,,-1 into the ac
6096 034232 312 01 0 00 034443 CAME 1,[-1,,-1] ;Pass if c(ac)=-1,,-1
6097 STOP^
6098 034233 254 04 0 00 034234 HALT .+1 ;Test failed if program halts here
6099 034234 324 00 0 00 034235 JUMPA .+1 ;To loop change this instruction^
6100
6101 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 72
DFKAD1 MAC 1-Oct-84 16:01 INDIRECT ADDRESSING - BASIC TESTS SEQ 0154
6102 ;This test verifies that indirect addressing works when both e and @e
6103 ;Are within the ac range. the instruction specifying indirect addressing
6104 ;Is a move. after move is executed, c(ac) is checked for 707070,,707070,
6105 ;The initial contents of the indirect address.
6106
6107 034235 402 00 0 00 000001 C21300: SETZM 1 ;Preload ac with 0
6108 034236 201 07 0 00 000003 MOVEI 7,3 ;Setup direct address with indirect address
6109 034237 200 03 0 00 034530 MOVE 3,[707070,,707070] ;Preload indirect address with 707070,,707070
6110 034240 200 01 1 00 000007 MOVE 1,@7 ;*Fwt from indirect address should
6111 ;Place 707070,,707070 into the ac
6112 034241 312 01 0 00 034530 CAME 1,[707070,,707070] ;Pass if c(ac)=707070,,707070
6113 STOP^
6114 034242 254 04 0 00 034243 HALT .+1 ;Test failed if program halts here
6115 034243 324 00 0 00 034244 JUMPA .+1 ;To loop change this instruction^
6116
6117 ;**********
6118
6119 ;This test verifies that indirect addressing works when e is within the ac
6120 ;Range and @e is beyond the ac range. the instruction specifying indirect
6121 ;Addressing is a move. after move is executed, c(ac) is checked for
6122 ;707070,,707070, The initial contents of the indirect address.
6123
6124 034244 254 00 0 00 034246 C21400: JRST .+2
6125 034245 707070 707070 XWD 707070,707070 ;Indirect address and its data
6126 034246 402 00 0 00 000001 SETZM 1 ;Preload ac with 0
6127 034247 201 07 0 00 034245 MOVEI 7,C21400+1 ;Setup direct address with indirect address
6128 034250 200 01 1 00 000007 MOVE 1,@7 ;*Fwt from indirect address should
6129 ;Place 707070,,707070 into ac
6130 034251 312 01 0 00 034245 CAME 1,C21400+1 ;Pass if c(ac)=707070,,707070
6131 STOP^
6132 034252 254 04 0 00 034253 HALT .+1 ;Test failed if program halts here
6133 034253 324 00 0 00 034254 JUMPA .+1 ;To loop change this instruction^
6134
6135 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 73
DFKAD1 MAC 1-Oct-84 16:01 INDIRECT ADDRESSING - BASIC TESTS SEQ 0155
6136 ;This test verifies that indirect addressing works when both e and @e
6137 ;Are beyond the ac range. the instruction specifying indirect addressing
6138 ;Is a move. after move is executed, c(ac) is checked for 202020,,202020,
6139 ;The initial contents of the indirect address.
6140
6141 034254 254 00 0 00 034257 C21500: JRST .+3
6142 034255 000000 034256 .+1 ;Direct address and its data
6143 034256 202020 202020 XWD 202020,202020 ;Indirect address and its data
6144 034257 402 00 0 00 000001 SETZM 1 ;Preload ac with 0
6145 034260 200 01 1 00 034255 MOVE 1,@C21500+1 ;*Fwt from indirect address should
6146 ;Place 202020,,202020 into ac
6147 034261 312 01 0 00 034256 CAME 1,C21500+2 ;Pass if c(ac)=202020,,202020
6148 STOP^
6149 034262 254 04 0 00 034263 HALT .+1 ;Test failed if program halts here
6150 034263 324 00 0 00 034264 JUMPA .+1 ;To loop change this instruction^
6151
6152 ;**********
6153
6154 ;This test verifies that indirect addressing works when both e and @e
6155 ;Are beyond the ac range. the instruction specifying indirect
6156 ;Addressing is a came.
6157
6158 034264 254 00 0 00 034267 C21600: JRST .+3
6159 034265 000000 034266 .+1 ;Direct address and its data
6160 034266 272727 272727 XWD 272727,272727 ;Indirect address and its data
6161 034267 200 01 0 00 034266 MOVE 1,C21600+2 ;Preload ac
6162 034270 312 01 1 00 034265 CAME 1,@C21600+1 ;*Came of data from indirect address - non-ac range
6163 STOP^
6164 034271 254 04 0 00 034272 HALT .+1 ;Test failed if program halts here
6165 034272 324 00 0 00 034273 JUMPA .+1 ;To loop change this instruction^
6166
6167 ;**********
6168
6169 ;This test verifies that indirect addressing works when e is within the ac
6170 ;Range and @e is beyond the ac range. the instruction specifying indirect
6171 ;Addressing is a came.
6172
6173 034273 254 00 0 00 034275 C21700: JRST .+2
6174 034274 252525 252525 XWD 252525,252525 ;Indirect address and its data
6175 034275 201 07 0 00 034274 MOVEI 7,C21700+1 ;Setup direct address with indirect address
6176 034276 200 01 0 00 034274 MOVE 1,C21700+1 ;Setup ac
6177 034277 312 01 1 00 000007 CAME 1,@7 ;*Came if data from indirect address - ac range
6178 STOP^
6179 034300 254 04 0 00 034301 HALT .+1 ;Test failed if program halts here
6180 034301 324 00 0 00 034302 JUMPA .+1 ;To loop change this instruction^
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 74
DFKAD1 MAC 1-Oct-84 16:01 TEST INDIRECT ADDRESSING WITH INDEXING SEQ 0156
6181 SUBTTL TEST INDIRECT ADDRESSING WITH INDEXING
6182
6183 ;Setup index registers
6184
6185 034302 201 01 0 00 777774 MOVEI 1,-4
6186 034303 201 03 0 00 000002 MOVEI 3,2
6187 034304 201 04 0 00 000010 MOVEI 4,10
6188 034305 201 05 0 00 000001 MOVEI 5,1
6189 034306 201 06 0 00 000005 MOVEI 6,5
6190 034307 201 07 0 00 000007 MOVEI 7,7
6191 034310 201 10 0 00 000004 MOVEI 10,4
6192 034311 201 11 0 00 777772 MOVEI 11,-6
6193 034312 201 12 0 00 000005 MOVEI 12,5
6194 034313 201 13 0 00 000002 MOVEI 13,2
6195
6196 034314 254 00 0 00 034345 JRST C22000 ;Resume test
6197
6198 ;Indirect addressing/indexing test table
6199
6200 ;;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;;
6201
6202 ;Do not modify this table or tests c21700 thru c22600 independently !
6203
6204 ;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;;
6205
6206 034315 000003 034320 E217: E217A(3)
6207 034316 000020 034323 E220: @E220A
6208 034317 220220 220220 E220B: 220220,,220220
6209 034320 000020 034325 E217A: @E221A ;E221-4
6210 034321 221221 221221 E221B: 221221,,221221
6211 034322 217217 217217 E222A: 217217,,217217 ;E217a+2
6212 034323 000000 034317 E220A: E220B
6213 034324 000000 034324 E221: E221
6214 034325 000000 034321 E221A: E221B
6215 034326 000000 034324 E222: E221
6216 034327 223223 223223 E223A: 223223,,223223
6217 034330 000004 034330 E224A: E224A(4) ;E223-6
6218 034331 222222 222222 222222,,222222 ;E222a+7
6219 034332 000000 034332 E225: E225
6220 034333 000007 034322 E222A(7) ;E222+5
6221 034334 000020 034337 @E225A ;E225+2
6222 034335 225225 225225 E225B: 225225,,225225
6223 034336 000000 034336 E223: E223
6224 034337 000000 034335 E225A: E225B
6225 034340 224224 224224 224224,,224224 ;E224a+10
6226 034341 226226 226226 E226B: 226226,,226226
6227 034342 000000 034327 E223A ;E223+4
6228 034343 000025 034343 E226A: @E226A(5) ;E223+5
6229 034344 000000 034341 E226B ;E226a+1
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 75
DFKAD1 MAC 1-Oct-84 16:01 TEST INDIRECT ADDRESSING WITH INDEXING SEQ 0157
6230 ;This test verifies that indirect addressing in combination with indexing
6231 ;Functions correctly. in this case, move 2,@e217 is tested where
6232 ;C(e217)=e217a(3) and c(3)=0,,2. hence, the result in the ac should be
6233 ;C(e217a+2)=217217,,217217 .
6234
6235 034345 476 00 0 00 000002 C22000: SETOM 2 ;Initialize ac
6236 034346 200 02 1 00 034315 MOVE 2,@E217 ;Test indirect addressing with indexing
6237 034347 312 02 0 00 034322 CAME 2,E217A+2 ;Pass if c(ac)=217217,,217217
6238 STOP^
6239 034350 254 04 0 00 034351 HALT .+1 ;Test failed if program halts here
6240 034351 324 00 0 00 034352 JUMPA .+1 ;To loop change this instruction^
6241
6242 ;**********
6243
6244 ;This test verifies that indirect addressing in combination with indexing
6245 ;Functions correctly. in this case, move 2,@e220 is tested where
6246 ;C(e220)=@e220a and c(e220a)=e220b. hence, the result in the ac should
6247 ;Be c(e220b)=220220,,220220 .
6248
6249 034352 402 00 0 00 000002 C22100: SETZM 2 ;Initialize ac
6250 034353 200 02 1 00 034316 MOVE 2,@E220 ;Test indirect addressing with indexing
6251 034354 312 02 0 00 034317 CAME 2,E220B ;Pass if c(ac)=220220,,220220
6252 STOP^
6253 034355 254 04 0 00 034356 HALT .+1 ;Test failed if program halts here
6254 034356 324 00 0 00 034357 JUMPA .+1 ;To loop change this instruction^
6255
6256 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 76
DFKAD1 MAC 1-Oct-84 16:01 TEST INDIRECT ADDRESSING WITH INDEXING SEQ 0158
6257 ;This test verifies that indirect addressing in combination with indexing
6258 ;Functions correctly. in this case,e221(1) 2,@e217 is tested where c(1)=-4
6259 ;And e221-4=e217a. hence, the result in the ac should be
6260 ;C(e217a)=@e221a=20,,e221a .
6261
6262 034357 476 00 0 00 000002 C22200: SETOM 2 ;Initialize ac
6263 034360 200 02 0 01 034324 MOVE 2,E221(1) ;Test indirect addressing with indexing
6264 034361 312 02 0 00 034320 CAME 2,E217A ;Pass if c(ac)=@e221a=20,,e221a
6265 STOP^
6266 034362 254 04 0 00 034363 HALT .+1 ;Test failed if program halts here
6267 034363 324 00 0 00 034364 JUMPA .+1 ;To loop change this instruction^
6268
6269 ;**********
6270
6271 ;This test verifies that indirect addressing in combination with indexing
6272 ;Functions correctly. in this case, move 2,e222(6) is tested where c(6)=5
6273 ;Hence, the result in the ac should be c(e222+5)=e222a(7)=7,,e222a .
6274
6275 034364 402 00 0 00 000002 C22300: SETZM 2 ;Initialize ac
6276 034365 200 02 0 06 034326 MOVE 2,E222(6) ;Test indirect addressing with indexing
6277 034366 312 02 0 00 034333 CAME 2,E222+5 ;Pass if c(ac)=e222a(7)=7,,e222a
6278 STOP^
6279 034367 254 04 0 00 034370 HALT .+1 ;Test failed if program halts here
6280 034370 324 00 0 00 034371 JUMPA .+1 ;To loop change this instruction^
6281
6282 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 77
DFKAD1 MAC 1-Oct-84 16:01 TEST INDIRECT ADDRESSING WITH INDEXING SEQ 0159
6283 ;This test verifies that indirect addressing in combination with indexing
6284 ;Functions correctly. in this case, move 2,@e223(10) is tested where c(10)=4
6285 ;And c(e223+4)=e223a. hence, the result in the ac should be
6286 ;C(e223a)=223223,,223223 .
6287
6288 034371 476 00 0 00 000002 C22400: SETOM 2 ;Initialize ac
6289 034372 200 02 1 10 034336 MOVE 2,@E223(10) ;Test indirect addressing with indexing
6290 034373 312 02 0 00 034327 CAME 2,E223A ;Pass if c(ac)=223223,,223223
6291 STOP^
6292 034374 254 04 0 00 034375 HALT .+1 ;Test failed if program halts here
6293 034375 324 00 0 00 034376 JUMPA .+1 ;To loop change this instruction^
6294
6295 ;**********
6296
6297 ;This test verifies that indirect addressing in combination with indexing
6298 ;Functions correctly. in this case, move 2,@e223(11) is tested where
6299 ;C(11)=-6, c(e223-6)=e224a(4) and c(4)=10. hence, the result in the ac
6300 ;Should be c(e224a+10)=224224,,224224 .
6301
6302 034376 402 00 0 00 000002 C22500: SETZM 2 ;Initialize ac
6303 034377 200 02 1 11 034336 MOVE 2,@E223(11) ;Test indirect addressing with indexing
6304 034400 312 02 0 00 034340 CAME 2,E224A+10 ;Pass if c(ac)=224224,,224224
6305 STOP^
6306 034401 254 04 0 00 034402 HALT .+1 ;Test failed if program halts here
6307 034402 324 00 0 00 034403 JUMPA .+1 ;To loop change this instruction^
6308
6309 ;**********
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 78
DFKAD1 MAC 1-Oct-84 16:01 TEST INDIRECT ADDRESSING WITH INDEXING SEQ 0160
6310 ;This test verifies that indirect addressing in combination with indexing
6311 ;Functions correctly. in this case, move 2,@e225(13) is tested where c(13)=2,
6312 ;C(e225+2)=@e225a and c(e225a)=e225b. hence, the result in the ac should be
6313 ;C(e225b)=225225,,225225.
6314
6315 034403 476 00 0 00 000002 C22600: SETOM 2 ;Initialize ac
6316 034404 200 02 1 13 034332 MOVE 2,@E225(13) ;Test indirect addressing with indexing
6317 034405 312 02 0 00 034335 CAME 2,E225B ;Pass if c(ac)=225225,,225225
6318 STOP^
6319 034406 254 04 0 00 034407 HALT .+1 ;Test failed if program halts here
6320 034407 324 00 0 00 034410 JUMPA .+1 ;To loop change this instruction^
6321
6322 ;**********
6323
6324 ;This test verifies that indirect addressing in combination with indexing
6325 ;Functions correctly. in this case, move 2,@e223(12) is tested where
6326 ;C(12)=5, c(e223+5)=@e226a(5), c(5)=1 and c(e226a+1)=e226b. hence, the
6327 ;Result in the ac should be c(e226b)=226226,,226226.
6328
6329 034410 402 00 0 00 000002 C22700: SETZM 2 ;Initialize ac
6330 034411 200 02 1 12 034336 MOVE 2,@E223(12) ;Test indirect addressing with indexing
6331 034412 312 02 0 00 034341 CAME 2,E226B ;Pass if c(ac)=226226,,226226
6332 STOP^
6333 034413 254 04 0 00 034414 HALT .+1 ;Test failed if program halts here
6334 034414 324 00 0 00 034415 JUMPA .+1 ;To loop change this instruction^
6335
6336 ;**********
6337
6338
6339 034415 402 00 0 00 034572 ENDIT: SETZM TNUMB#
6340 034416 254 00 0 00 030057 JRST BEGEND
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 1
STOR KLM 18-Sep-79 17:18 *STOR* RESERVED STORAGE, SEPT 18,1979 SEQ 0161
6341 SUBTTL *STOR* RESERVED STORAGE, SEPT 18,1979
6342
6343 ;PROGRAM LITERALS
6344
6345 XLIST
6346 IFNDEF $LPAPER,<LIST>
6347 034417 LIT
6348 034417 000001 000001
6349 034420 254 00 0 00 030715
6350 034421 000001 000000
6351 034422 000002 000000
6352 034423 000004 000000
6353 034424 000010 000000
6354 034425 000020 000000
6355 034426 000040 000000
6356 034427 000100 000000
6357 034430 000200 000000
6358 034431 000400 000000
6359 034432 001000 000000
6360 034433 002000 000000
6361 034434 004000 000000
6362 034435 010000 000000
6363 034436 020000 000000
6364 034437 040000 000000
6365 034440 100000 000000
6366 034441 200000 000000
6367 034442 400000 000000
6368 034443 777777 777777
6369 034444 777777 777776
6370 034445 777777 777775
6371 034446 777777 777773
6372 034447 777777 777767
6373 034450 777777 777757
6374 034451 777777 777737
6375 034452 777777 777677
6376 034453 777777 777577
6377 034454 777777 777377
6378 034455 777777 776777
6379 034456 777777 775777
6380 034457 777777 773777
6381 034460 777777 767777
6382 034461 777777 757777
6383 034462 777777 737777
6384 034463 777777 677777
6385 034464 777777 577777
6386 034465 777777 377777
6387 034466 777776 777777
6388 034467 777775 777777
6389 034470 777773 777777
6390 034471 777767 777777
6391 034472 777757 777777
6392 034473 777737 777777
6393 034474 777677 777777
6394 034475 777577 777777
6395 034476 777377 777777
DFKAD PDP10 Kl10 BASIC INSTRUCTION DIAGNOSTIC (4) 0,2 MACRO %53A(1152) 10:53 2-Oct-84 Page 1-1
STOR KLM 18-Sep-79 17:18 *STOR* RESERVED STORAGE, SEPT 18,1979 SEQ 0162
6396 034477 776777 777777
6397 034500 775777 777777
6398 034501 773777 777777
6399 034502 767777 777777
6400 034503 757777 777777
6401 034504 737777 777777
6402 034505 677777 777777
6403 034506 577777 777777
6404 034507 377777 777777
6405 034510 777777 000000
6406 034511 000000 777777
6407 034512 252525 252525
6408 034513 000000 000000
6409 034514 254 04 0 00 032717
6410 034515 377777 377777
6411 034516 400000 400000
6412 034517 201 01 0 00 034173
6413 034520 201 01 0 00 000001
6414 034521 201 01 0 00 777777
6415 034522 256 00 0 00 034521
6416 034523 256 00 0 00 034522
6417 034524 256 00 0 00 034523
6418 034525 256 00 0 00 034524
6419 034526 200 01 0 00 034443
6420 034527 334 00 0 00 000000
6421 034530 707070 707070
6422 LIST
6423 034531 000000 000000 ENDSLD: 0
6424
6425 IFDEF DEBUG,<
6426 034532 PATCH: BLOCK DEBUG ;PATCHING AREA
6427 >
6428
6429 ;PROGRAM VARIABLES
6430 034572 VAR
6431
6432 IFDEF PGMEND,<
6433 034573 000000 000000 END: 0
6434 030000 END BEGIN >
NO ERRORS DETECTED
PROGRAM BREAK IS 000000
ABSOLUTE BREAK IS 034574
CPU TIME USED 00:18.819
23P CORE USED
ABORT 92#
AC 5681# 5682 5687 5688 5690 5691 5693 5694 5696 5697 5699 5700 5702 5703 SEQ 0163
5705 5706 5708 5709 5711 5712 5714 5715 5716
AC0 693#
ALTMGO 446#
AMCLRB 360#
ANXM 360#
AROV 360# 4820 4999 5003
AROVTP 360#
AROVU 360#
AST 561#
ATSIN 562#
BEGEND 442# 6340
BEGIN 43 44 45 46 47 48 49 50 51 52 53 307 308 373#
736 844 6434
BEGIN1 389# 443
BELL 565#
BIS 360#
C100 887#
C1000 1840#
C10000 5015#
C10100 5035#
C10200 5054#
C10300 5074#
C10400 5091#
C10500 5103#
C1100 2137#
C11200 5117#
C11300 5130#
C11400 5142#
C11500 5155#
C11600 5166#
C11700 5178#
C1200 2151#
C12000 5192#
C12100 5207#
C12200 5235#
C12300 5250#
C12301 5278#
C12600 5308#
C12700 5321#
C1300 2570#
C13100 5333#
C13200 5346#
C13300 5359#
C13400 5386#
C13600 5417#
C13700 5435#
C1400 2993#
C14000 5452#
C14100 5474#
C14200 5491#
C14500 5516#
C14600 5528#
C14700 5541# SEQ 0164
C1500 3007#
C15000 5552#
C15100 5564#
C15200 5577#
C15300 5589#
C15400 5601#
C15500 5617#
C15600 5630#
C15700 5643#
C1600 3426#
C16000 5655#
C16100 5668#
C16200 5681#
C16201 5727#
C16202 5754#
C16400 5785#
C16500 5798#
C16600 5810#
C16700 5823#
C1700 3854#
C17000 5837#
C17100 5855#
C17200 5868#
C17300 5882#
C17400 5894#
C17500 5908#
C17600 5921#
C17700 5935#
C200 901#
C2000 4055#
C20000 5948#
C20100 5962#
C20200 5974#
C20300 5988#
C20400 6007#
C20500 6021#
C20600 6035#
C20700 6049#
C2100 4254#
C21000 6061#
C21100 6074#
C21200 6091#
C21300 6107#
C21400 6124# 6127 6130
C21500 6141# 6145 6147
C21600 6158# 6161 6162
C21700 6173# 6175 6176
C2200 4267#
C22000 6196 6235#
C22100 6249#
C22200 6262#
C22300 6275#
C22400 6288# SEQ 0165
C22500 6302#
C22600 6315#
C22700 6329#
C2400 4280#
C2410 4287#
C2700 4299#
C2710 4306#
C300 913#
C3000 4317#
C3100 4339#
C3110 4354#
C3200 4364#
C3210 4371#
C3300 4384#
C3400 4398#
C3500 4413#
C3600 4429#
C3700 4443#
C400 926#
C4000 4457#
C4100 4472#
C4200 4486#
C4300 4501#
C4400 4516#
C4500 4529#
C4600 4543#
C4700 4556#
C500 941#
C5000 4571#
C5100 4585#
C5200 4599#
C5300 4614#
C5400 4629#
C5500 4645#
C5600 4663#
C5700 4680#
C5701 4695#
C5702 4709#
C600 1258#
C6000 4727#
C6100 4742#
C6200 4757#
C6300 4776#
C6400 4797#
C6500 4818#
C6600 4835#
C6700 4853#
C700 1583#
C7000 4868#
C7100 4888#
C7200 4909#
C7300 4931#
C7400 4950# SEQ 0166
C7500 4966#
C7600 4979#
C7700 4996#
CCA 360#
CHAIN 112#
CHNOFF 360#
CHNON 360#
CLK 360#
CLKCLR 360#
CLKDIS 360#
CLKENB 360#
CLKU 360#
CLOCKF 428#
CNTLC 445#
CNTRP 360#
COMMA 554#
CONSW 429#
CPOPJ 449#
CPOPJ1 447#
CRLF 242 243 549#
CRLF2 246 247 551#
CRY0 360# 4760 4890 5018 5022
CRY1 360# 4837 5038 5042
CSHFLG 608#
CSHMEM 609#
CTRP 360#
CYCL60 602#
DCK 360# 5476 5480 5493 5502
DDT 695#
DDTLNK 126# 387
DDTSRT 387#
DEBUG 30# 6425 6426
DECVER 4# 10 24 408
DF22F 513#
DIAGMN 376#
DIAGNO 694#
DIAMON 696#
DING 98#
DOLLAR 568#
DONG11 697# 828 841
DSKUPD 413
DTE 701# 828 841
DTE0 702#
DTE1 703#
DTE2 704#
DTE3 705#
E217 6206# 6236
E217A 6206 6209# 6237 6264
E220 6207# 6250
E220A 6207 6212#
E220B 6208# 6212 6251
E221 6213# 6213 6215 6263
E221A 6209 6214# SEQ 0167
E221B 6210# 6214
E222 6215# 6276 6277
E222A 6211# 6220
E223 6223# 6223 6289 6303 6330
E223A 6216# 6227 6290
E224A 6217# 6217 6304
E225 6219# 6219 6316
E225A 6221 6224#
E225B 6222# 6224 6317
E226A 6228# 6228
E226B 6226# 6229 6331
END 6433#
ENDFIX 688#
ENDIT 6339#
ENDSLD 6423#
ERDIAG 37#
ERMORE 462#
ERRPC 433#
ERRTLS 434#
ERSTOP 101#
EXCASB 31# 411
EXCMEM 360#
EXCPFW 360#
EXIOT 360#
FOV 360# 4855 4870 4911 5057 5061 5419
FOVU 360#
FRDLNK 124#
FSELNK 123#
FXU 360# 5437 5441 5454 5463
HYPEN 559#
IADBRK 360#
IADEXC 360#
IADSTP 360#
IADUSR 360#
IAPRC1 360#
IAPRE1 360#
IASRTC 360#
IASRTE 360#
IASRTS 360#
ICNSLL 360#
ICNSLR 360#
IDATAF 360#
IEVNPR 360#
IFMMAN 360#
IINSTF 360#
IIOPFC 360#
IIOPFL 360#
IMAINT 360#
IMGINM 360#
IMGNLO 360#
IMGNOF 360#
IMGNON 360#
IMIPGD 360# SEQ 0168
IMLAPD 360#
INHCSH 109#
INHPAG 106#
INXCLR 360#
INXM 360#
INXSTP 360#
IOCLR 360#
IP50HZ 360#
IPAREN 360#
IPARER 360#
IPRSTP 360#
IPWRFL 360#
IPWRLO 360#
IRQCLR 360#
ISPDOF 360#
ISPDON 360#
ITERAT 65# 406
ITMDIS 360#
ITMENB 360#
ITMOEN 360#
ITMOUT 360#
ITMSET 360#
ITRCH1 466#
ITRCNT 406# 782 803 807 815 816 820
IWRITE 360#
JOB41 360#
JOBAPR 360#
JOBCNI 360#
JOBDDT 360#
JOBFF 360#
JOBOPC 360#
JOBREL 360#
JOBREN 360#
JOBSA 360#
JOBSYM 360#
JOBTPC 360#
JOBUSY 360#
JOBUUO 360#
JOBVER 360#
KA10 360
KAHZ50 114#
KAIFLG 423#
KI10 33# 360
KL10 34# 360
KL10P0 360
KL10PO 35#
KLFLG 424# 783 794 813
KLOLD 322
KNTRP 360#
KTRP 360#
LAPRAL 360#
LAPRP1 360#
LAPRP2 360# SEQ 0169
LAPRP3 360#
LAPRP4 360#
LAPRP5 360#
LAPRP6 360#
LAPRP7 360#
LAROVT 360#
LCASDE 360#
LCASLD 360#
LCASLO 360#
LCASWB 360#
LCASWD 360#
LCCASD 360#
LCHNOF 360#
LCHNON 360#
LCIOPF 360#
LCNTRP 360#
LCNXER 360#
LCPAER 360#
LCPWRF 360#
LCSBER 360#
LCSLOA 360#
LCSLOO 360#
LCTRP 360#
LCWSX 360#
LDATAF 360#
LDCASD 360#
LDEXCB 360#
LDIOPF 360#
LDLNK 125# 376 378
LDNXER 360#
LDPAER 360#
LDPWRF 360#
LDSBER 360#
LDUSRB 360#
LECASD 360#
LEIOPF 360#
LENXER 360#
LEPAER 360#
LEPWRF 360#
LESBER 360#
LEUPFW 360#
LEVNCD 360#
LEVNPA 360#
LEVNPD 360#
LEXCMP 360#
LFLGCL 360#
LFLGDS 360#
LFLGEN 360#
LFLGST 360#
LFP 563#
LINSTF 360#
LINT 360#
LIOCLR 360# SEQ 0170
LIOPFE 360#
LIP 360#
LKNTRP 360#
LKTRP 360#
LLACBL 360#
LLDUSB 360#
LLPRCN 360#
LMUUO 360#
LMUUOP 360#
LNXMEN 360#
LNXMER 360#
LOOPER 100#
LPAREN 360#
LPARER 360#
LPDOVT 360#
LPFWPC 360#
LPGFTR 360#
LPICH1 360#
LPICH2 360#
LPICH3 360#
LPICH4 360#
LPICH5 360#
LPICH6 360#
LPICH7 360#
LPICHA 360#
LPICLR 360#
LPIIP1 360#
LPIIP2 360#
LPIIP3 360#
LPIIP4 360#
LPIIP5 360#
LPIIP6 360#
LPIIP7 360#
LPIOFF 360#
LPION 360#
LPNTRP 360#
LPRCH1 360#
LPRCH2 360#
LPRCH3 360#
LPRCH4 360#
LPRCH5 360#
LPRCH6 360#
LPRCH7 360#
LPTRP 360#
LPWRFE 360#
LPWRFL 360#
LREQSE 360#
LRQCLR 360#
LSBSEN 360#
LSBUSE 360#
LSCASD 360#
LSECMO 360#
LSIOPF 360# SEQ 0171
LSMODE 360#
LSNTRP 360#
LSNXER 360#
LSPAER 360#
LSPWRF 360#
LSSBER 360#
LSTRP 360#
LTRP3T 360#
LTRPAE 360#
LTRPEN 360#
LUSCMP 360#
LUUO 360#
LUUO1 493 494
LUUO10 493 498
LUUO11 493 498
LUUO12 493 499
LUUO13 493 499
LUUO14 493 500
LUUO15 493 500
LUUO16 493 501
LUUO17 493 501
LUUO2 493 495
LUUO20 493 502
LUUO21 493 502
LUUO22 493 503
LUUO23 493 503
LUUO24 493 504
LUUO25 493 504
LUUO26 493 505
LUUO27 493 505
LUUO3 493 495
LUUO30 493 506
LUUO31 493 506
LUUO32 493 507
LUUO33 493 507
LUUO4 493 496
LUUO5 493 496
LUUO6 493 497
LUUO7 493 497
LUUOI 360#
LWRITE 360#
MAPNEW 514#
MARGIN 436#
MCNVER 3# 10 24 408
MEMLOW 516#
MEMMAP 38# 414
MEMSIZ 517#
MEMTOT 515#
MINUS 558#
MODDVC 108#
MODDVL 307 307# 409
MODDVU 308 308# 410
MODLNK 127# 373 SEQ 0172
MONCTL 426# 823 850
MONFLG 425# 776
MONTEN 427# 781 809 835
MONTYP 640#
MPVU 360#
MUUO 360#
MUUOPC 360#
NOPNT 96#
NXMU 360#
OPRSEL 110#
OPTIME 528#
P 153 154 155 156 360# 448
PAG 360#
PALERS 102#
PARCLR 360#
PARDIS 360#
PAREA0 58#
PAREA1 59# 404
PAREA2 60# 405
PAREA3 61# 402
PAREA4 62# 403
PAREA5 63# 415
PAREA6 64# 416
PAREA7 415#
PAREA8 416#
PARENB 360#
PARU 360#
PASCNT 430# 802
PATCH 6426#
PDISF 525#
PDLOVU 360#
PDOVTP 360#
PERIOD 555#
PFSTRT 382#
PGFTRP 360#
PGMEND 36# 6432
PGMNAM 407 851 854#
PI 815
PICHN1 360#
PICHN2 360#
PICHN3 360#
PICHN4 360#
PICHN5 360#
PICHN6 360#
PICHN7 360#
PICHNA 360#
PICLR 360#
PIOFF 360#
PION 360#
PLIST 594# 594
PLISTE 594 596#
PLISTS 595#
PLUS 560# SEQ 0173
PNTENB 524#
PNTEXT 403#
PNTFLG 523#
PNTINH 526#
PNTLPT 97#
PNTNAM 402#
PNTRP 360#
PNTSPC 527#
PTRP 360#
PVPAGI 621#
PWFCLR 360#
QUEST 566#
RADIX 569#
RADLSC 571#
RADLSP 570#
RANDBS 404#
REENTR 384#
RELIAB 104#
REPT 360#
REPT1 360#
REPTU 482#
REQSET 360#
RESRT1 459#
RESRT2 460#
RETURN 391# 811 818 836
RSTART 93#
RTP 564#
RUNFLG 431#
SADR1 43# 380
SADR10 52# 396
SADR11 53# 397
SADR2 44# 382
SADR3 45# 384
SADR4 46#
SADR5 47# 445
SADR6 48# 446
SADR7 49# 393
SADR8 50# 394
SADR9 51# 395
SBINIT 166 390#
SCOPE 483#
SENSE1 360#
SENSE2 360#
SENSE3 360#
SENSE4 360#
SENSE5 360#
SENSE6 360#
SFSTRT 380#
SLASH 567#
SM10 671#
SMLUSR 360#
SN 933# 999 999# 1015 1015# 1031 1031# 1047 1047# 1063 1063# 1079 1079# 1095
1095# 1111 1111# 1127 1127# 1143 1143# 1159 1159# 1175 1175# 1191 1191# 1207 SEQ 0174
1207# 1223 1223# 1239 1239# 1249# 1332 1332# 1349 1349# 1366 1366# 1383 1383#
1400 1400# 1417 1417# 1434 1434# 1451 1451# 1468 1468# 1485 1485# 1502 1502#
1519 1519# 1536 1536# 1553 1553# 1570 1570# 1580# 1603 1603# 1619 1619# 1635
1635# 1651 1651# 1667 1667# 1683 1683# 1699 1699# 1715 1715# 1731 1731# 1747
1747# 1763 1763# 1779 1779# 1795 1795# 1811 1811# 1827 1827# 1837# 1863 1863#
1881 1881# 1899 1899# 1917 1917# 1935 1935# 1953 1953# 1971 1971# 1989 1989#
2007 2007# 2025 2025# 2043 2043# 2061 2061# 2079 2079# 2097 2097# 2115 2115#
2148# 2179 2179# 2201 2201# 2223 2223# 2245 2245# 2267 2267# 2289 2289# 2311
2311# 2333 2333# 2355 2355# 2377 2377# 2399 2399# 2421 2421# 2443 2443# 2465
2465# 2487 2487# 2509 2509# 2531 2531# 2553 2553# 2567# 2598 2598# 2620 2620#
2642 2642# 2664 2664# 2686 2686# 2708 2708# 2730 2730# 2752 2752# 2774 2774#
2796 2796# 2818 2818# 2840 2840# 2862 2862# 2884 2884# 2906 2906# 2928 2928#
2950 2950# 2972 2972# 3004# 3035 3035# 3057 3057# 3079 3079# 3101 3101# 3123
3123# 3145 3145# 3167 3167# 3189 3189# 3211 3211# 3233 3233# 3255 3255# 3277
3277# 3299 3299# 3321 3321# 3343 3343# 3365 3365# 3387 3387# 3409 3409# 3423#
3454 3454# 3476 3476# 3498 3498# 3520 3520# 3542 3542# 3564 3564# 3586 3586#
3608 3608# 3630 3630# 3652 3652# 3674 3674# 3696 3696# 3718 3718# 3740 3740#
3762 3762# 3784 3784# 3806 3806# 3828 3828# 3844# 3865 3865# 3877 3877# 3889
3889# 3901 3901# 3913 3913# 3925 3925# 3937 3937# 3949 3949# 3961 3961# 3973
3973# 3985 3985# 3997 3997# 4009 4009# 4021 4021# 4033 4033# 4046# 4066 4066#
4078 4078# 4090 4090# 4102 4102# 4114 4114# 4126 4126# 4138 4138# 4150 4150#
4162 4162# 4174 4174# 4186 4186# 4198 4198# 4210 4210# 4222 4222# 4234 4234#
SNTRP 360#
SPACE 556#
SRTDDT 386#
START 374 779 787 795 799 847#
START1 393#
START2 394#
START3 395#
START4 396#
START5 397#
STARTA 389 797 808 817 824 831 848 852 873#
STRP 360#
SUBLNK 128# 390
SWPTAB 677#
SWTEXR 405#
SYSEXR 378#
TAB 557#
TESTPC 432#
TICKS 435#
TN0 360#
TN1 360#
TNUMB 6339# 6339
TOTALS 94#
TRP3TP 360#
TRPENB 360#
TTNBRF 615#
TTYFIL 531#
TTYSPD 532#
TXTINH 105#
UOLIP 360#
UOUSR 360#
USER 422# 772 775 777 778 804 847 SEQ 0175
USERF 360# 774
USRASB 32# 412
USRCMP 360#
USRCRF 541#
USRLFF 540#
USRPFW 360#
UUODIS 494#
UUOEXT 450#
UUORTN 451#
UUOSKP 448#
XX 3846# 3867 3867# 3868 3870 3879 3879# 3880 3882 3891 3891# 3892 3894 3903
3903# 3904 3906 3915 3915# 3916 3918 3927 3927# 3928 3930 3939 3939# 3940
3942 3951 3951# 3952 3954 3963 3963# 3964 3966 3975 3975# 3976 3978 3987
3987# 3988 3990 3999 3999# 4000 4002 4011 4011# 4012 4014 4023 4023# 4024
4026 4035 4035# 4036 4038 4048# 4068 4068# 4069 4070 4080 4080# 4081 4082
4092 4092# 4093 4094 4104 4104# 4105 4106 4116 4116# 4117 4118 4128 4128#
4129 4130 4140 4140# 4141 4142 4152 4152# 4153 4154 4164 4164# 4165 4166
4176 4176# 4177 4178 4188 4188# 4189 4190 4200 4200# 4201 4202 4212 4212#
4213 4214 4224 4224# 4225 4226 4236 4236# 4237 4238
ZZ 934# 944 944# 945 946 946# 947 948 948# 949 950 950# 951 952
952# 953 954 954# 955 956 956# 957 958 958# 959 960 960# 961
962 962# 963 964 964# 965 966 966# 967 968 968# 969 970 970#
971 972 972# 973 974 974# 975 977# 1000 1000# 1001 1016 1016# 1017
1032 1032# 1033 1048 1048# 1049 1064 1064# 1065 1080 1080# 1081 1096 1096#
1097 1112 1112# 1113 1128 1128# 1129 1144 1144# 1145 1160 1160# 1161 1176
1176# 1177 1192 1192# 1193 1208 1208# 1209 1224 1224# 1225 1240 1240# 1241
1250# 1262 1262# 1263 1264 1265 1265# 1266 1267 1268 1268# 1269 1270 1271
1271# 1272 1273 1274 1274# 1275 1276 1277 1277# 1278 1279 1280 1280# 1281
1282 1283 1283# 1284 1285 1286 1286# 1287 1288 1289 1289# 1290 1291 1292
1292# 1293 1294 1295 1295# 1296 1297 1298 1298# 1299 1300 1301 1301# 1302
1303 1304 1304# 1305 1306 1308# 1333 1333# 1334 1350 1350# 1351 1367 1367#
1368 1384 1384# 1385 1401 1401# 1402 1418 1418# 1419 1435 1435# 1436 1452
1452# 1453 1469 1469# 1470 1486 1486# 1487 1503 1503# 1504 1520 1520# 1521
1537 1537# 1538 1554 1554# 1555 1571 1571# 1572 1581# 1604 1604# 1605 1606
1620 1620# 1621 1622 1636 1636# 1637 1638 1652 1652# 1653 1654 1668 1668#
1669 1670 1684 1684# 1685 1686 1700 1700# 1701 1702 1716 1716# 1717 1718
1732 1732# 1733 1734 1748 1748# 1749 1750 1764 1764# 1765 1766 1780 1780#
1781 1782 1796 1796# 1797 1798 1812 1812# 1813 1814 1828 1828# 1829 1830
1838# 1864 1864# 1865 1866 1867 1882 1882# 1883 1884 1885 1900 1900# 1901
1902 1903 1918 1918# 1919 1920 1921 1936 1936# 1937 1938 1939 1954 1954#
1955 1956 1957 1972 1972# 1973 1974 1975 1990 1990# 1991 1992 1993 2008
2008# 2009 2010 2011 2026 2026# 2027 2028 2029 2044 2044# 2045 2046 2047
2062 2062# 2063 2064 2065 2080 2080# 2081 2082 2083 2098 2098# 2099 2100
2101 2116 2116# 2117 2118 2119 2149# 2180 2180# 2181 2181# 2183 2186 2202
2202# 2203 2205 2208 2224 2224# 2225 2227 2230 2246 2246# 2247 2249 2252
2268 2268# 2269 2271 2274 2290 2290# 2291 2293 2296 2312 2312# 2313 2315
2318 2334 2334# 2335 2337 2340 2356 2356# 2357 2359 2362 2378 2378# 2379
2381 2384 2400 2400# 2401 2403 2406 2422 2422# 2423 2425 2428 2444 2444#
2445 2447 2450 2466 2466# 2467 2469 2472 2488 2488# 2489 2491 2494 2510
2510# 2511 2513 2516 2532 2532# 2533 2535 2538 2554 2554# 2555 2557 2560
2568# 2599 2599# 2600 2600# 2602 2605 2621 2621# 2622 2624 2627 2643 2643#
2644 2646 2649 2665 2665# 2666 2668 2671 2687 2687# 2688 2690 2693 2709
2709# 2710 2712 2715 2731 2731# 2732 2734 2737 2753 2753# 2754 2756 2759 SEQ 0176
2775 2775# 2776 2778 2781 2797 2797# 2798 2800 2803 2819 2819# 2820 2822
2825 2841 2841# 2842 2844 2847 2863 2863# 2864 2866 2869 2885 2885# 2886
2888 2891 2907 2907# 2908 2910 2913 2929 2929# 2930 2932 2935 2951 2951#
2952 2954 2957 2973 2973# 2974 2976 2979 3005# 3036 3036# 3037 3037# 3039
3042 3058 3058# 3059 3061 3064 3080 3080# 3081 3083 3086 3102 3102# 3103
3105 3108 3124 3124# 3125 3127 3130 3146 3146# 3147 3149 3152 3168 3168#
3169 3171 3174 3190 3190# 3191 3193 3196 3212 3212# 3213 3215 3218 3234
3234# 3235 3237 3240 3256 3256# 3257 3259 3262 3278 3278# 3279 3281 3284
3300 3300# 3301 3303 3306 3322 3322# 3323 3325 3328 3344 3344# 3345 3347
3350 3366 3366# 3367 3369 3372 3388 3388# 3389 3391 3394 3410 3410# 3411
3413 3416 3424# 3455 3455# 3456 3456# 3458 3461 3477 3477# 3478 3480 3483
3499 3499# 3500 3502 3505 3521 3521# 3522 3524 3527 3543 3543# 3544 3546
3549 3565 3565# 3566 3568 3571 3587 3587# 3588 3590 3593 3609 3609# 3610
3612 3615 3631 3631# 3632 3634 3637 3653 3653# 3654 3656 3659 3675 3675#
3676 3678 3681 3697 3697# 3698 3700 3703 3719 3719# 3720 3722 3725 3741
3741# 3742 3744 3747 3763 3763# 3764 3766 3769 3785 3785# 3786 3788 3791
3807 3807# 3808 3810 3813 3829 3829# 3830 3832 3835 3845# 3866 3866# 3868
3869 3870 3878 3878# 3880 3881 3882 3890 3890# 3892 3893 3894 3902 3902#
3904 3905 3906 3914 3914# 3916 3917 3918 3926 3926# 3928 3929 3930 3938
3938# 3940 3941 3942 3950 3950# 3952 3953 3954 3962 3962# 3964 3965 3966
3974 3974# 3976 3977 3978 3986 3986# 3988 3989 3990 3998 3998# 4000 4001
4002 4010 4010# 4012 4013 4014 4022 4022# 4024 4025 4026 4034 4034# 4036
4037 4038 4047# 4067 4067# 4069 4070 4071 4079 4079# 4081 4082 4083 4091
4091# 4093 4094 4095 4103 4103# 4105 4106 4107 4115 4115# 4117 4118 4119
4127 4127# 4129 4130 4131 4139 4139# 4141 4142 4143 4151 4151# 4153 4154
4155 4163 4163# 4165 4166 4167 4175 4175# 4177 4178 4179 4187 4187# 4189
4190 4191 4199 4199# 4201 4202 4203 4211 4211# 4213 4214 4215 4223 4223#
4225 4226 4227 4235 4235# 4237 4238 4239
$$420 746#
$$421 747#
$$422 748#
$$423 749#
$$424 750#
$$425 751#
$$426 752#
$$427 753#
$$430 754#
$$431 755#
$$432 756#
$$433 757#
$$434 758#
$$435 759#
$$436 760#
$$437 761#
$$500 764#
$$501 765#
$$502 766#
$$503 767#
$$BEGI 732#
$$DTE0 792 828#
$$DTE2 793 841#
$$LOC 729# 768
$$MUUO 646# SEQ 0177
$$OUTE 652#
$$STAR 732 733 772#
$$TAX1 664#
$$TAX2 665#
$$TOGG 658#
$$UUO 635#
$ACC0 473#
$BEGEN 741#
$BEND1 443#
$BEND2 444#
$CHRIN 534#
$CRLF 536#
$DDT 710#
$DEVCH 360#
$DSKUP 413#
$DTCHR 722#
$DTCI 716#
$DTCLK 715# 790
$DTCMD 719# 826 839
$DTF11 718#
$DTFLG 714# 789 827 829 840 842
$DTMTD 723#
$DTMTI 724#
$DTOPR 721# 791
$DTSEQ 720#
$DTSWR 726#
$DTT11 717#
$DVCH1 360#
$DVOFF 530#
$EMODE 411#
$FFF 538#
$IBUF 586#
$INEXT 588#
$INNM 587#
$ITRHL 454#
$ITRX1 455#
$LPAPE 6346
$MMAP 414#
$MODVL 409#
$MODVU 410#
$OBUF 577#
$ONETM 437#
$OUTEX 579#
$OUTNM 578#
$PAPER 360
$PARER 461#
$PNAME 407#
$PSHER 465#
$PVER 408#
$RSRTX 457#
$RSRTY 458#
$SPAG1 477#
$SPB1 798 804# SEQ 0178
$SPBEN 741 802#
$SPBEX 805 813#
$SPBKL 814 820#
$SPBUS 807#
$SPEC 738 797#
$SPKLD 821 835#
$START 374#
$STD 709# 736#
$STKIL 781#
$STKL 789#
$STL 711#
$STM 712# 738#
$SVAPR 475#
$SVPAG 476#
$SVPI 474#
$SVUPC 480#
$SVUUO 479#
$TABF 537#
$TTCHR 533#
$TWCNT 529#
$TYPNB 535#
$UMODE 412#
$UORTX 452#
$USRHL 456#
$UUOER 453# 494
$VTF 539#
%ACTFL 486#
%ACTUL 487#
%COREC 485#
%CORFL 484#
%DISCR 488#
%ERHI1 627#
%ERHI2 628#
%ERHI3 629#
.JB41 360#
.JBAPR 360#
.JBCNI 360#
.JBDDT 360#
.JBFF 360#
.JBOPC 360#
.JBREL 360#
.JBREN 360#
.JBSA 360#
.JBSYM 360#
.JBTPC 360#
.JBUSY 360#
.JBUUO 360#
.JBVER 360#
CFLUSH 278#
CINVAL 277# SEQ 0179
CLOKOP 272#
CWRTBI 279#
DROPDV 239#
ENDUUO 285# 442
EOPUUO 286# 444
ERLOOP 330#
ERLP1 331#
ERLP2 332#
ERRHLT 173#
ERROR 339#
ERROR1 350#
ERUUO 329#
EXIT 810
FATAL 172#
FRD36 314#
FRD8 315#
FREAD 313#
FSELEC 312#
GET 156#
GO 153#
HALT 158# 463 746 748 749 753 767 844 891 904 916 929 1003 1019
1035 1051 1067 1083 1099 1115 1131 1147 1163 1179 1195 1211 1227 1243
1336 1353 1370 1387 1404 1421 1438 1455 1472 1489 1506 1523 1540 1557
1574 1608 1624 1640 1656 1672 1688 1704 1720 1736 1752 1768 1784 1800
1816 1832 1869 1887 1905 1923 1941 1959 1977 1995 2013 2031 2049 2067
2085 2103 2121 2143 2188 2210 2232 2254 2276 2298 2320 2342 2364 2386
2408 2430 2452 2474 2496 2518 2540 2562 2607 2629 2651 2673 2695 2717
2739 2761 2783 2805 2827 2849 2871 2893 2915 2937 2959 2981 2999 3044
3066 3088 3110 3132 3154 3176 3198 3220 3242 3264 3286 3308 3330 3352
3374 3396 3418 3463 3485 3507 3529 3551 3573 3595 3617 3639 3661 3683
3705 3727 3749 3771 3793 3815 3837 3872 3884 3896 3908 3920 3932 3944
3956 3968 3980 3992 4004 4016 4028 4040 4073 4085 4097 4109 4121 4133
4145 4157 4169 4181 4193 4205 4217 4229 4241 4258 4271 4285 4289 4304
4308 4329 4352 4356 4369 4373 4384 4388 4404 4419 4435 4448 4462 4476
4491 4505 4520 4533 4547 4561 4576 4590 4605 4620 4635 4652 4670 4687
4700 4714 4732 4747 4765 4786 4807 4825 4842 4860 4876 4898 4919 4937
4956 4970 4985 5005 5024 5044 5063 5082 5093 5105 5121 5134 5146 5158
5169 5182 5196 5211 5215 5220 5225 5240 5254 5258 5263 5268 5282 5286
5291 5296 5312 5325 5337 5350 5364 5368 5373 5378 5391 5395 5400 5405
5426 5443 5465 5482 5504 5519 5532 5544 5555 5568 5581 5592 5605 5621
5634 5647 5659 5672 5718 5732 5736 5741 5746 5759 5763 5768 5773 5789
5802 5814 5827 5842 5846 5859 5872 5886 5898 5913 5926 5940 5952 5966
5978 5994 6011 6025 6040 6053 6063 6081 6098 6114 6132 6149 6164 6179
6239 6253 6266 6279 6292 6306 6319 6333
JEN 160#
JRSTF 159#
MAPADR 295#
MAPCNK 296#
MAPMEM 292#
MAPPNT 298#
MAPSET 297#
MEMSEG 294#
MEMZRO 293# SEQ 0180
MODPCP 305#
MODPCU 304#
MTROP 273#
NAME 7# 10
PBELL 248#
PCRL 242#
PCRL2 246#
PCRL2F 247#
PCRLF 243#
PFORCE 250#
PGMINT 166#
PJRST 157#
PMSG 252#
PMSGF 255#
PNT1 208#
PNT11 222#
PNT11F 223#
PNT1F 209#
PNT2 210#
PNT2F 211#
PNT3 212#
PNT3F 213#
PNT4 214#
PNT4F 215#
PNT5 216#
PNT5F 217#
PNT6 218#
PNT6F 219#
PNT7 220#
PNT7F 221#
PNTA 194#
PNTADF 225#
PNTADR 224#
PNTAF 195#
PNTAL 196#
PNTALF 197#
PNTCHF 207#
PNTCHR 206#
PNTCI 204#
PNTCIF 205#
PNTCW 240#
PNTCWF 241#
PNTDCF 233#
PNTDEC 232#
PNTDS 234#
PNTDSF 235#
PNTHW 228#
PNTHWF 229#
PNTMGN 319#
PNTMSF 201#
PNTMSG 200#
PNTNM 236#
PNTOCF 231# SEQ 0181
PNTOCS 230#
PNTOCT 226#
PNTOTF 227#
PNTSIX 237#
PNTSXF 238#
PSIXL 198#
PSIXLF 199#
PSIXM 202#
PSIXMF 203#
PSP 244#
PSPF 245#
PUT 155#
REPTUO 333#
RTN 154# 450
S 84#
SFLAG 78# 4758 4778 4799 4818 4835 4853 4868 4888 4909 4997 5016 5036 5055
5074 5417 5435 5452 5457 5474 5491 5496
SIXBTZ 261#
STOP 72# 890 903 915 928 1002 1018 1034 1050 1066 1082 1098 1114 1130
1146 1162 1178 1194 1210 1226 1242 1335 1352 1369 1386 1403 1420 1437
1454 1471 1488 1505 1522 1539 1556 1573 1607 1623 1639 1655 1671 1687
1703 1719 1735 1751 1767 1783 1799 1815 1831 1868 1886 1904 1922 1940
1958 1976 1994 2012 2030 2048 2066 2084 2102 2120 2142 2187 2209 2231
2253 2275 2297 2319 2341 2363 2385 2407 2429 2451 2473 2495 2517 2539
2561 2606 2628 2650 2672 2694 2716 2738 2760 2782 2804 2826 2848 2870
2892 2914 2936 2958 2980 2998 3043 3065 3087 3109 3131 3153 3175 3197
3219 3241 3263 3285 3307 3329 3351 3373 3395 3417 3462 3484 3506 3528
3550 3572 3594 3616 3638 3660 3682 3704 3726 3748 3770 3792 3814 3836
3871 3883 3895 3907 3919 3931 3943 3955 3967 3979 3991 4003 4015 4027
4039 4072 4084 4096 4108 4120 4132 4144 4156 4168 4180 4192 4204 4216
4228 4240 4257 4270 4284 4288 4303 4307 4328 4351 4355 4368 4372 4387
4403 4418 4434 4447 4461 4475 4490 4504 4519 4532 4546 4560 4575 4589
4604 4619 4634 4651 4669 4686 4699 4713 4731 4746 4764 4785 4806 4824
4841 4859 4875 4897 4918 4936 4954 4969 4984 5004 5023 5043 5062 5081
5092 5104 5120 5133 5145 5157 5168 5181 5195 5210 5214 5219 5224 5239
5253 5257 5262 5267 5281 5285 5290 5295 5311 5324 5336 5349 5363 5367
5372 5377 5390 5394 5399 5404 5425 5442 5464 5481 5503 5518 5531 5543
5554 5567 5580 5591 5604 5620 5633 5646 5658 5671 5717 5731 5735 5740
5745 5758 5762 5767 5772 5788 5801 5813 5826 5841 5845 5858 5871 5885
5897 5912 5925 5939 5951 5965 5977 5993 6010 6024 6039 6052 6062 6080
6097 6113 6131 6148 6163 6178 6238 6252 6265 6278 6291 6305 6318 6332
SWITCH 267#
TTALTM 188#
TTICHR 181#
TTICLR 191#
TTICNV 186#
TTIDEC 185#
TTINO 183#
TTIOCT 184#
TTIYES 182#
TTLOOK 187#
TTSIXB 189#
TTYINP 190# SEQ 0182