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klad.sources/msdpmd.xrf
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1 %TITLE 'STIRS FAULT ISOLATION DATA FOR M8621 (DPM) BOARD'
2
3 MODULE MSDPMD (
4 LANGUAGE(BLISS36)
5 ) =
6
7 BEGIN
8
9 !
10 ! COPYRIGHT (C) 1979 BY
11 ! DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASS.
12 !
13 ! THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COPIED
14 ! ONLY IN ACCORDANCE WITH THE TERMS OF SUCH LICENSE AND WITH THE
15 ! INCLUSION OF THE ABOVE COPYRIGHT NOTICE. THIS SOFTWARE OR ANY OTHER
16 ! COPIES THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY
17 ! OTHER PERSON. NO TITLE TO AND OWNERSHIP OF THE SOFTWARE IS HEREBY
18 ! TRANSFERRED.
19 !
20 ! THE INFORMATION IN THIS SOFTWARE IS SUBJECT TO CHANGE WITHOUT NOTICE
21 ! AND SHOULD NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL EQUIPMENT
22 ! CORPORATION.
23 !
24 ! DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE OR RELIABILITY OF ITS
25 ! SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL.
26 !
27
28 !++
29 ! FACILITY: DECSYSTEM 2020 DIAGNOSTIC RELEASE TAPE 'DSTIR'
30 !
31 ! ABSTRACT:
32 !
33 ! THIS MODULE CONTAINS THE FAULT ISOLATION DATA FOR THE KS10
34 ! STIMULUS/RESPONSE (STIRS) DIAGNOSTIC FOR THE M8621 (DPM) BOARD.
35 ! IT IS LINKED TO THE 'MSSTRC' AND 'MSDPMT' MODULES TO PRODUCE
36 ! THE 'MSDPM.EXE' FILE.
37 !
38 ! ENVIRONMENT: RUNS UNDER 'CSL' ON A TOPS-20 SYSTEM.
39 !
40 ! AUTHOR: ARON INSINGA , CREATION DATE: 01-SEP-78!
41 ! MODIFIED BY:
42 !
43 ! ARON INSINGA, 23-MAY-79; VERSION 0.1
44 !--
45 !
46 ! EQUATED SYMBOLS:
47 !
48
49 GLOBAL LITERAL
50 DATA_VERSION = 1,
51 DATA_EDIT = 0;
52
53 COMPILETIME
54 ALLOC_B = 35, ! PDP-11 STYLE BIT # IN WORD, READY TO OVERFLOW
55 ALLOC_W = -1, ! WORD #, SO WE WILL START WITH 0 AFTER OVERFLOW
56 ALLOC_N = 0, ! NUMBER OF THINGS ALLOCATED
57 ALLOC_N_1 = 0, ! (ALLOC_N - 1) TEMPORARY
58 ALLOC_W_1 = 0, ! (ALLOC_W + 1) TEMPORARY
59 ALLOC_B_1 = 0; ! (35 - ALLOC_B) TEMPORARY
60
61 !
62 ! MACROS:
63 !
64
65 MACRO
66 ALLOC(ALLOC_NAME,ALLOC_SLIT) = ! ALLOCATE FAULT ANALYSIS BITS
67 %ASSIGN(ALLOC_B,ALLOC_B + 1)
68 %IF ALLOC_B EQL 36
69 %THEN
70 %ASSIGN(ALLOC_B,0)
71 %ASSIGN(ALLOC_W,ALLOC_W + 1)
72 COMPILETIME
73 %NAME(W_,%NUMBER(ALLOC_W)) = 0;
74 %FI
75 ! PRINT THE WORD # AND PDP-10 BIT # INTO THE LISTING
76 %ASSIGN(ALLOC_B_1,35 - ALLOC_B)
77 %PRINT(%NUMBER(ALLOC_W),',',%NUMBER(ALLOC_B_1))
78 MACRO
79 ALLOC_NAME =
80 %QUOTE %ASSIGN
81 (
82 %QUOTE %EXPAND %NAME(W_,%NUMBER(ALLOC_W)),
83 %QUOTE %EXPAND %NAME(W_,%NUMBER(ALLOC_W)) OR
84 (1 ^ %QUOTE %EXPAND %NUMBER(ALLOC_B))
85 )
86 %QUOTE % ;
87 BIND
88 %NAME(N_,%NUMBER(ALLOC_N)) =
89 %IF %NULL(ALLOC_SLIT)
90 %THEN
91 %ASSIGN(ALLOC_N_1,ALLOC_N - 1)
92 %NAME(N_,%NUMBER(ALLOC_N_1))
93 %ELSE
94 UPLIT(%ASCIZ ALLOC_SLIT)
95 %FI ;
96 %ASSIGN(ALLOC_N,ALLOC_N + 1)
97 %,
98 DUMP(X,N)[] = ! X0, ... XN
99 %IF %COUNT GEQ N %THEN %EXITMACRO %FI
100 %IF %COUNT NEQ 0 %THEN , %FI
101 %NAME(X,%NUMBER(%COUNT))
102 DUMP(X,N)
103 %,
104 DUMP_ASSIGN(N)[] = ! %ASSIGN(X0,0) ... %ASSIGN(XN,0)
105 %IF %COUNT GEQ N %THEN %EXITMACRO %FI
106 %QUOTE %ASSIGN (%NAME(W_,%NUMBER(%COUNT)),0)
107 DUMP_ASSIGN(N)
108 %;
109
110 ! DPM 1
111 ALLOC(DBM_SEL_SCAD,'DPM1: DBM MUX SELECT')
112 ALLOC(DBM_SEL_PF)
113 ALLOC(DBM_SEL_APR)
114 ALLOC(DBM_SEL_APR_EN)
115 ALLOC(DBM_SEL_BYTES)
116 ALLOC(DBM_SEL_BYTES35)
117 ALLOC(DBM_SEL_EXP)
118 ALLOC(DBM_SEL_MSEC)
119 ALLOC(DBM_SEL_DP)
120 ALLOC(DBM_SEL_DP_SWAP)
121 ALLOC(DBM_SEL_VMA)
122 ALLOC(DBM_SEL_MEM)
123 ALLOC(DBM_SEL_N)
124
125 ! DPM 1,2
126 ALLOC(DBM_SCAD,'DPM1,2: DBM MUX')
127 ALLOC(DBM_PF)
128 ALLOC(DBM_APR)
129 ALLOC(DBM_APR_EN)
130 ALLOC(DBM_BYTES)
131 ALLOC(DBM_BYTES35)
132 ALLOC(DBM_EXP)
133 ALLOC(DBM_MSEC)
134 ALLOC(DBM_DP)
135 ALLOC(DBM_DP_SWAP)
136 ALLOC(DBM_VMA)
137 ALLOC(DBM_VMA_MEM)
138 ALLOC(DBM_MEM)
139 ALLOC(DBM_N)
140
141 ! DPM 3
142 ALLOC(SCADA_SC,'DPM3: SCAD A MUX')
143 ALLOC(SCADA_SN)
144 ALLOC(SCADA_44)
145 ALLOC(SCADA_BYTE1)
146 ALLOC(SCADA_BYTE2)
147 ALLOC(SCADA_BYTE3)
148 ALLOC(SCADA_BYTE4)
149 ALLOC(SCADA_BYTE5)
150 ALLOC(SCADA_SEL_SC,'DPM3: SCAD A MUX SELECT')
151 ALLOC(SCADA_SEL_SN)
152 ALLOC(SCADA_SEL_44)
153 ALLOC(SCADA_SEL_BYTE1)
154 ALLOC(SCADA_SEL_BYTE2)
155 ALLOC(SCADA_SEL_BYTE3)
156 ALLOC(SCADA_SEL_BYTE4)
157 ALLOC(SCADA_SEL_BYTE5)
158 ALLOC(SCADB_FE,'DPM3: SCAD B MUX')
159 ALLOC(SCADB_EXP)
160 ALLOC(SCADB_SHIFT)
161 ALLOC(SCADB_SIZE)
162 ALLOC(SCADB_SEL_FE,'DPM3: SCAD B MUX SELECT')
163 ALLOC(SCADB_SEL_EXP)
164 ALLOC(SCADB_SEL_SHIFT)
165 ALLOC(SCADB_SEL_SIZE)
166
167 ! DPM 3,4
168 ALLOC(SCAD_A_MUL2,'DPB3,4: SCAD')
169 ALLOC(SCAD_OR)
170 ALLOC(SCAD_SUBB)
171 ALLOC(SCAD_SUB)
172 ALLOC(SCAD_ADD)
173 ALLOC(SCAD_AND)
174 ALLOC(SCAD_A_DEC)
175 ALLOC(SCAD_A)
176
177 ! DPM 4
178 ALLOC(VMA_USER_DP,'DPM4: VMA USER')
179 ALLOC(VMA_USER_N)
180 ALLOC(VMA_PREV_DP,'DPM4: VMA PREVIOUS')
181 ALLOC(VMA_PREV_N)
182 ALLOC(VMA_PHYS_DP,'DPM4: VMA PHYSICAL')
183 ALLOC(VMA_PHYS_N)
184 ALLOC(VMA_FETCH_DP,'DPM4: VMA FETCH')
185 ALLOC(VMA_FETCH_N)
186 ALLOC(VMA_CYCLE_DP,'DPM4: VMA CYCLE')
187 ALLOC(VMA_CYCLE_N)
188 ALLOC(VMA_SWEEP,'DPM4: VMA SWEEP')
189 ALLOC(VMA_SWEEP_CD)
190 ALLOC(VMA_SWEEP_PT)
191 ALLOC(VMA,'DPM4: VMA REGISTER')
192 ALLOC(FE,'DPM4: FE REGISTER')
193 ALLOC(FE_EN,'DPM4: FE ENABLE')
194 ALLOC(FE_SIGN,'DPM4: FE SIGN')
195 ALLOC(SC,'DPM4: SC REGISTER')
196 ALLOC(SC_EN,'DPM4: SC ENABLE')
197 ALLOC(SC_SIGN,'DPM4: SC SIGN')
198 ALLOC(AC_REF,'DPM4: VMA IS AC')
199
200 ! DPM 5
201 ALLOC(MEM_READ_N,'DPM5: MEM READ')
202 ALLOC(MEM_READ_DP)
203 ALLOC(MEM_READ_DRO)
204 ALLOC(MEM_WRITE_N,'DPM5: MEM WRITE')
205 ALLOC(MEM_WRITE_DP)
206 ALLOC(MEM_WRITE_DRO)
207 ALLOC(MEM_WR_TEST_N,'DPM5: MEM WRITE TEST')
208 ALLOC(MEM_WR_TEST_DP)
209 ALLOC(MEM_WR_TEST_DRO)
210 ALLOC(MEM_CAC_INH_N,'DPM5: MEM CACHE INHIBIT')
211 ALLOC(MEM_CAC_INH_DP)
212 ALLOC(MEM_CAC_INH_DRO)
213 ALLOC(BUS_REQ,'DPM5: BUS REQUEST')
214 ALLOC(BUS_REQ_A)
215 ALLOC(CLK_APR,'DPM5: CLOCK APR')
216 ALLOC(MEM_DELAY,'DPM5: MEM DELAY')
217 ALLOC(VMA_EN,'DPM5: VMA EN')
218 ALLOC(MEM_EN,'DPM5: MEM EN')
219 ALLOC(SPEC,'DPM5: SPEC')
220 ALLOC(STOP,'DPM5: STOP MEM')
221 ALLOC(MEM_WAIT,'DPM5: MEM WAIT')
222 ALLOC(FORCE,'DPM5: FORCE RAMFILE')
223
224 ! DPM 5,6,C
225 ALLOC(BUS_CYCLE,'DPM5,6,C: BUS CYCLE CONTROL')
226
227 ! DPM 6
228 ALLOC(PT_ADR,'DPM6: PAGE TABLE')
229 ALLOC(PT_IO)
230 ALLOC(PT_VAL_WRT)
231 ALLOC(PT_USR)
232 ALLOC(PT_CAC)
233 ALLOC(PT_PAR)
234 ALLOC(PT_RAM_PAG_USR)
235 ALLOC(PT_RAM_VAL_WRT)
236 ALLOC(PT_RAM_CAC)
237 ALLOC(PT_RAM_PAR)
238 ALLOC(PF,'DPM6: PAGE FAIL')
239 ALLOC(PF_WT)
240 ALLOC(PF_NXM)
241 ALLOC(PF_BAD)
242 ALLOC(PF_OK)
243 ALLOC(PT_PAR_GEN,'DPM6: PT PARITY')
244 ALLOC(PAR_ERR,'DPM6: PARITY ERR')
245
246 ! DPM 7
247 ALLOC(CD_ADR,'DPM7: CACHE DIR')
248 ALLOC(CD_IO)
249 ALLOC(CD_VAL)
250 ALLOC(CD_CMP,'DPM7: CD COMPARATOR')
251 ALLOC(CD_HIT,'DPM7: CD HIT')
252 ALLOC(CD_PAR,'DPM7: CD PARITY')
253 ALLOC(CD_RAM_PAG_USR)
254 ALLOC(CD_RAM_VAL)
255 ALLOC(CD_RAM_PAR)
256
257 ! DPM 8,9
258 ALLOC(BUS_MUX_DP,'DPM8,9: DBM MUX')
259 ALLOC(BUS_MUX_VMA)
260 ALLOC(BUS_MUX_PAGE)
261 ALLOC(BUS_PAR,'DPM8,9: BUS PARITY')
262
263 ! DPM 8,9,C
264 ALLOC(BUS_T,'DPM8,9: BUS XCVR')
265 ALLOC(BUS_R);
266
267 ! DPM A
268 ALLOC(CLK,'DPMA: CLOCK')
269 ALLOC(RAM_CLK,'DPMA: RAM CLOCK')
270 ALLOC(BUS_CLK,'DPMA: BUS CLOCK')
271 ALLOC(BUS_XMIT,'DPMA: BUS XMIT')
272 ALLOC(RESET,'DPMA: RESET')
273 ALLOC(PXCT,'DPMA: PXCT')
274 ALLOC(PXCT_MUX,'DPMA: PXCT MUX')
275 ALLOC(PXCT_MUX_DPE)
276 ALLOC(SPEC_PREV,'DPMA: SPEC 10')
277 ALLOC(SPEC_APR)
278 ALLOC(SPEC_SWEEP)
279 ALLOC(SPEC_APR_EN)
280 ALLOC(SPEC_PXCT_OFF)
281 ALLOC(SPEC_MEMCLR)
282 ALLOC(SPEC_MEMCLR_NXM)
283 ALLOC(SPEC_MEMCLR_BAD)
284 ALLOC(SPEC_MSEC,'DPMA: SPEC 20')
285 ALLOC(SPEC_PAGE)
286 ALLOC(SPEC_PXCT_EN)
287
288 ! DPM A,C
289 ALLOC(PT_CLK,'DPMA,C: PT CLOCK')
290
291 ! DPM B
292 ALLOC(APR,'DPMB: APR FLAGS')
293 ALLOC(APR_EN,'DPMB: APR EN')
294 ALLOC(TRAP_EN,'DPMB: TRAP EN')
295 ALLOC(PAGE_EN,'DPMB: PAGE EN')
296
297 ! DPM C
298 ALLOC(BUS_TIMEOUT,'DPMC: BUS TIMEOUT')
299 ALLOC(BUS_NXM,'DPMC: NXM ERR')
300 ALLOC(BAD_DATA,'DPMC: BAD DATA')
301 ALLOC(MEM_CYCLE,'DPMC: MEM CYCLE')
302 ALLOC(IO_CYCLE,'DPMC: IO CYCLE')
303 ALLOC(MSEC,'DPMC: MSEC')
304 ALLOC(MSEC_FREQ,'DPMC: MSEC FREQUENCY')
305
306 ! COMBINATIONS
307
308 MACRO
309 BUS = BUS_T BUS_R %,
310 BUS_MUX = BUS_MUX_DP BUS_MUX_VMA BUS_MUX_PAGE %,
311 BUS_ALL = BUS BUS_REQ BUS_TIMEOUT BUS_CYCLE BUS_CLK BUS_XMIT BUS_NXM %,
312 VMA_ALL_DP = VMA_CYCLE_DP VMA_EN VMA VMA_PHYS_DP VMA_PREV_DP VMA_USER_DP %,
313 VMA_ALL_N = VMA_CYCLE_N VMA_EN VMA VMA_PHYS_N VMA_PREV_N VMA_USER_N N_ALL %,
314 N_ALL = DBM_N DBM_SEL_N %,
315 PT_MESS = SPEC_PAGE PF BUS_ALL MEM_EN BUS_REQ MEM_WRITE_N MEM_READ_N BUS_MUX_PAGE VMA_ALL_N %,
316 PF_CODE = PF DBM_PF DBM_SEL_PF %,
317 VMA_USER_PREV = VMA_USER_DP VMA_USER_N VMA_PREV_DP VMA_PREV_N %,
318 SPEC_PXCT = SPEC_PXCT_OFF SPEC_PXCT_EN %;
319
320 !
321 ! EQUATED SYMBOLS:
322 !
323
324 GLOBAL LITERAL
325 MAXNETS = ALLOC_N;
326
327 MACRO
328 NTWK =
329 %ASSIGN(ALLOC_W_1,ALLOC_W + 1)
330 DUMP(W_,%NUMBER(ALLOC_W_1))
331 DUMP_ASSIGN(%NUMBER(ALLOC_W_1))
332 %;
333
334 ! THIS MAKES A V E R Y LONG LISTING WITH EXPANSIONS
335 SWITCHES LIST(NOEXPAND);
336
337 GLOBAL BIND
338 NET_NAMES = PLIT
339 (
340 DUMP(N_,%NUMBER(ALLOC_N))
341 );
342
343 ! DOCUMENT WHAT JUST HAPPENED
344 %PRINT(%NUMBER(ALLOC_N))
345 %PRINT(%NUMBER(ALLOC_W))
346 %PRINT(%NUMBER(ALLOC_B))
347
348 BIND T1_E1 = UPLIT(DBM_N NTWK);
349 BIND T1_NE1 = UPLIT(DBM_N NTWK);
350 BIND T1_E2 = UPLIT(DBM_SEL_N NTWK);
351 BIND T1_NE2 = UPLIT(DBM_SEL_N NTWK);
352
353 BIND T1_ES = PLIT( T1_E1,
354 T1_E2);
355 BIND T1_NES = PLIT( T1_NE1,
356 T1_NE2);
357
358
359 BIND T2_E1 = UPLIT(DBM_DP_SWAP NTWK);
360 BIND T2_NE1 = UPLIT(DBM_DP_SWAP NTWK);
361 BIND T2_E2 = UPLIT(DBM_SEL_DP_SWAP NTWK);
362 BIND T2_NE2 = UPLIT(DBM_SEL_DP_SWAP NTWK);
363
364 BIND T2_ES = PLIT( T2_E1,
365 T2_E2);
366 BIND T2_NES = PLIT( T2_NE1,
367 T2_NE2);
368
369
370 BIND T3_E1 = UPLIT(DBM_DP NTWK);
371 BIND T3_NE1 = UPLIT(DBM_DP NTWK);
372 BIND T3_E2 = UPLIT(DBM_SEL_DP NTWK);
373 BIND T3_NE2 = UPLIT(DBM_SEL_DP NTWK);
374
375 BIND T3_ES = PLIT( T3_E1,
376 T3_E2);
377 BIND T3_NES = PLIT( T3_NE1,
378 T3_NE2);
379
380
381 BIND T4_E1 = UPLIT(SCAD_A SCADA_SN DBM_SCAD NTWK);
382 BIND T4_NE1 = UPLIT(SCAD_A SCADA_SN DBM_SCAD NTWK);
383 BIND T4_E2 = UPLIT(SCAD_A SCADA_SEL_SN DBM_SEL_SCAD NTWK);
384 BIND T4_NE2 = UPLIT(SCAD_A SCADA_SEL_SN DBM_SEL_SCAD NTWK);
385
386 BIND T4_ES = PLIT( T4_E1,
387 T4_E2);
388 BIND T4_NES = PLIT( T4_NE1,
389 T4_NE2);
390
391
392 BIND T5_E1 = UPLIT(SCAD_A_DEC SCADA_SN SCADA_SEL_SN DBM_SCAD DBM_SEL_SCAD NTWK);
393 BIND T5_NE1 = UPLIT(SCAD_A_DEC SCADA_SN SCADA_SEL_SN DBM_SCAD DBM_SEL_SCAD NTWK);
394
395 BIND T5_ES = PLIT( T5_E1);
396 BIND T5_NES = PLIT( T5_NE1);
397
398
399 BIND T6_E1 = UPLIT(SCAD_A_MUL2 SCADA_SN SCADA_SEL_SN DBM_SCAD DBM_SEL_SCAD NTWK);
400 BIND T6_NE1 = UPLIT(SCAD_A_MUL2 SCADA_SN SCADA_SEL_SN DBM_SCAD DBM_SEL_SCAD NTWK);
401
402 BIND T6_ES = PLIT( T6_E1);
403 BIND T6_NES = PLIT( T6_NE1);
404
405
406 BIND T7_E1 = UPLIT(SCAD_A SC SCADA_SC SCADA_SN DBM_SCAD NTWK);
407 BIND T7_NE1 = UPLIT(SCAD_A SC SCADA_SC SCADA_SN DBM_SCAD NTWK);
408 BIND T7_E2 = UPLIT(SCAD_A SC_EN SCADA_SEL_SC SCADA_SEL_SN DBM_SEL_SCAD NTWK);
409 BIND T7_NE2 = UPLIT(SCAD_A SC_EN SCADA_SEL_SC SCADA_SEL_SN DBM_SEL_SCAD NTWK);
410
411 BIND T7_ES = PLIT( T7_E1,
412 T7_E2);
413 BIND T7_NES = PLIT( T7_NE1,
414 T7_NE2);
415
416
417 BIND T8_E1 = UPLIT(SCAD_A SCADA_44 SC SCADA_SC SCADA_SN DBM_SCAD NTWK);
418 BIND T8_NE1 = UPLIT(SCAD_A SCADA_44 SC SCADA_SC SCADA_SN DBM_SCAD NTWK);
419 BIND T8_E2 = UPLIT(SCAD_A SCADA_SEL_44 SC_EN SCADA_SEL_SC SCADA_SEL_SN DBM_SEL_SCAD NTWK);
420 BIND T8_NE2 = UPLIT(SCAD_A SCADA_SEL_44 SC_EN SCADA_SEL_SC SCADA_SEL_SN DBM_SEL_SCAD NTWK);
421
422 BIND T8_ES = PLIT( T8_E1,
423 T8_E2);
424 BIND T8_NES = PLIT( T8_NE1,
425 T8_NE2);
426
427
428 BIND T9_E1 = UPLIT(SCAD_A SCADA_44 SCADA_BYTE1 DBM_SCAD NTWK);
429 BIND T9_NE1 = UPLIT(SCAD_A SCADA_44 SCADA_BYTE1 DBM_SCAD NTWK);
430 BIND T9_E2 = UPLIT(SCAD_A SCADA_SEL_44 SCADA_SEL_BYTE1 DBM_SEL_SCAD NTWK);
431 BIND T9_NE2 = UPLIT(SCAD_A SCADA_SEL_44 SCADA_SEL_BYTE1 DBM_SEL_SCAD NTWK);
432 BIND T9_E3 = UPLIT(SCAD_A SCADA_44 SCADA_BYTE2 DBM_SCAD NTWK);
433 BIND T9_NE3 = UPLIT(SCAD_A SCADA_44 SCADA_BYTE2 DBM_SCAD NTWK);
434 BIND T9_E4 = UPLIT(SCAD_A SCADA_SEL_44 SCADA_SEL_BYTE2 DBM_SEL_SCAD NTWK);
435 BIND T9_NE4 = UPLIT(SCAD_A SCADA_SEL_44 SCADA_SEL_BYTE2 DBM_SEL_SCAD NTWK);
436 BIND T9_E5 = UPLIT(SCAD_A SCADA_44 SCADA_BYTE3 DBM_SCAD NTWK);
437 BIND T9_NE5 = UPLIT(SCAD_A SCADA_44 SCADA_BYTE3 DBM_SCAD NTWK);
438 BIND T9_E6 = UPLIT(SCAD_A SCADA_SEL_44 SCADA_SEL_BYTE3 DBM_SEL_SCAD NTWK);
439 BIND T9_NE6 = UPLIT(SCAD_A SCADA_SEL_44 SCADA_SEL_BYTE3 DBM_SEL_SCAD NTWK);
440 BIND T9_E7 = UPLIT(SCAD_A SCADA_44 SCADA_BYTE4 DBM_SCAD NTWK);
441 BIND T9_NE7 = UPLIT(SCAD_A SCADA_44 SCADA_BYTE4 DBM_SCAD NTWK);
442 BIND T9_E8 = UPLIT(SCAD_A SCADA_SEL_44 SCADA_SEL_BYTE4 DBM_SEL_SCAD NTWK);
443 BIND T9_NE8 = UPLIT(SCAD_A SCADA_SEL_44 SCADA_SEL_BYTE4 DBM_SEL_SCAD NTWK);
444 BIND T9_E9 = UPLIT(SCAD_A SCADA_44 SCADA_BYTE5 DBM_SCAD NTWK);
445 BIND T9_NE9 = UPLIT(SCAD_A SCADA_44 SCADA_BYTE5 DBM_SCAD NTWK);
446 BIND T9_E10 = UPLIT(SCAD_A SCADA_SEL_44 SCADA_SEL_BYTE5 DBM_SEL_SCAD NTWK);
447 BIND T9_NE10 = UPLIT(SCAD_A SCADA_SEL_44 SCADA_SEL_BYTE5 DBM_SEL_SCAD NTWK);
448
449 BIND T9_ES = PLIT( T9_E1,
450 T9_E2,
451 T9_E3,
452 T9_E4,
453 T9_E5,
454 T9_E6,
455 T9_E7,
456 T9_E8,
457 T9_E9,
458 T9_E10);
459 BIND T9_NES = PLIT( T9_NE1,
460 T9_NE2,
461 T9_NE3,
462 T9_NE4,
463 T9_NE5,
464 T9_NE6,
465 T9_NE7,
466 T9_NE8,
467 T9_NE9,
468 T9_NE10);
469
470
471 BIND T10_E1 = UPLIT(SCAD_OR SCADB_FE SCADA_SN SCAD_A SCADA_SC SC FE DBM_SCAD NTWK);
472 BIND T10_NE1 = UPLIT(SCAD_OR SCADB_FE SCADA_SN SCAD_A SCADA_SC SC FE DBM_SCAD NTWK);
473 BIND T10_E2 = UPLIT(SCAD_OR SCADB_SEL_FE SCADA_SEL_SN SCAD_A SCADA_SEL_SC SC_EN FE_EN DBM_SEL_SCAD NTWK);
474 BIND T10_NE2 = UPLIT(SCAD_OR SCADB_SEL_FE SCADA_SEL_SN SCAD_A SCADA_SEL_SC SC_EN FE_EN DBM_SEL_SCAD NTWK);
475
476 BIND T10_ES = PLIT( T10_E1,
477 T10_E2);
478 BIND T10_NES = PLIT( T10_NE1,
479 T10_NE2);
480
481
482 BIND T11_E1 = UPLIT(SCAD_OR SCADB_SHIFT SCADA_SN DBM_SCAD NTWK);
483 BIND T11_NE1 = UPLIT(SCAD_OR SCADB_SHIFT SCADA_SN DBM_SCAD NTWK);
484 BIND T11_E2 = UPLIT(SCAD_OR SCADB_SEL_SHIFT SCADA_SEL_SN DBM_SEL_SCAD NTWK);
485 BIND T11_NE2 = UPLIT(SCAD_OR SCADB_SEL_SHIFT SCADA_SEL_SN DBM_SEL_SCAD NTWK);
486
487 BIND T11_ES = PLIT( T11_E1,
488 T11_E2);
489 BIND T11_NES = PLIT( T11_NE1,
490 T11_NE2);
491
492
493 BIND T12_E1 = UPLIT(SCAD_OR SCADB_SIZE SCADA_SN DBM_SCAD NTWK);
494 BIND T12_NE1 = UPLIT(SCAD_OR SCADB_SIZE SCADA_SN DBM_SCAD NTWK);
495 BIND T12_E2 = UPLIT(SCAD_OR SCADB_SEL_SIZE SCADA_SEL_SN DBM_SEL_SCAD NTWK);
496 BIND T12_NE2 = UPLIT(SCAD_OR SCADB_SEL_SIZE SCADA_SEL_SN DBM_SEL_SCAD NTWK);
497
498 BIND T12_ES = PLIT( T12_E1,
499 T12_E2);
500 BIND T12_NES = PLIT( T12_NE1,
501 T12_NE2);
502
503
504 BIND T13_E1 = UPLIT(SCADB_EXP SCAD_OR SCADA_SN SCADA_SEL_SN DBM_SCAD DBM_SEL_SCAD NTWK);
505 BIND T13_NE1 = UPLIT(SCADB_EXP SCAD_OR SCADA_SN SCADA_SEL_SN DBM_SCAD DBM_SEL_SCAD NTWK);
506
507 BIND T13_ES = PLIT( T13_E1);
508 BIND T13_NES = PLIT( T13_NE1);
509
510
511 BIND T14_E1 = UPLIT(DBM_BYTES SCADA_SN SCADA_SEL_SN SCAD_A NTWK);
512 BIND T14_NE1 = UPLIT(DBM_BYTES SCADA_SN SCADA_SEL_SN SCAD_A NTWK);
513 BIND T14_E2 = UPLIT(DBM_SEL_BYTES SCADA_SN SCADA_SEL_SN SCAD_A NTWK);
514 BIND T14_NE2 = UPLIT(DBM_SEL_BYTES SCADA_SN SCADA_SEL_SN SCAD_A NTWK);
515
516 BIND T14_ES = PLIT( T14_E1,
517 T14_E2);
518 BIND T14_NES = PLIT( T14_NE1,
519 T14_NE2);
520
521
522 BIND T15_E1 = UPLIT(DBM_BYTES35 SCADA_SN SCADA_SEL_SN SCAD_A NTWK);
523 BIND T15_NE1 = UPLIT(DBM_BYTES35 SCADA_SN SCADA_SEL_SN SCAD_A NTWK);
524 BIND T15_E2 = UPLIT(DBM_SEL_BYTES35 SCADA_SN SCADA_SEL_SN SCAD_A NTWK);
525 BIND T15_NE2 = UPLIT(DBM_SEL_BYTES35 SCADA_SN SCADA_SEL_SN SCAD_A NTWK);
526
527 BIND T15_ES = PLIT( T15_E1,
528 T15_E2);
529 BIND T15_NES = PLIT( T15_NE1,
530 T15_NE2);
531
532
533 BIND T16_E1 = UPLIT(SCAD_AND SCADB_FE SCADA_SN SCAD_A SCADA_SC SC FE DBM_SCAD NTWK);
534 BIND T16_NE1 = UPLIT(SCAD_AND SCADB_FE SCADA_SN SCAD_A SCADA_SC SC FE DBM_SCAD NTWK);
535 BIND T16_E2 = UPLIT(SCAD_AND SCADB_SEL_FE SCADA_SEL_SN SCAD_A SCADA_SEL_SC SC_EN FE_EN DBM_SEL_SCAD NTWK);
536 BIND T16_NE2 = UPLIT(SCAD_AND SCADB_SEL_FE SCADA_SEL_SN SCAD_A SCADA_SEL_SC SC_EN FE_EN DBM_SEL_SCAD NTWK);
537
538 BIND T16_ES = PLIT( T16_E1,
539 T16_E2);
540 BIND T16_NES = PLIT( T16_NE1,
541 T16_NE2);
542
543
544 BIND T17_E1 = UPLIT(SCAD_ADD SC SC_EN SCADA_SC FE FE_EN SCADB_FE DBM_SCAD DBM_SEL_SCAD SCADA_SN SCADA_SEL_SN NTWK);
545 BIND T17_NE1 = UPLIT(SCAD_ADD SC SC_EN SCADA_SC FE FE_EN SCADB_FE DBM_SCAD DBM_SEL_SCAD SCADA_SN SCADA_SEL_SN NTWK);
546 BIND T17_E2 = UPLIT(SCAD_SUB SC SC_EN SCADA_SC FE FE_EN SCADB_FE DBM_SCAD DBM_SEL_SCAD SCADA_SN SCADA_SEL_SN NTWK);
547 BIND T17_NE2 = UPLIT(SCAD_SUB SC SC_EN SCADA_SC FE FE_EN SCADB_FE DBM_SCAD DBM_SEL_SCAD SCADA_SN SCADA_SEL_SN NTWK);
548 BIND T17_E3 = UPLIT(SCAD_SUBB SC SC_EN SCADA_SC FE FE_EN SCADB_FE DBM_SCAD DBM_SEL_SCAD SCADA_SN SCADA_SEL_SN NTWK);
549 BIND T17_NE3 = UPLIT(SCAD_SUBB SC SC_EN SCADA_SC FE FE_EN SCADB_FE DBM_SCAD DBM_SEL_SCAD SCADA_SN SCADA_SEL_SN NTWK);
550
551 BIND T17_ES = PLIT( T17_E1,
552 T17_E2,
553 T17_E3);
554 BIND T17_NES = PLIT( T17_NE1,
555 T17_NE2,
556 T17_NE3);
557
558
559 BIND T18_NE1 = UPLIT(VMA_USER_DP VMA_FETCH_DP VMA_PHYS_DP VMA_PREV_DP VMA_CYCLE_DP VMA DBM_VMA SPEC_SWEEP NTWK);
560 BIND T18_E2 = UPLIT(VMA_USER_DP DBM_VMA SPEC_SWEEP VMA_SWEEP NTWK);
561 BIND T18_NE2 = UPLIT(VMA_USER_DP NTWK);
562 BIND T18_E3 = UPLIT(VMA_FETCH_DP DBM_VMA SPEC_SWEEP VMA_SWEEP NTWK);
563 BIND T18_NE3 = UPLIT(VMA_FETCH_DP NTWK);
564 BIND T18_E4 = UPLIT(VMA_PHYS_DP DBM_VMA SPEC_SWEEP VMA_SWEEP NTWK);
565 BIND T18_NE4 = UPLIT(VMA_PHYS_DP NTWK);
566 BIND T18_E5 = UPLIT(VMA_PREV_DP DBM_VMA SPEC_SWEEP VMA_SWEEP NTWK);
567 BIND T18_NE5 = UPLIT(VMA_PREV_DP NTWK);
568 BIND T18_E6 = UPLIT(VMA_CYCLE_DP DBM_VMA SPEC_SWEEP VMA_SWEEP NTWK);
569 BIND T18_NE6 = UPLIT(VMA_CYCLE_DP NTWK);
570 BIND T18_E7 = UPLIT(VMA DBM_VMA SPEC_SWEEP VMA_SWEEP NTWK);
571 BIND T18_NE7 = UPLIT(VMA NTWK);
572
573 BIND T18_ES = PLIT( T18_E2,
574 T18_E3,
575 T18_E4,
576 T18_E5,
577 T18_E6,
578 T18_E7);
579 BIND T18_NES = PLIT( T18_NE1,
580 T18_NE2,
581 T18_NE3,
582 T18_NE4,
583 T18_NE5,
584 T18_NE6,
585 T18_NE7);
586
587
588 BIND T19_E1 = UPLIT(DBM_EXP DBM_SEL_EXP SCAD_A SCADA_SN NTWK);
589 BIND T19_NE1 = UPLIT(DBM_EXP DBM_SEL_EXP SCAD_A SCADA_SN NTWK);
590
591 BIND T19_ES = PLIT( T19_E1);
592 BIND T19_NES = PLIT( T19_NE1);
593
594
595 BIND T20_NE1 = UPLIT(VMA_USER_N VMA_FETCH_N VMA_PHYS_N VMA_CYCLE_N NTWK);
596 BIND T20_E2 = UPLIT(VMA_USER_N DBM_VMA DBM_SEL_VMA SPEC_SWEEP VMA_SWEEP NTWK);
597 BIND T20_NE2 = UPLIT(VMA_USER_N NTWK);
598 BIND T20_E3 = UPLIT(VMA_FETCH_N DBM_VMA DBM_SEL_VMA SPEC_SWEEP VMA_SWEEP NTWK);
599 BIND T20_NE3 = UPLIT(VMA_FETCH_N NTWK);
600 BIND T20_E4 = UPLIT(VMA_PHYS_N DBM_VMA DBM_SEL_VMA SPEC_SWEEP VMA_SWEEP NTWK);
601 BIND T20_NE4 = UPLIT(VMA_PHYS_N NTWK);
602 BIND T20_E5 = UPLIT(VMA_CYCLE_N DBM_VMA DBM_SEL_VMA SPEC_SWEEP VMA_SWEEP NTWK);
603 BIND T20_NE5 = UPLIT(VMA_CYCLE_N NTWK);
604
605 BIND T20_ES = PLIT( T20_E2,
606 T20_E3,
607 T20_E4,
608 T20_E5);
609 BIND T20_NES = PLIT( T20_NE1,
610 T20_NE2,
611 T20_NE3,
612 T20_NE4,
613 T20_NE5);
614
615
616 BIND T21_E1 = UPLIT(MEM_WRITE_N FORCE AC_REF VMA_ALL_N STOP MEM_EN NTWK);
617 BIND T21_NE1 = UPLIT(MEM_WRITE_N NTWK);
618 BIND T21_E2 = UPLIT(MEM_READ_N FORCE AC_REF VMA_ALL_N STOP MEM_EN NTWK);
619 BIND T21_NE2 = UPLIT(MEM_READ_N NTWK);
620
621 BIND T21_ES = PLIT( T21_E1,
622 T21_E2);
623 BIND T21_NES = PLIT( T21_NE1,
624 T21_NE2);
625
626
627 BIND T22_E1 = UPLIT(BUS_ALL BUS_MUX_VMA VMA_ALL_N FORCE AC_REF STOP MEM_EN BUS_REQ MEM_READ_N MEM_WRITE_N NTWK);
628 BIND T22_NE1 = UPLIT(MEM_READ_N MEM_WRITE_N BUS_REQ MEM_EN NTWK);
629
630 BIND T22_ES = PLIT( T22_E1);
631 BIND T22_NES = PLIT( T22_NE1);
632
633
634 BIND T23_E1 = UPLIT(BUS_R DBM_MEM DBM_SEL_MEM BUS_MUX_VMA BUS_ALL VMA_ALL_N MEM_EN BUS_REQ MEM_READ_N NTWK);
635 BIND T23_NE1 = UPLIT(BUS_R NTWK);
636
637 BIND T23_ES = PLIT( T23_E1);
638 BIND T23_NES = PLIT( T23_NE1);
639
640
641 BIND T24_E1 = UPLIT(BUS_T BUS_MUX_DP BUS_MUX_VMA BUS_ALL VMA_ALL_N MEM_EN BUS_REQ MEM_WRITE_N NTWK);
642 BIND T24_NE1 = UPLIT(BUS_T BUS_MUX_DP NTWK);
643
644 BIND T24_ES = PLIT( T24_E1);
645 BIND T24_NES = PLIT( T24_NE1);
646
647
648 BIND T25_E1 = UPLIT(AC_REF FORCE BUS_T BUS_MUX_DP BUS_MUX_VMA BUS_ALL VMA_ALL_N MEM_EN BUS_REQ MEM_WRITE_N NTWK);
649 BIND T25_NE1 = UPLIT( NTWK);
650
651 BIND T25_ES = PLIT( T25_E1);
652 BIND T25_NES = PLIT( T25_NE1);
653
654
655 BIND T26_E1 = UPLIT(AC_REF FORCE BUS_T BUS_MUX_DP BUS_MUX_VMA BUS_ALL VMA_ALL_N MEM_EN BUS_REQ MEM_WRITE_N NTWK);
656 BIND T26_NE1 = UPLIT( NTWK);
657
658 BIND T26_ES = PLIT( T26_E1);
659 BIND T26_NES = PLIT( T26_NE1);
660
661
662 BIND T27_E1 = UPLIT(DBM_VMA_MEM DBM_SEL_VMA MEM_CAC_INH_N NTWK);
663 BIND T27_NE1 = UPLIT(MEM_CAC_INH_N NTWK);
664 BIND T27_E2 = UPLIT(DBM_VMA_MEM DBM_SEL_VMA NTWK);
665 BIND T27_NE2 = UPLIT( NTWK);
666 BIND T27_E3 = UPLIT(DBM_VMA_MEM DBM_SEL_VMA MEM_WRITE_N NTWK);
667 BIND T27_NE3 = UPLIT(MEM_WRITE_N NTWK);
668 BIND T27_E4 = UPLIT(DBM_VMA_MEM DBM_SEL_VMA MEM_WR_TEST_N NTWK);
669 BIND T27_NE4 = UPLIT(MEM_WR_TEST_N NTWK);
670 BIND T27_E5 = UPLIT(DBM_VMA_MEM DBM_SEL_VMA MEM_READ_N NTWK);
671 BIND T27_NE5 = UPLIT(MEM_READ_N NTWK);
672
673 BIND T27_ES = PLIT( T27_E1,
674 T27_E2,
675 T27_E3,
676 T27_E4,
677 T27_E5);
678 BIND T27_NES = PLIT( T27_NE1,
679 T27_NE2,
680 T27_NE3,
681 T27_NE4,
682 T27_NE5);
683
684
685 BIND T28_E1 = UPLIT(DBM_VMA_MEM DBM_SEL_VMA MEM_CAC_INH_DP NTWK);
686 BIND T28_NE1 = UPLIT(MEM_CAC_INH_DP NTWK);
687 BIND T28_E2 = UPLIT(DBM_VMA_MEM DBM_SEL_VMA NTWK);
688 BIND T28_NE2 = UPLIT( NTWK);
689 BIND T28_E3 = UPLIT(DBM_VMA_MEM DBM_SEL_VMA MEM_WRITE_DP NTWK);
690 BIND T28_NE3 = UPLIT(MEM_WRITE_DP NTWK);
691 BIND T28_E4 = UPLIT(DBM_VMA_MEM DBM_SEL_VMA MEM_WR_TEST_DP NTWK);
692 BIND T28_NE4 = UPLIT(MEM_WR_TEST_DP NTWK);
693 BIND T28_E5 = UPLIT(DBM_VMA_MEM DBM_SEL_VMA MEM_READ_DP NTWK);
694 BIND T28_NE5 = UPLIT(MEM_READ_DP NTWK);
695
696 BIND T28_ES = PLIT( T28_E1,
697 T28_E2,
698 T28_E3,
699 T28_E4,
700 T28_E5);
701 BIND T28_NES = PLIT( T28_NE1,
702 T28_NE2,
703 T28_NE3,
704 T28_NE4,
705 T28_NE5);
706
707
708 BIND T29_E1 = UPLIT(DBM_VMA_MEM DBM_SEL_VMA MEM_CAC_INH_DRO NTWK);
709 BIND T29_NE1 = UPLIT(MEM_CAC_INH_DRO NTWK);
710 BIND T29_E2 = UPLIT(DBM_VMA_MEM DBM_SEL_VMA NTWK);
711 BIND T29_NE2 = UPLIT( NTWK);
712 BIND T29_E3 = UPLIT(DBM_VMA_MEM DBM_SEL_VMA MEM_WRITE_DRO NTWK);
713 BIND T29_NE3 = UPLIT(MEM_WRITE_DRO NTWK);
714 BIND T29_E4 = UPLIT(DBM_VMA_MEM DBM_SEL_VMA MEM_WR_TEST_DRO NTWK);
715 BIND T29_NE4 = UPLIT(MEM_WR_TEST_DRO NTWK);
716 BIND T29_E5 = UPLIT(DBM_VMA_MEM DBM_SEL_VMA MEM_READ_DRO NTWK);
717 BIND T29_NE5 = UPLIT(MEM_READ_DRO NTWK);
718
719 BIND T29_ES = PLIT( T29_E1,
720 T29_E2,
721 T29_E3,
722 T29_E4,
723 T29_E5);
724 BIND T29_NES = PLIT( T29_NE1,
725 T29_NE2,
726 T29_NE3,
727 T29_NE4,
728 T29_NE5);
729
730
731 BIND T30_E1 = UPLIT(N_ALL BUS_ALL BUS_MUX_VMA BUS_MUX_DP VMA_ALL_N MEM_WRITE_N MEM_CAC_INH_N FORCE AC_REF MEM_EN NTWK);
732 BIND T30_NE1 = UPLIT(MEM_EN NTWK);
733
734 BIND T30_ES = PLIT( T30_E1);
735 BIND T30_NES = PLIT( T30_NE1);
736
737
738 BIND T31_E1 = UPLIT(BUS_REQ_A BUS_ALL BUS_MUX_VMA BUS_MUX_DP VMA_ALL_N MEM_WRITE_N MEM_CAC_INH_N FORCE AC_REF MEM_EN NTWK);
739 BIND T31_NE1 = UPLIT(BUS_REQ_A NTWK);
740
741 BIND T31_ES = PLIT( T31_E1);
742 BIND T31_NES = PLIT( T31_NE1);
743
744
745 BIND T32_E1 = UPLIT(PT_IO PT_VAL_WRT PT_USR PT_MESS N_ALL NTWK);
746 BIND T32_NE1 = UPLIT(PT_IO NTWK);
747
748 BIND T32_ES = PLIT( T32_E1);
749 BIND T32_NES = PLIT( T32_NE1);
750
751
752 BIND T33_E1 = UPLIT(PT_ADR PT_IO PT_VAL_WRT PT_USR PT_MESS N_ALL NTWK);
753 BIND T33_NE1 = UPLIT(PT_ADR SPEC_PAGE NTWK);
754
755 BIND T33_ES = PLIT( T33_E1);
756 BIND T33_NES = PLIT( T33_NE1);
757
758
759 BIND T34_E1 = UPLIT(PT_VAL_WRT PT_IO PF_WT PF_CODE PT_USR PT_MESS N_ALL NTWK);
760 BIND T34_NE1 = UPLIT(PT_VAL_WRT NTWK);
761
762 BIND T34_ES = PLIT( T34_E1);
763 BIND T34_NES = PLIT( T34_NE1);
764
765
766 BIND T35_E1 = UPLIT(VMA_USER_PREV SPEC_PREV SPEC_PXCT MEM_EN N_ALL VMA_EN DBM_VMA_MEM DBM_SEL_VMA NTWK);
767 BIND T35_NE1 = UPLIT(VMA_USER_DP VMA_USER_N VMA_PREV_DP VMA_PREV_N SPEC_PXCT_OFF SPEC_PREV NTWK);
768
769 BIND T35_ES = PLIT( T35_E1);
770 BIND T35_NES = PLIT( T35_NE1);
771
772
773 BIND T36_E1 = UPLIT(PT_USR PT_IO PT_VAL_WRT PT_USR PT_MESS N_ALL PF_CODE NTWK);
774 BIND T36_NE1 = UPLIT(PT_USR NTWK);
775
776 BIND T36_ES = PLIT( T36_E1);
777 BIND T36_NES = PLIT( T36_NE1);
778
779
780 BIND T37_E1 = UPLIT(PT_VAL_WRT PT_IO PF_WT PF_CODE PT_USR PT_MESS N_ALL NTWK);
781 BIND T37_NE1 = UPLIT(PF_WT NTWK);
782
783 BIND T37_ES = PLIT( T37_E1);
784 BIND T37_NES = PLIT( T37_NE1);
785
786
787 BIND T38_E1 = UPLIT(PT_VAL_WRT PT_IO PF_NXM SPEC_MEMCLR_NXM PF_CODE PT_USR PT_MESS N_ALL NTWK);
788 BIND T38_NE1 = UPLIT(PF_NXM SPEC_MEMCLR_NXM NTWK);
789
790 BIND T38_ES = PLIT( T38_E1);
791 BIND T38_NES = PLIT( T38_NE1);
792
793
794 BIND T39_E1 = UPLIT(PT_VAL_WRT PT_IO PF_WT PF_CODE PT_USR PT_MESS N_ALL PF_BAD SPEC_MEMCLR_BAD NTWK);
795 BIND T39_NE1 = UPLIT(PF_BAD SPEC_MEMCLR_BAD NTWK);
796
797 BIND T39_ES = PLIT( T39_E1);
798 BIND T39_NES = PLIT( T39_NE1);
799
800
801 BIND T40_E1 = UPLIT(PT_VAL_WRT PT_IO PF_WT PF_CODE PT_USR PT_MESS N_ALL PF_OK NTWK);
802 BIND T40_NE1 = UPLIT(PF_OK NTWK);
803
804 BIND T40_ES = PLIT( T40_E1);
805 BIND T40_NES = PLIT( T40_NE1);
806
807
808 BIND T41_E1 = UPLIT(VMA_SWEEP_PT VMA_SWEEP SPEC_SWEEP PT_VAL_WRT PT_IO PF_WT PF_CODE PT_USR PT_MESS N_ALL NTWK);
809 BIND T41_NE1 = UPLIT(VMA_SWEEP_PT NTWK);
810
811 BIND T41_ES = PLIT( T41_E1);
812 BIND T41_NES = PLIT( T41_NE1);
813
814
815 BIND T42_E1 = UPLIT(CD_HIT PT_CAC CD_ADR CD_IO CD_CMP PT_IO PT_ADR PT_MESS N_ALL NTWK);
816 BIND T42_NE1 = UPLIT(CD_HIT PT_CAC NTWK);
817
818 BIND T42_ES = PLIT( T42_E1);
819 BIND T42_NES = PLIT( T42_NE1);
820
821
822 BIND T43_E1 = UPLIT(CD_HIT PT_CAC CD_ADR CD_IO CD_CMP PT_IO PT_ADR PT_MESS N_ALL NTWK);
823 BIND T43_NE1 = UPLIT(CD_IO NTWK);
824
825 BIND T43_ES = PLIT( T43_E1);
826 BIND T43_NES = PLIT( T43_NE1);
827
828
829 BIND T44_E1 = UPLIT(CD_HIT PT_CAC CD_ADR CD_IO CD_CMP PT_IO PT_ADR PT_MESS N_ALL NTWK);
830 BIND T44_NE1 = UPLIT(CD_ADR NTWK);
831
832 BIND T44_ES = PLIT( T44_E1);
833 BIND T44_NES = PLIT( T44_NE1);
834
835
836 BIND T45_E1 = UPLIT(VMA_SWEEP_CD VMA_SWEEP SPEC_SWEEP CD_HIT CD_ADR CD_IO CD_CMP PT_CAC PT_USR PT_IO PT_ADR PT_MESS N_ALL NTWK);
837 BIND T45_NE1 = UPLIT(VMA_SWEEP_CD NTWK);
838
839 BIND T45_ES = PLIT( T45_E1);
840 BIND T45_NES = PLIT( T45_NE1);
841
842
843 BIND T46_E1 = UPLIT(CD_HIT CD_ADR CD_IO CD_CMP PT_CAC PT_USR PT_IO PT_ADR PT_MESS N_ALL NTWK);
844 BIND T46_NE1 = UPLIT( NTWK);
845
846 BIND T46_ES = PLIT( T46_E1);
847 BIND T46_NES = PLIT( T46_NE1);
848
849
850 BIND T47_E1 = UPLIT(CD_VAL CD_HIT PT_CAC CD_ADR CD_IO CD_CMP PT_IO PT_ADR PT_MESS N_ALL NTWK);
851 BIND T47_NE1 = UPLIT(CD_VAL NTWK);
852
853 BIND T47_ES = PLIT( T47_E1);
854 BIND T47_NES = PLIT( T47_NE1);
855
856
857 BIND T48_E1 = UPLIT(PT_RAM_PAG_USR PT_IO PT_VAL_WRT PT_USR PT_MESS NTWK);
858 BIND T48_NE1 = UPLIT(PT_RAM_PAG_USR NTWK);
859
860 BIND T48_ES = PLIT( T48_E1);
861 BIND T48_NES = PLIT( T48_NE1);
862
863
864 BIND T49_E1 = UPLIT(PT_RAM_VAL_WRT PT_IO PT_VAL_WRT PT_USR PT_MESS PF_CODE NTWK);
865 BIND T49_NE1 = UPLIT(PT_RAM_VAL_WRT NTWK);
866
867 BIND T49_ES = PLIT( T49_E1);
868 BIND T49_NES = PLIT( T49_NE1);
869
870
871 BIND T50_E1 = UPLIT(CD_RAM_PAG_USR CD_HIT PT_CAC CD_ADR CD_IO CD_CMP PT_IO PT_ADR PT_MESS N_ALL NTWK);
872 BIND T50_NE1 = UPLIT(CD_RAM_PAG_USR NTWK);
873
874 BIND T50_ES = PLIT( T50_E1);
875 BIND T50_NES = PLIT( T50_NE1);
876
877
878 BIND T51_E1 = UPLIT(CD_RAM_VAL CD_HIT PT_CAC CD_ADR CD_IO CD_CMP PT_IO PT_ADR PT_MESS N_ALL NTWK);
879 BIND T51_NE1 = UPLIT(CD_RAM_VAL NTWK);
880
881 BIND T51_ES = PLIT( T51_E1);
882 BIND T51_NES = PLIT( T51_NE1);
883
884
885 BIND T52_E1 = UPLIT(PT_RAM_CAC CD_IO CD_CMP CD_HIT PT_IO PT_ADR PT_CAC PT_MESS N_ALL NTWK);
886 BIND T52_NE1 = UPLIT(PT_RAM_CAC NTWK);
887
888 BIND T52_ES = PLIT( T52_E1);
889 BIND T52_NES = PLIT( T52_NE1);
890
891
892 BIND T53_E1 = UPLIT(BUS_PAR BUS_ALL BUS_MUX NTWK);
893 BIND T53_NE1 = UPLIT(BUS_PAR NTWK);
894
895 BIND T53_ES = PLIT( T53_E1);
896 BIND T53_NES = PLIT( T53_NE1);
897
898
899 BIND T54_E1 = UPLIT(APR DBM_APR DBM_SEL_APR NTWK);
900 BIND T54_NE1 = UPLIT(APR DBM_APR DBM_SEL_APR NTWK);
901
902 BIND T54_ES = PLIT( T54_E1);
903 BIND T54_NES = PLIT( T54_NE1);
904
905
906 BIND T55_E1 = UPLIT(APR_EN DBM_APR_EN DBM_SEL_APR_EN APR NTWK);
907 BIND T55_NE1 = UPLIT(APR_EN DBM_APR_EN DBM_SEL_APR_EN NTWK);
908
909 BIND T55_ES = PLIT( T55_E1);
910 BIND T55_NES = PLIT( T55_NE1);
911
912
913 BIND T56_E1 = UPLIT(PT_PAR PT_PAR_GEN PAR_ERR BUS_T BUS_R BUS_PAR NTWK);
914 BIND T56_NE1 = UPLIT(PT_PAR PT_PAR_GEN NTWK);
915
916 BIND T56_ES = PLIT( T56_E1);
917 BIND T56_NES = PLIT( T56_NE1);
918
919
920 BIND T57_E1 = UPLIT(PT_RAM_PAR PT_PAR PT_PAR_GEN PAR_ERR BUS_T BUS_R BUS_PAR NTWK);
921 BIND T57_NE1 = UPLIT(PT_RAM_PAR PT_PAR PT_PAR_GEN NTWK);
922
923 BIND T57_ES = PLIT( T57_E1);
924 BIND T57_NES = PLIT( T57_NE1);
925
926
927 BIND T58_E1 = UPLIT(CD_PAR PAR_ERR N_ALL PT_IO PT_CAC CD_IO CD_CMP CD_HIT PT_MESS NTWK);
928 BIND T58_NE1 = UPLIT(CD_PAR NTWK);
929
930 BIND T58_ES = PLIT( T58_E1);
931 BIND T58_NES = PLIT( T58_NE1);
932
933
934 BIND T59_E1 = UPLIT(CD_RAM_PAR CD_PAR PAR_ERR N_ALL PT_IO PT_CAC CD_IO CD_CMP CD_HIT PT_MESS NTWK);
935 BIND T59_NE1 = UPLIT(CD_RAM_PAR NTWK);
936
937 BIND T59_ES = PLIT( T59_E1);
938 BIND T59_NES = PLIT( T59_NE1);
939
940
941 BIND T60_E1 = UPLIT(PXCT PXCT_MUX DBM_VMA DBM_SEL_VMA SPEC_PXCT_EN SPEC_PXCT_OFF NTWK);
942 BIND T60_NE1 = UPLIT(PXCT PXCT_MUX DBM_VMA DBM_SEL_VMA SPEC_PXCT_EN SPEC_PXCT_OFF NTWK);
943
944 BIND T60_ES = PLIT( T60_E1);
945 BIND T60_NES = PLIT( T60_NE1);
946
947
948 BIND T61_E1 = UPLIT(PXCT PXCT_MUX_DPE SPEC_PXCT_EN SPEC_PXCT_OFF NTWK);
949 BIND T61_NE1 = UPLIT(PXCT PXCT_MUX_DPE SPEC_PXCT_EN SPEC_PXCT_OFF NTWK);
950
951 BIND T61_ES = PLIT( T61_E1);
952 BIND T61_NES = PLIT( T61_NE1);
953
954
955 BIND T62_E1 = UPLIT(SCAD_A SC_EN SC_SIGN SCADA_SN SCADA_SEL_SN NTWK);
956 BIND T62_NE1 = UPLIT(SCAD_A SC_EN SC_SIGN SCADA_SN SCADA_SEL_SN NTWK);
957
958 BIND T62_ES = PLIT( T62_E1);
959 BIND T62_NES = PLIT( T62_NE1);
960
961
962 BIND T63_E1 = UPLIT(FE_SIGN FE_EN SCAD_A_DEC SCADA_SN SCADA_SEL_SN NTWK);
963 BIND T63_NE1 = UPLIT(FE_SIGN FE_EN NTWK);
964
965 BIND T63_ES = PLIT( T63_E1);
966 BIND T63_NES = PLIT( T63_NE1);
967
968
969 BIND T64_E1 = UPLIT(MSEC DBM_MSEC NTWK);
970 BIND T64_NE1 = UPLIT(MSEC DBM_MSEC NTWK);
971
972 BIND T64_ES = PLIT( T64_E1);
973 BIND T64_NES = PLIT( T64_NE1);
974
975
976 BIND T65_E1 = UPLIT(MSEC_FREQ DBM_MSEC NTWK);
977 BIND T65_NE1 = UPLIT(MSEC_FREQ DBM_MSEC NTWK);
978
979 BIND T65_ES = PLIT( T65_E1);
980
981 BIND T65_NES = PLIT( T65_NE1);
982 GLOBAL BIND ES_TBL = UPLIT( T1_ES,
983 T2_ES,
984 T3_ES,
985 T4_ES,
986 T5_ES,
987 T6_ES,
988 T7_ES,
989 T8_ES,
990 T9_ES,
991 T10_ES,
992 T11_ES,
993 T12_ES,
994 T13_ES,
995 T14_ES,
996 T15_ES,
997 T16_ES,
998 T17_ES,
999 T18_ES,
1000 T19_ES,
1001 T20_ES,
1002 T21_ES,
1003 T22_ES,
1004 T23_ES,
1005 T24_ES,
1006 T25_ES,
1007 T26_ES,
1008 T27_ES,
1009 T28_ES,
1010 T29_ES,
1011 T30_ES,
1012 T31_ES,
1013 T32_ES,
1014 T33_ES,
1015 T34_ES,
1016 T35_ES,
1017 T36_ES,
1018 T37_ES,
1019 T38_ES,
1020 T39_ES,
1021 T40_ES,
1022 T41_ES,
1023 T42_ES,
1024 T43_ES,
1025 T44_ES,
1026 T45_ES,
1027 T46_ES,
1028 T47_ES,
1029 T48_ES,
1030 T49_ES,
1031 T50_ES,
1032 T51_ES,
1033 T52_ES,
1034 T53_ES,
1035 T54_ES,
1036 T55_ES,
1037 T56_ES,
1038 T57_ES,
1039 T58_ES,
1040 T59_ES,
1041 T60_ES,
1042 T61_ES,
1043 T62_ES,
1044 T63_ES,
1045 T64_ES,
1046 T65_ES);
1047
1048 GLOBAL BIND NES_TBL = UPLIT( T1_NES,
1049 T2_NES,
1050 T3_NES,
1051 T4_NES,
1052 T5_NES,
1053 T6_NES,
1054 T7_NES,
1055 T8_NES,
1056 T9_NES,
1057 T10_NES,
1058 T11_NES,
1059 T12_NES,
1060 T13_NES,
1061 T14_NES,
1062 T15_NES,
1063 T16_NES,
1064 T17_NES,
1065 T18_NES,
1066 T19_NES,
1067 T20_NES,
1068 T21_NES,
1069 T22_NES,
1070 T23_NES,
1071 T24_NES,
1072 T25_NES,
1073 T26_NES,
1074 T27_NES,
1075 T28_NES,
1076 T29_NES,
1077 T30_NES,
1078 T31_NES,
1079 T32_NES,
1080 T33_NES,
1081 T34_NES,
1082 T35_NES,
1083 T36_NES,
1084 T37_NES,
1085 T38_NES,
1086 T39_NES,
1087 T40_NES,
1088 T41_NES,
1089 T42_NES,
1090 T43_NES,
1091 T44_NES,
1092 T45_NES,
1093 T46_NES,
1094 T47_NES,
1095 T48_NES,
1096 T49_NES,
1097 T50_NES,
1098 T51_NES,
1099 T52_NES,
1100 T53_NES,
1101 T54_NES,
1102 T55_NES,
1103 T56_NES,
1104 T57_NES,
1105 T58_NES,
1106 T59_NES,
1107 T60_NES,
1108 T61_NES,
1109 T62_NES,
1110 T63_NES,
1111 T64_NES,
1112 T65_NES);
1113
1114 EXTERNAL ROUTINE
1115 TST1,
1116 TST2,
1117 TST3,
1118 TST4,
1119 TST5,
1120 TST6,
1121 TST7,
1122 TST8,
1123 TST9,
1124 TST10,
1125 TST11,
1126 TST12,
1127 TST13,
1128 TST14,
1129 TST15,
1130 TST16,
1131 TST17,
1132 TST18,
1133 TST19,
1134 TST20,
1135 TST21,
1136 TST22,
1137 TST23,
1138 TST24,
1139 TST25,
1140 TST26,
1141 TST27,
1142 TST28,
1143 TST29,
1144 TST30,
1145 TST31,
1146 TST32,
1147 TST33,
1148 TST34,
1149 TST35,
1150 TST36,
1151 TST37,
1152 TST38,
1153 TST39,
1154 TST40,
1155 TST41,
1156 TST42,
1157 TST43,
1158 TST44,
1159 TST45,
1160 TST46,
1161 TST47,
1162 TST48,
1163 TST49,
1164 TST50,
1165 TST51,
1166 TST52,
1167 TST53,
1168 TST54,
1169 TST55,
1170 TST56,
1171 TST57,
1172 TST58,
1173 TST59,
1174 TST60,
1175 TST61,
1176 TST62,
1177 TST63,
1178 TST64,
1179 TST65;
1180
1181
1182 GLOBAL BIND TEST_DISP = PLIT( TST1,
1183 TST2,
1184 TST3,
1185 TST4,
1186 TST5,
1187 TST6,
1188 TST7,
1189 TST8,
1190 TST9,
1191 TST10,
1192 TST11,
1193 TST12,
1194 TST13,
1195 TST14,
1196 TST15,
1197 TST16,
1198 TST17,
1199 TST18,
1200 TST19,
1201 TST20,
1202 TST21,
1203 TST22,
1204 TST23,
1205 TST24,
1206 TST25,
1207 TST26,
1208 TST27,
1209 TST28,
1210 TST29,
1211 TST30,
1212 TST31,
1213 TST32,
1214 TST33,
1215 TST34,
1216 TST35,
1217 TST36,
1218 TST37,
1219 TST38,
1220 TST39,
1221 TST40,
1222 TST41,
1223 TST42,
1224 TST43,
1225 TST44,
1226 TST45,
1227 TST46,
1228 TST47,
1229 TST48,
1230 TST49,
1231 TST50,
1232 TST51,
1233 TST52,
1234 TST53,
1235 TST54,
1236 TST55,
1237 TST56,
1238 TST57,
1239 TST58,
1240 TST59,
1241 TST60,
1242 TST61,
1243 TST62,
1244 TST63,
1245 TST64,
1246 TST65);
1247 GLOBAL LITERAL MAXTEST = 65;
1248
1249 GLOBAL
1250 TESTS_FAILED: BITVECTOR[MAXTEST];
1251
1252 GLOBAL
1253 NET_FAULTS: BITVECTOR[MAXNETS];
1254
1255 END
1256 ELUDOM
AC_REF 198 616 618 627 648 655 731 738
ALLOC_B 54# 67 68# 70 76 84 346
ALLOC_B_1 59# 76 77
ALLOC_N 56# 88 91 96 325 340 344
ALLOC_NAME 66 79#
ALLOC_N_1 57# 91 92
ALLOC_SLIT 66 89 94
ALLOC_W 55# 71 73 77 82 83 329 345
ALLOC_W_1 58# 329 330 331
ALLOC 66# 111 112 113 114 115 116 117 118 119 120 121
122 123 126 127 128 129 130 131 132 133 134 135
136 137 138 139 142 143 144 145 146 147 148 149
150 151 152 153 154 155 156 157 158 159 160 161
162 163 164 165 168 169 170 171 172 173 174 175
178 179 180 181 182 183 184 185 186 187 188 189
190 191 192 193 194 195 196 197 198 201 202 203
204 205 206 207 208 209 210 211 212 213 214 215
216 217 218 219 220 221 222 225 228 229 230 231
232 233 234 235 236 237 238 239 240 241 242 243
244 247 248 249 250 251 252 253 254 255 258 259
260 261 264 265 268 269 270 271 272 273 274 275
276 277 278 279 280 281 282 283 284 285 286 289
292 293 294 295 298 299 300 301 302 303 304
APR 292 899 900 906
APR_EN 293 906 907
BAD_DATA 300
BLISS36 4
BUS 309# 311
BUS_ALL 311# 315 627 634 641 648 655 731 738 892
BUS_CLK 270 311
BUS_CYCLE 225 311
BUS_MUX 310# 892
BUS_MUX_DP 258 310 641 642 648 655 731 738
BUS_MUX_PAGE 260 310 315
BUS_MUX_VMA 259 310 627 634 641 648 655 731 738
BUS_NXM 299 311
BUS_PAR 261 892 893 913 920
BUS_REQ 213 311 315 627 628 634 641 648 655
BUS_REQ_A 214 738 739
BUS_R 265 309 634 635 913 920
BUS_TIMEOUT 298 311
BUS_T 264 309 641 642 648 655 913 920
BUS_XMIT 271 311
CD_ADR 247 815 822 829 830 836 843 850 871 878
CD_CMP 250 815 822 829 836 843 850 871 878 885 927 934
CD_HIT 251 815 816 822 829 836 843 850 871 878 885 927
934
CD_IO 248 815 822 823 829 836 843 850 871 878 885 927
934
CD_PAR 252 927 928 934
CD_RAM_PAG_USR 253 871 872
CD_RAM_PAR 255 934 935
CD_RAM_VAL 254 878 879
CD_VAL 249 850 851
CLK 268
CLK_APR 215
DATA_EDIT 51#
DATA_VERSION 50#
DBM_APR 128 899 900
DBM_APR_EN 129 906 907
DBM_BYTES 130 511 512
DBM_BYTES35 131 522 523
DBM_DP 134 370 371
DBM_DP_SWAP 135 359 360
DBM_EXP 132 588 589
DBM_MEM 138 634
DBM_MSEC 133 969 970 976 977
DBM_N 139 314 348 349
DBM_PF 127 316
DBM_SCAD 126 381 382 392 393 399 400 406 407 417 418 428
429 432 433 436 437 440 441 444 445 471 472 482
483 493 494 504 505 533 534 544 545 546 547 548
549
DBM_SEL_APR 113 899 900
DBM_SEL_APR_EN 114 906 907
DBM_SEL_BYTES 115 513 514
DBM_SEL_BYTES35 116 524 525
DBM_SEL_DP_SWAP 120 361 362
DBM_SEL_DP 119 372 373
DBM_SEL_EXP 117 588 589
DBM_SEL_MEM 122 634
DBM_SEL_MSEC 118
DBM_SEL_N 123 314 350 351
DBM_SEL_PF 112 316
DBM_SEL_SCAD 111 383 384 392 393 399 400 408 409 419 420 430
431 434 435 438 439 442 443 446 447 473 474 484
485 495 496 504 505 535 536 544 545 546 547 548
549
DBM_SEL_VMA 121 596 598 600 602 662 664 666 668 670 685 687
689 691 693 708 710 712 714 716 766 941 942
DBM_VMA 136 559 560 562 564 566 568 570 596 598 600 602
941 942
DBM_VMA_MEM 137 662 664 666 668 670 685 687 689 691 693 708
710 712 714 716 766
DUMP 98# 102 330 340
DUMP_ASSIGN 104# 107 331
ES_TBL 982#
FE 192 471 472 533 534 544 545 546 547 548 549
FE_EN 193 473 474 535 536 544 545 546 547 548 549 962
963
FE_SIGN 194 962 963
FORCE 222 616 618 627 648 655 731 738
IO_CYCLE 302
LANGUAGE 4
MAXNETS 325# 1253
MAXTEST 1247# 1250
MEM_CAC_INH_DP 211 685 686
MEM_CAC_INH_DRO 212 708 709
MEM_CAC_INH_N 210 662 663 731 738
MEM_CYCLE 301
MEM_DELAY 216
MEM_EN 218 315 616 618 627 628 634 641 648 655 731 732
738 766
MEM_READ_DP 202 693 694
MEM_READ_DRO 203 716 717
MEM_READ_N 201 315 618 619 627 628 634 670 671
MEM_WAIT 221
MEM_WRITE_DP 205 689 690
MEM_WRITE_DRO 206 712 713
MEM_WRITE_N 204 315 616 617 627 628 641 648 655 666 667 731
738
MEM_WR_TEST_DP 208 691 692
MEM_WR_TEST_DRO 209 714 715
MEM_WR_TEST_N 207 668 669
MSDPMD 3#
MSEC 303 969 970
MSEC_FREQ 304 976 977
N 98 99 102 104 105 107
NES_TBL 1048#
NET_FAULTS 1253
NET_NAMES 338#
NTWK 328# 348 349 350 351 359 360 361 362 370 371 372
373 381 382 383 384 392 393 399 400 406 407 408
409 417 418 419 420 428 429 430 431 432 433 434
435 436 437 438 439 440 441 442 443 444 445 446
447 471 472 473 474 482 483 484 485 493 494 495
496 504 505 511 512 513 514 522 523 524 525 533
534 535 536 544 545 546 547 548 549 559 560 561
562 563 564 565 566 567 568 569 570 571 588 589
595 596 597 598 599 600 601 602 603 616 617 618
619 627 628 634 635 641 642 648 649 655 656 662
663 664 665 666 667 668 669 670 671 685 686 687
688 689 690 691 692 693 694 708 709 710 711 712
713 714 715 716 717 731 732 738 739 745 746 752
753 759 760 766 767 773 774 780 781 787 788 794
795 801 802 808 809 815 816 822 823 829 830 836
837 843 844 850 851 857 858 864 865 871 872 878
879 885 886 892 893 899 900 906 907 913 914 920
921 927 928 934 935 941 942 948 949 955 956 962
963 969 970 976 977
N_ 88 92 340
N_ALL 313 314# 731 745 752 759 766 773 780 787 794 801
808 815 822 829 836 843 850 871 878 885 927 934
PAGE_EN 295
PAR_ERR 244 913 920 927 934
PF 238 315 316
PF_BAD 241 794 795
PF_CODE 316# 759 773 780 787 794 801 808 864
PF_NXM 240 787 788
PF_OK 242 801 802
PF_WT 239 759 780 781 794 801 808
PT_ADR 228 752 753 815 822 829 836 843 850 871 878 885
PT_CAC 232 815 816 822 829 836 843 850 871 878 885 927
934
PT_CLK 289
PT_IO 229 745 746 752 759 773 780 787 794 801 808 815
822 829 836 843 850 857 864 871 878 885 927 934
PT_MESS 315# 745 752 759 773 780 787 794 801 808 815 822
829 836 843 850 857 864 871 878 885 927 934
PT_PAR 233 913 914 920 921
PT_PAR_GEN 243 913 914 920 921
PT_RAM_CAC 236 885 886
PT_RAM_PAG_USR 234 857 858
PT_RAM_PAR 237 920 921
PT_RAM_VAL_WRT 235 864 865
PT_USR 231 745 752 759 773 774 780 787 794 801 808 836
843 857 864
PT_VAL_WRT 230 745 752 759 760 773 780 787 794 801 808 857
864
PXCT 273 941 942 948 949
PXCT_MUX 274 941 942
PXCT_MUX_DPE 275 948 949
RAM_CLK 269
RESET 272
SC 195 406 407 417 418 471 472 533 534 544 545 546
547 548 549
SCADA_44 144 417 418 428 429 432 433 436 437 440 441 444
445
SCADA_BYTE1 145 428 429
SCADA_BYTE2 146 432 433
SCADA_BYTE3 147 436 437
SCADA_BYTE4 148 440 441
SCADA_BYTE5 149 444 445
SCADA_SC 142 406 407 417 418 471 472 533 534 544 545 546
547 548 549
SCADA_SEL_BYTE1 153 430 431
SCADA_SEL_BYTE2 154 434 435
SCADA_SEL_BYTE3 155 438 439
SCADA_SEL_BYTE4 156 442 443
SCADA_SEL_BYTE5 157 446 447
SCADA_SEL_SC 150 408 409 419 420 473 474 535 536
SCADA_SEL_SN 151 383 384 392 393 399 400 408 409 419 420 473
474 484 485 495 496 504 505 511 512 513 514 522
523 524 525 535 536 544 545 546 547 548 549 955
956 962
SCADA_SEL_44 152 419 420 430 431 434 435 438 439 442 443 446
447
SCADA_SN 143 381 382 392 393 399 400 406 407 417 418 471
472 482 483 493 494 504 505 511 512 513 514 522
523 524 525 533 534 544 545 546 547 548 549 588
589 955 956 962
SCADB_EXP 159 504 505
SCADB_FE 158 471 472 533 534 544 545 546 547 548 549
SCADB_SEL_EXP 163
SCADB_SEL_FE 162 473 474 535 536
SCADB_SEL_SHIFT 164 484 485
SCADB_SEL_SIZE 165 495 496
SCADB_SHIFT 160 482 483
SCADB_SIZE 161 493 494
SCAD_A 175 381 382 383 384 406 407 408 409 417 418 419
420 428 429 430 431 432 433 434 435 436 437 438
439 440 441 442 443 444 445 446 447 471 472 473
474 511 512 513 514 522 523 524 525 533 534 535
536 588 589 955 956
SCAD_ADD 172 544 545
SCAD_AND 173 533 534 535 536
SCAD_A_DEC 174 392 393 962
SCAD_A_MUL2 168 399 400
SCAD_OR 169 471 472 473 474 482 483 484 485 493 494 495
496 504 505
SCAD_SUB 171 546 547
SCAD_SUBB 170 548 549
SC_EN 196 408 409 419 420 473 474 535 536 544 545 546
547 548 549 955 956
SC_SIGN 197 955 956
SPEC 219
SPEC_APR 277
SPEC_APR_EN 279
SPEC_MEMCLR 281
SPEC_MEMCLR_BAD 283 794 795
SPEC_MEMCLR_NXM 282 787 788
SPEC_MSEC 284
SPEC_PAGE 285 315 753
SPEC_PREV 276 766 767
SPEC_PXCT 318# 766
SPEC_PXCT_EN 286 318 941 942 948 949
SPEC_PXCT_OFF 280 318 767 941 942 948 949
SPEC_SWEEP 278 559 560 562 564 566 568 570 596 598 600 602
808 836
STOP 220 616 618 627
T10_ES 476# 991
T10_E1 471# 476
T10_E2 473# 477
T10_NE1 472# 478
T10_NE2 474# 479
T10_NES 478# 1057
T11_ES 487# 992
T11_E1 482# 487
T11_E2 484# 488
T11_NE1 483# 489
T11_NE2 485# 490
T11_NES 489# 1058
T12_ES 498# 993
T12_E1 493# 498
T12_E2 495# 499
T12_NE1 494# 500
T12_NE2 496# 501
T12_NES 500# 1059
T13_ES 507# 994
T13_E1 504# 507
T13_NE1 505# 508
T13_NES 508# 1060
T14_ES 516# 995
T14_E1 511# 516
T14_E2 513# 517
T14_NE1 512# 518
T14_NE2 514# 519
T14_NES 518# 1061
T15_ES 527# 996
T15_E1 522# 527
T15_E2 524# 528
T15_NE1 523# 529
T15_NE2 525# 530
T15_NES 529# 1062
T16_ES 538# 997
T16_E1 533# 538
T16_E2 535# 539
T16_NE1 534# 540
T16_NE2 536# 541
T16_NES 540# 1063
T17_ES 551# 998
T17_E1 544# 551
T17_E2 546# 552
T17_E3 548# 553
T17_NE1 545# 554
T17_NE2 547# 555
T17_NE3 549# 556
T17_NES 554# 1064
T18_ES 573# 999
T18_E2 560# 573
T18_E3 562# 574
T18_E4 564# 575
T18_E5 566# 576
T18_E6 568# 577
T18_E7 570# 578
T18_NE1 559# 579
T18_NE2 561# 580
T18_NE3 563# 581
T18_NE4 565# 582
T18_NE5 567# 583
T18_NE6 569# 584
T18_NE7 571# 585
T18_NES 579# 1065
T19_ES 591# 1000
T19_E1 588# 591
T19_NE1 589# 592
T19_NES 592# 1066
T1_E1 348# 353
T1_E2 350# 354
T1_ES 353# 982
T1_NES 355# 1048
T1_NE1 349# 355
T1_NE2 351# 356
T20_ES 605# 1001
T20_E2 596# 605
T20_E3 598# 606
T20_E4 600# 607
T20_E5 602# 608
T20_NE1 595# 609
T20_NE2 597# 610
T20_NE3 599# 611
T20_NE4 601# 612
T20_NE5 603# 613
T20_NES 609# 1067
T21_ES 621# 1002
T21_E1 616# 621
T21_E2 618# 622
T21_NE1 617# 623
T21_NE2 619# 624
T21_NES 623# 1068
T22_ES 630# 1003
T22_E1 627# 630
T22_NE1 628# 631
T22_NES 631# 1069
T23_ES 637# 1004
T23_E1 634# 637
T23_NE1 635# 638
T23_NES 638# 1070
T24_ES 644# 1005
T24_E1 641# 644
T24_NE1 642# 645
T24_NES 645# 1071
T25_ES 651# 1006
T25_E1 648# 651
T25_NE1 649# 652
T25_NES 652# 1072
T26_ES 658# 1007
T26_E1 655# 658
T26_NE1 656# 659
T26_NES 659# 1073
T27_ES 673# 1008
T27_E1 662# 673
T27_E2 664# 674
T27_E3 666# 675
T27_E4 668# 676
T27_E5 670# 677
T27_NE1 663# 678
T27_NE2 665# 679
T27_NE3 667# 680
T27_NE4 669# 681
T27_NE5 671# 682
T27_NES 678# 1074
T28_ES 696# 1009
T28_E1 685# 696
T28_E2 687# 697
T28_E3 689# 698
T28_E4 691# 699
T28_E5 693# 700
T28_NE1 686# 701
T28_NE2 688# 702
T28_NE3 690# 703
T28_NE4 692# 704
T28_NE5 694# 705
T28_NES 701# 1075
T29_ES 719# 1010
T29_E1 708# 719
T29_E2 710# 720
T29_E3 712# 721
T29_E4 714# 722
T29_E5 716# 723
T29_NE1 709# 724
T29_NE2 711# 725
T29_NE3 713# 726
T29_NE4 715# 727
T29_NE5 717# 728
T29_NES 724# 1076
T2_E1 359# 364
T2_E2 361# 365
T2_ES 364# 983
T2_NES 366# 1049
T2_NE1 360# 366
T2_NE2 362# 367
T30_ES 734# 1011
T30_E1 731# 734
T30_NE1 732# 735
T30_NES 735# 1077
T31_ES 741# 1012
T31_E1 738# 741
T31_NE1 739# 742
T31_NES 742# 1078
T32_ES 748# 1013
T32_E1 745# 748
T32_NE1 746# 749
T32_NES 749# 1079
T33_ES 755# 1014
T33_E1 752# 755
T33_NE1 753# 756
T33_NES 756# 1080
T34_ES 762# 1015
T34_E1 759# 762
T34_NE1 760# 763
T34_NES 763# 1081
T35_ES 769# 1016
T35_E1 766# 769
T35_NE1 767# 770
T35_NES 770# 1082
T36_ES 776# 1017
T36_E1 773# 776
T36_NE1 774# 777
T36_NES 777# 1083
T37_ES 783# 1018
T37_E1 780# 783
T37_NE1 781# 784
T37_NES 784# 1084
T38_ES 790# 1019
T38_E1 787# 790
T38_NE1 788# 791
T38_NES 791# 1085
T39_ES 797# 1020
T39_E1 794# 797
T39_NE1 795# 798
T39_NES 798# 1086
T3_E1 370# 375
T3_E2 372# 376
T3_ES 375# 984
T3_NES 377# 1050
T3_NE1 371# 377
T3_NE2 373# 378
T40_ES 804# 1021
T40_E1 801# 804
T40_NE1 802# 805
T40_NES 805# 1087
T41_ES 811# 1022
T41_E1 808# 811
T41_NE1 809# 812
T41_NES 812# 1088
T42_ES 818# 1023
T42_E1 815# 818
T42_NE1 816# 819
T42_NES 819# 1089
T43_ES 825# 1024
T43_E1 822# 825
T43_NE1 823# 826
T43_NES 826# 1090
T44_ES 832# 1025
T44_E1 829# 832
T44_NE1 830# 833
T44_NES 833# 1091
T45_ES 839# 1026
T45_E1 836# 839
T45_NE1 837# 840
T45_NES 840# 1092
T46_ES 846# 1027
T46_E1 843# 846
T46_NE1 844# 847
T46_NES 847# 1093
T47_ES 853# 1028
T47_E1 850# 853
T47_NE1 851# 854
T47_NES 854# 1094
T48_ES 860# 1029
T48_E1 857# 860
T48_NE1 858# 861
T48_NES 861# 1095
T49_ES 867# 1030
T49_E1 864# 867
T49_NE1 865# 868
T49_NES 868# 1096
T4_E1 381# 386
T4_E2 383# 387
T4_ES 386# 985
T4_NES 388# 1051
T4_NE1 382# 388
T4_NE2 384# 389
T50_ES 874# 1031
T50_E1 871# 874
T50_NE1 872# 875
T50_NES 875# 1097
T51_ES 881# 1032
T51_E1 878# 881
T51_NE1 879# 882
T51_NES 882# 1098
T52_ES 888# 1033
T52_E1 885# 888
T52_NE1 886# 889
T52_NES 889# 1099
T53_ES 895# 1034
T53_E1 892# 895
T53_NE1 893# 896
T53_NES 896# 1100
T54_ES 902# 1035
T54_E1 899# 902
T54_NE1 900# 903
T54_NES 903# 1101
T55_ES 909# 1036
T55_E1 906# 909
T55_NE1 907# 910
T55_NES 910# 1102
T56_ES 916# 1037
T56_E1 913# 916
T56_NE1 914# 917
T56_NES 917# 1103
T57_ES 923# 1038
T57_E1 920# 923
T57_NE1 921# 924
T57_NES 924# 1104
T58_ES 930# 1039
T58_E1 927# 930
T58_NE1 928# 931
T58_NES 931# 1105
T59_ES 937# 1040
T59_E1 934# 937
T59_NE1 935# 938
T59_NES 938# 1106
T5_E1 392# 395
T5_ES 395# 986
T5_NES 396# 1052
T5_NE1 393# 396
T60_ES 944# 1041
T60_E1 941# 944
T60_NE1 942# 945
T60_NES 945# 1107
T61_ES 951# 1042
T61_E1 948# 951
T61_NE1 949# 952
T61_NES 952# 1108
T62_ES 958# 1043
T62_E1 955# 958
T62_NE1 956# 959
T62_NES 959# 1109
T63_ES 965# 1044
T63_E1 962# 965
T63_NE1 963# 966
T63_NES 966# 1110
T64_ES 972# 1045
T64_E1 969# 972
T64_NE1 970# 973
T64_NES 973# 1111
T65_ES 979# 1046
T65_E1 976# 979
T65_NE1 977# 981
T65_NES 981# 1112
T6_E1 399# 402
T6_ES 402# 987
T6_NES 403# 1053
T6_NE1 400# 403
T7_E1 406# 411
T7_E2 408# 412
T7_ES 411# 988
T7_NES 413# 1054
T7_NE1 407# 413
T7_NE2 409# 414
T8_E1 417# 422
T8_E2 419# 423
T8_ES 422# 989
T8_NES 424# 1055
T8_NE1 418# 424
T8_NE2 420# 425
T9_E1 428# 449
T9_E10 446# 458
T9_E2 430# 450
T9_E3 432# 451
T9_E4 434# 452
T9_E5 436# 453
T9_E6 438# 454
T9_E7 440# 455
T9_E8 442# 456
T9_E9 444# 457
T9_ES 449# 990
T9_NES 459# 1056
T9_NE1 429# 459
T9_NE10 447# 468
T9_NE2 431# 460
T9_NE3 433# 461
T9_NE4 435# 462
T9_NE5 437# 463
T9_NE6 439# 464
T9_NE7 441# 465
T9_NE8 443# 466
T9_NE9 445# 467
TESTS_FAILED 1250
TEST_DISP 1182#
TRAP_EN 294
TST1 1115* 1182
TST10 1124 1191
TST11 1125 1192
TST12 1126 1193
TST13 1127 1194
TST14 1128 1195
TST15 1129 1196
TST16 1130 1197
TST17 1131 1198
TST18 1132 1199
TST19 1133 1200
TST2 1116 1183
TST20 1134 1201
TST21 1135 1202
TST22 1136 1203
TST23 1137 1204
TST24 1138 1205
TST25 1139 1206
TST26 1140 1207
TST27 1141 1208
TST28 1142 1209
TST29 1143 1210
TST3 1117 1184
TST30 1144 1211
TST31 1145 1212
TST32 1146 1213
TST33 1147 1214
TST34 1148 1215
TST35 1149 1216
TST36 1150 1217
TST37 1151 1218
TST38 1152 1219
TST39 1153 1220
TST4 1118 1185
TST40 1154 1221
TST41 1155 1222
TST42 1156 1223
TST43 1157 1224
TST44 1158 1225
TST45 1159 1226
TST46 1160 1227
TST47 1161 1228
TST48 1162 1229
TST49 1163 1230
TST5 1119 1186
TST50 1164 1231
TST51 1165 1232
TST52 1166 1233
TST53 1167 1234
TST54 1168 1235
TST55 1169 1236
TST56 1170 1237
TST57 1171 1238
TST58 1172 1239
TST59 1173 1240
TST6 1120 1187
TST60 1174 1241
TST61 1175 1242
TST62 1176 1243
TST63 1177 1244
TST64 1178 1245
TST65 1179 1246
TST7 1121 1188
TST8 1122 1189
TST9 1123 1190
VMA 191 312 313 559 570 571
VMA_ALL_DP 312#
VMA_ALL_N 313# 315 616 618 627 634 641 648 655 731 738
VMA_CYCLE_DP 186 312 559 568 569
VMA_CYCLE_N 187 313 595 602 603
VMA_EN 217 312 313 766
VMA_FETCH_DP 184 559 562 563
VMA_FETCH_N 185 595 598 599
VMA_PHYS_DP 182 312 559 564 565
VMA_PHYS_N 183 313 595 600 601
VMA_PREV_DP 180 312 317 559 566 567 767
VMA_PREV_N 181 313 317 767
VMA_SWEEP 188 560 562 564 566 568 570 596 598 600 602 808
836
VMA_SWEEP_CD 189 836 837
VMA_SWEEP_PT 190 808 809
VMA_USER_DP 178 312 317 559 560 561 767
VMA_USER_N 179 313 317 595 596 597 767
VMA_USER_PREV 317# 766
W_ 73 82 83 106 330
X 98 101 102
TIME: 4 SEC.
CORE: 14K