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.TITLE	"KL10 PAGING DIAGNOSTIC MICRO-CODE"

.TOC	"HOW TO READ THE MICROCODE -- FORMATS & CONSTRUCTS"

;(1)	FIELD DEFINITIONS
;	THESE OCCUR AT THE BEGINNING OF THE LISTING, IN THE SOURCE FILE
; DEFINE.MIC (CONTROL AND DISPATCH RAM DEFINITIONS).
; THEY HAVE THE FORM:
;	SYMBOL/=J,K,L,M
;	THE FIRST PARAMETER (J) IS MEANINGFUL ONLY WHEN "D" IS SPECIFIED
; AS THE DEFAULT MECHANISM, AND IN THAT CASE, GIVES THE DEFAULT VALUE OF
; THE FIELD IN OCTAL.
;	THE SECOND PARAMETER (K) GIVES THE FIELD SIZE IN (DECIMAL) NUMBER
; OF BITS.
;	THE THIRD PARAMETER (L) GIVES THE FIELD POSITION IN DECIMAL
; AS THE BIT NUMBER OF THE RIGHTMOST BIT OF THE FIELD.  BITS ARE NUMBERED
; FROM 0 ON THE LEFT.  NOTE THAT THE POSITION OF BITS IN THE MICROWORD
; SHOWN IN THE LISTING BEARS NO RELATION TO THE ORDERING OF BITS IN THE
; HARDWARE MICROWORD, WHERE FIELDS ARE OFTEN BROKEN UP AND SCATTERED.
;	THE FOURTH PARAMETER (M) IS OPTIONAL, AND SELECTS A DEFAULT
; MECHANISM FOR THE FIELD.  THE LEGAL VALUES OF THIS PARAMETER ARE THE
; CHARACTERS "D", "T", "P", OR "+".
;	  "D" MEANS J IS THE DEFAULT VALUE OF THE FIELD IF NO EXPLICIT
;	VALUE IS SPECIFIED.
;	  "T" IS USED ON THE TIME FIELD TO SPECIFY THAT THE VALUE OF THE
;	FIELD DEPENDS ON THE TIME PARAMETERS SELECTED FOR OTHER FIELDS.
;	[THIS NEEDS A MUCH BETTER EXPLANATION]
;	  "P" IS USED ON THE PARITY FIELD TO SPECIFY THAT THE VALUE OF THE
;	FIELD SHOULD DEFAULT SUCH THAT PARITY OF THE ENTIRE WORD
;	IS ODD.  IF THIS OPTION IS SELECTED ON A FIELD WHOSE SIZE (K) IS
;	ZERO, THE MICRO ASSEMBLER WILL ATTEMPT TO FIND A BIT SOMEWHERE
;	IN THE WORD FOR WHICH NO VALUE IS SPECIFIED OR DEFAULTED.
;	  "+" IS USED ON THE JUMP ADDRESS FIELD TO SPECIFY THAT THE DEFAULT
;	JUMP ADDRESS IS THE ADDRESS OF THE NEXT INSTRUCTION ASSEMBLED (NOT,
;	IN GENERAL, THE CURRENT LOCATION +1).
;	IN GENERAL, A FIELD CORRESPONDS TO THE SET OF BITS WHICH PROVIDE
; SELECT INPUTS FOR MIXERS OR DECODERS, OR CONTROLS FOR ALU'S.
; EXAMPLES:
;	AR/=0,3,26,D
;	THE MICROCODE FIELD WHICH CONTROLS THE AR MIXER (AND THEREFORE
; THE DATA TO BE LOADED INTO AR ON EACH EBOX CLOCK) IS THREE BITS WIDE
; AND THE RIGHTMOST BIT IS SHOWN IN THE LISTING AS BIT 26 OF THE
; MICROINSTRUCTION.  IF NO VALUE IS SPECIFICALLY REQUESTED FOR THE FIELD,
; THE MICROASSEMBLER WILL ENSURE THAT THE FIELD IS 0.
;	AD/=0,6,17
;	THE FIELD WHICH CONTROLS THE AD IS 6 BITS WIDE, ENDING ON
; BIT 17.  THE FOURTH PARAMETER OF THE FIELD IS OMITTED, SO THE FIELD
; IS AVAILABLE TO THE MICROASSEMBLER (IF NO VALUE IS EXPLICITLY
; CALLED OUT FOR THE FIELD) FOR MODIFICATION TO ENSURE ODD PARITY IN THE
; ENTIRE WORD.

;(2)	VALUE DEFINITIONS
;	FOLLOWING A FIELD DEFINITION, SYMBOLS MAY BE CREATED IN THAT
; FIELD TO CORRESPOND TO VALUES OF THE FIELD.  THE FORM IS:
;	SYMBOL=N,T1,T2
;	"N" IS, IN OCTAL, THE VALUE OF SYMBOL WHEN USED IN THE FIELD.
; T1 AND T2 ARE OPTIONAL, AND SPECIFY PARAMETERS IN THE TIME FIELD
; CALCULATION FOR MICROINSTRUCTIONS IN WHICH THIS FIELD/SYMBOL IS USED.
; the microassembler computes the sums of all the t1's and all the t2's
; specified for field/symbol specifications in a word, and uses the max
; of the two sums as the default value for the field whose default
; mechanism is "t".  EXAMPLES:
;	AD/=0,6,17	;FIELD DEFINITION IN WHICH FOLLOWING SYMBOLS EXIST
;	XOR=31
;	A+B=6,1
;	HERE THE SYMBOLS "XOR" AND "A+B" ARE DEFINED FOR THE "AD" FIELD.
; TO THE ASSEMBLER, THEREFORE, WRITING "AD/XOR" MEANS PUT THE VALUE 31
; INTO THE 6-BIT FIELD ENDING ON BIT 17 OF THE MICROWORD.  THE SYMBOLS
; ARE CHOSEN FOR MNEMONIC SIGNIFICANCE, OF COURSE, SO ONE READING
; THE MICROCODE WOULD INTERPRET "AD/XOR" AS "THE OUTPUT OF AD SHALL BE THE
; EXCLUSIVE OR OF ITS A AND B INPUTS".  SIMILIARLY, "AD/A+B" IS READ AS
; "AD PRODUCES THE SUM OF A AND B".  THE SECOND PARAMETER IN THE DEFINITION
; OF "A+B" IS A CONTROL TO THE MICRO ASSEMBLER'S TIME-FIELD CALCULATION,
; WHICH TELLS THE ASSEMBLER THAT THIS OPERATION TAKES LONGER THAN THE
; BASIC CYCLE, AND THEREFORE THAT THE TIME FIELD SHOULD BE INCREASED.
;	AR/=0,3,26,D	;FIELD DEFINITION FOR FOLLOWING SYMBOLS
;	AR=0
;	AD=2
;	HERE THE SYMBOLS "AR" AND "AD" ARE DEFINED FOR THE FIELD NAMED
; "AR", WHICH CONTROLS THE AR MIXER.  WE COULD WRITE AR/AR TO MEAN THAT
; THE AR MIXER SELECT INPUTS WOULD BE 0, WHICH IN THE 
; HARDWARE SELECTS THE AR OUTPUT FOR RECIRCULATION TO THE REGISTER.  IN
; PRACTICE, HOWEVER, WE WANT THIS TO BE THE DEFAULT CASE, SO THAT AR
; DOES NOT CHANGE UNLESS WE SPECIFICALLY REQUEST IT, SO THE FIELD
; DEFINITION SPECIFIES 0 AS THE DEFAULT VALUE OF THE FIELD.  IF WE
; WANT AR LOADED FROM THE AD OUTPUT, WE WRITE "AR/AD" TO SET THE
; MIXER SELECTS TO PASS THE AD OUTPUT INTO THE AR.
;
;(3)	LABEL DEFINITIONS
;	A MICRO INSTRUCTION MAY BE LABELLED BY A SYMBOL FOLLOWED BY COLON
; PRECEDING THE MICROINSTRUCTION DEFINITION.  THE ADDRESS OF THE
; MICROINSTRUCTION BECOMES THE VALUE OF THE SYMBOL IN THE FIELD NAMED "J".
; EXAMPLE:
;	FOO:	J/FOO
;	THIS IS A MICROINSTRUCTION WHOSE "J" FIELD (JUMP ADDRESS) CONTAINS
; THE VALUE "FOO".  IT ALSO DEFINES THE SYMBOL "FOO" TO BE THE ADDRESS
; OF ITSELF.  THEREFORE, IF EXECUTED BY THE MICROPROCESSOR, IT WOULD
; LOOP ON ITSELF.
;
;(4)	COMMENTS
;	A SEMICOLON ANYWHERE ON A LINE CAUSES THE REST OF THE LINE
; TO BE IGNORED BY THE ASSEMBLER.  THIS TEXT IS AN EXAMPLE OF COMMENTS.

;(5)	MICROINSTRUCTION DEFINITION
;	A WORD OF MICROCODE IS DEFINED BY SPECIFYING A FIELD NAME,
; FOLLOWED BY SLASH (/), FOLLOWED BY A VALUE.  THE VALUE MAY BE A
; SYMBOL DEFINED FOR THAT FIELD, AN OCTAL DIGIT STRING, OR A DECIMAL
; DIGIT STRING (DISTINGUISHED BY THE FACT THAT IT CONTAINS "8" AND/OR
; "9" AND/OR IS TERMINATED BY A PERIOD). SEVERAL FIELDS MAY BE SPECIFIED
; IN ONE MICROINSTRUCTION BY SEPARATING FIELD/VALUE SPECIFICATIONS WITH
; COMMAS.  EXAMPLE:
;	ADB/BR,ADA/AR,AD/A+B,AR/AD
;	THE FIELD NAMED "ADB" IS GIVEN THE VALUE NAMED "BR" (TO
; CAUSE THE MIXER ON THE B SIDE OF AD TO SELECT BR), FIELD "ADA" HAS VALUE
; "AR", FIELD "AD" HAS VALUE "A+B", AND FIELD "AR" HAS VALUE "AD".
;
;(6)	CONTINUATION
;	THE DEFINITION OF A MICROINSTRUCTION MAY CONTINUED ONTO TWO OR
; MORE LINES BY BREAKING IT AFTER ANY COMMA.  IN OTHER WORDS, IF THE
; LAST NON-BLANK, NON-COMMENT CHARACTER ON A LINE IS A COMMA, THE
; INSTRUCTION SPECIFICATION IS CONTINUED ON THE FOLLOWING LINE.
; EXAMPLE:
;	ADB/BR,ADA/AR,		;SELECT AR & BR AS AD INPUTS
;		AD/A+B,AR/AD	;TAKE THE SUM INTO AR
; BY CONVENTION, CONTINUATION LINES ARE INDENTED AN EXTRA TAB.
;
;(7)	MACROS
;	A MACRO IS A SYMBOL WHOSE VALUE IS ONE OR MORE FIELD/VALUE
; SPECIFICATIONS AND/OR MACROS.  A MACRO DEFINITION IS A LINE CONTAINING
; THE MACRO NAME FOLLOWED BY A QUOTED STRING WHICH IS THE VALUE OF THE
; MACRO.  EXAMPLE:
;	AR_AR+BR	"ADB/BR,ADA/AR,AD/A+B,AR/AD"
; THE APPEARANCE OF A MACRO IN A MICROINSTRUCTION DEFINITION IS EQUIVALENT
; TO THE APPEARANCE OF ITS VALUE.  MACROS FOR VARIOUS FUNCTIONS
; ARE DEFINED IN "MACRO.MIC".
;
;(8)	CONDITIONAL ASSEMBLY
;	THE MICROCODE ASSEMBLER DOES NOT INCLUDE CONDITIONAL ASSEMBLY
;FACILITIES, BUT THERE IS A SNOBOL PROGRAM WHICH HAS BEEN USED FOR THAT
;PURPOSE BY INSERTING AND REMOVING SEMICOLONS AT APPROPRIATE PLACES.  IT
;PROCESSES COMMANDS OF THE FORM:
;	;;SET SWITCH ON			;DEFINES SWITCH VALUE
;	;;IF SWITCH ASSEMBLE		;PERFORMS CONDITIONAL ASSEMBLY
;	;;END SWITCH			;ENDS CONDITIONAL ASSEMBLY
;
;(9)	PSEUDO OPS
;	THE MICRO ASSEMBLER HAS 4 PSEUDO-OPERATORS:
;.DCODE AND .UCODE SELECT THE RAM INTO WHICH SUBSEQUENT MICROCODE WILL
;BE LOADED, AND THEREFORE THE FIELD DEFINITIONS AND MACROS WHICH ARE
;MEANINGFUL IN SUBSEQUENT MICROCODE
;.TITLE DEFINES A STRING OF TEXT TO APPEAR IN THE PAGE HEADER, AND
;.TOC DEFINES AN ENTRY FOR THE TABLE OF CONTENTS AT THE BEGINNING.

;(10)	LOCATION CONTROL
;	A MICROINSTRUCTION "LABELLED" WITH A NUMBER IS ASSIGNED TO THAT
; ADDRESS.
;	THE CHARACTER "=" AT THE BEGINNING OF A LINE, FOLLOWED BY
; A STRING OF 0'S, 1'S, AND/OR *'S, SPECIFIES A CONSTRAINT ON THE
; ADDRESS OF FOLLOWING MICROINSTRUCTIONS.  THE NUMBER OF CHARACTERS
; IN THE CONSTRAINT STRING (EXCLUDING THE "=") IS THE NUMBER OF LOW-ORDER
; BITS CONSTRAINED IN THE ADDRESS.  THE MICROASSEMBLER ATTEMPTS TO FIND
; AN UNUSED LOCATION WHOSE ADDRESS HAS 0 BITS IN THE POSITIONS
; CORRESPONDING TO 0'S IN THE CONSTRAINT STRING AND 1 BITS WHERE THE
; CONSTRAINT HAS 1'S.  ASTERISKS DENOTE "DON'T CARE" BIT POSITIONS.
;	IF THERE ARE ANY 0'S IN THE CONSTRAINT STRING, THE CONSTRAINT
; IMPLIES A BLOCK OF <2**N> MICROWORDS, WHERE N IS THE NUMBER OF 0'S
; IN THE STRING.  ALL LOCATIONS IN THE BLOCK WILL HAVE 1'S IN THE ADDRESS
; BITS CORRESPONDING TO 1'S IN THE STRING, AND BIT POSITIONS DENOTED BY *'S
; WILL BE THE SAME IN ALL LOCATIONS OF THE BLOCK.
;	IN SUCH A CONSTRAINT BLOCK, THE DEFAULT ADDRESS PROGRESSION IS
; COUNTING IN THE "0" POSITIONS OF THE CONSTRAINT STRING, BUT A NEW
; CONSTRAINT STRING OCCURING WITHIN A BLOCK MAY FORCE SKIPPING OVER
; SOME LOCATIONS OF THE BLOCK.  WITHIN A BLOCK, A NEW CONSTRAINT
; STRING DOES NOT CHANGE THE PATTERN OF DEFAULT ADDRESS PROGRESSION, IT
; MERELY ADVANCES THE LOCATION COUNTER OVER THOSE LOCATIONS.  THE
; MICROASSEMBLER WILL LATER FILL THEM IN.
;	A NULL CONSTRAINT STRING ("=" FOLLOWED BY ANYTHING BUT "0",
; "1", OR "*") SERVES TO TERMINATE A CONSTRAINT BLOCK.
; EXAMPLES:
;	=0	
;	THIS SPECIFIES THAT THE LOW-ORDER ADDRESS BIT MUST BE ZERO--
; THE MICROASSEMBLER FINDS AN EVEN-ODD PAIR OF LOCATIONS, AND PUTS
; THE NEXT TWO MICROINSTRUCTIONS INTO THEM.
;	=11
;	THIS SPECIFIES THAT THE TWO LOW-ORDER BITS OF THE ADDRESS MUST
; BOTH BE ONES.  SINCE THERE ARE NO 0'S IN THIS CONSTRAINT, THE
; ASSEMBLER FINDS ONLY ONE LOCATION MEETING THE CONSTRAINT.
;	=0*****
;	THIS SPECIFIES AN ADDRESS IN WHICH THE "40" BIT IS ZERO.  DUE
; TO THE IMPLEMENTATION OF THIS FEATURE IN THE ASSEMBLER,  THE DEFAULT
; ADDRESS PROGRESSION APPLIES ONLY TO THE LOW-ORDER 5 BITS, SO THIS
; CONSTRAINT FINDS ONE WORD IN WHICH THE "40" BIT IS ZERO, AND DOES
; NOT ATTEMPT TO FIND ONE IN WHICH THAT BIT IS A ONE.

.TOC	"MICROCODE LISTING TEMPLATE"
;HERE IS A TEMPLATE WHICH CAN BE USED WITH THE MICROCODE
; LISTING TO IDENTIFY FIELDS IN THE OUTPUT --


; ----  ---- ---- ---- ---- ---- ---- ----
; [--]  [--] []!! !!!! !!!! !![] [][] ![-]
;   !     !   !!! !!!! !!!! !! !  ! ! ! + # = MAGIC NUMBERS
;   !     !   !!! !!!! !!!! !! !  ! ! + MARK = SCOPE SYNC
;   !     !   !!! !!!! !!!! !! !  ! !
;   !     !   !!! !!!! !!!! !! !  ! + DISP/SPEC = SPECIAL FUNCTIONS
;   !     !   !!! !!!! !!!! !! !  + SKIP/COND = SPECIAL FUNCTIONS
;   !     !   !!! !!!! !!!! !! !
;   !     !   !!! !!!! !!!! !! + TIME, MEM = UINST TIME & MEM FUNCTION
;   !     !   !!! !!!! !!!! !+ VMA = VMA INPUT SELECT
;   !     !   !!! !!!! !!!! + SH/ARMM = SH FUNCTION / ARMM SELECT
;   !     !   !!! !!!! !!!!
;   !     !   !!! !!!! !!!+ SC, FE = SC INPUT SELECT & FE LOAD
;   !     !   !!! !!!! !!+ SCADB = SELECT FOR SCAD "B" INPUT
;   !     !   !!! !!!! !+ SCADA = ENABLE AND SELECT FOR SCAD "A" INPUT
;   !     !   !!! !!!! + SCAD = SC/FE ADDER FUNCTION
;   !     !   !!! !!!!
;   !     !   !!! !!!+ FM ADR = FAST MEMORY ADDRESS SELECT
;   !     !   !!! !!+ BR, BRX, MQ = LOAD BR & BRX, SEL FOR MQ
;   !     !   !!! !+ ARX = SELECT FOR ARX INPUT
;   !     !   !!! + AR = SELECT FOR AR INPUT
;   !     !   !!!
;   !     !   !!+ ADB = SELECT FOR ADDER "B" INPUT
;   !     !   !+ ADA = SELECT AND ENABLE FOR ADDER "A" INPUT
;   !     !   + AD = OPERATION IN ADDER AND ADDER EXTENSION
;   !     !
;   !     + J = BASE ADDRESS TO WHICH THIS MICROINSTRUCTION JUMPS
;   !
;   + LOCATION IN CRAM INTO WHICH THIS WORD IS LOADED
;
; U/V = MICRO INSTRUCTION FOR CRAM

;*******************************************************************

; D = WORD FOR DRAM
;
;   + LOCATION IN DRAM INTO WHICH THIS WORD IS LOADED
;   !
;   !   + A = OPERAND ACCESS CONTROL
;   !   !+ B = INSTRUCTION "MODE"
;   !   !! + P = PARITY FOR THIS WORD
;   !   !! !
;   !   !! !   + J = ADDRESS OF HANDLER FOR THIS INSTRUCTION
; [--]  !! ! [--]
; ----  ---- ----

.TOC	"CONTROL RAM DEFINITIONS -- AD"

;FIELDS ARRANGED FOR READABILITY, NOT COMPACTNESS
; IN THE PROCESSOR, BITS ARE SCATTERED IN ANOTHER ORDER

U0/=0,1,0,D	;BIT 0 UNUSED
J/=0,11,11,+	;SYMBOLS WILL BE DEFINED BY TAGS (CRA1&CRA2)

;MAIN ADDER CONTROLS

AD/=0,6,17	; (EDP3, EXCEPT CARRY IN, ON CTL1)
		;BIT 0 = CARRY IN, BIT 1 = BOOLE
		;BITS 2-5 = S8-S1 OF 10181 ALU
		;ARITHMETIC, AD AND ADX SEPARATED
	A+1=40,1
	A+XCRY=00,1
	A*2=03,1
	A*2+1=43,1
	A+B=06,1
	A+B+1=46,1
	ORCB+1=50,1
	A-B-1=11,1
	A-B=51,1
	XCRY-1=54,1
	A-1=17,1
		;72 BIT ARITHMETIC REQUIRES SPEC/AD LONG
		; MANY OTHER "ARITHMETIC" FUNCTIONS EXIST, BUT ARE
		; NOT GIVEN SYMBOLS BECAUSE NO USE COULD BE FOUND FOR THEM
		;ADDER LOGICAL FUNCTIONS
	SETCA=20
	ORC=21		;NAND
	ORCA=22
	1S=23
	ANDC=24		;NOR
	SETCB=25
	EQV=26
	ORCB=27
	ANDCA=30
	XOR=31
	B=32
	OR=33
	0S=34
	ANDCB=35
	AND=36
	A=37
		;BOOLEAN FUNCTIONS FOR WHICH CRY0 IS INTERESTING
	CRY A EQ -1=60	;GENERATE CRY0 IF A=1S, AD=SETCA
	CRY A.B#0=36	;CRY 0 IF A&B NON-ZERO, AD=AND
	CRY A#0=37	;GENERATE CRY0 IF A .NE. 0, AD=A
	CRY A GE B=71	;CRY0 IF A .GE. B, UNSIGNED; AD=XOR

.TOC	"CONTROL RAM DEFINITIONS -- DATA PATH MIXERS"

ADA/=0,3,20		; (EDP3)
	AR=0
	ARX=1
	MQ=2
	PC=3
ADA EN/=0,1,18		;ADA ENABLE ALSO ENABLES ADXA (EDP3)
	EN=0
	0S=1
U21/=0,1,21,D	;BIT 21 UNUSED
ADB/=0,2,23		;CONTROLS ADB AND ADXB (EDP3)
	FM=0
	BR*2=1
	BR=2
	AR*4=3
U23/=1,1,23,D	;PREVENT DEFAULT SELECTION OF FM
AR/=0,3,26,D		; (EDP1)
	AR=0
	ARMM=0		;REQUIRES SPECIAL FUNCTION
	CACHE=1		;ORDINARILY SELECTED BY HWARE
	AD=2
	EBUS=3
	SH=4
	AD*2=5
	ADX=6
	AD*.25=7
ARX/=0,3,29,D		; (EDP2)
;	ARX=0		;BY DEFAULT
	CACHE=1		;ORDINARILY BY MBOX RESP
	AD=2
	MQ=3
	SH=4
	ADX*2=5
	ADX=6
	ADX*.25=7
BR/=0,1,30,D		;DEFAULT TO RECIRCULATE (EDP4)
	AR=1
BRX/=0,1,31,D		;DEFAULT TO RECIRCULATE (EDP4)
	ARX=1
MQ/=0,1,32,D		;DEFAULT TO RECIRCULATE (EDP2)
	SH=1		;LOAD FROM SHIFT MATRIX
	MQ*2=0		;WITH SPEC/MQ SHIFT
	MQ*.25=1	;WITH SPEC/MQ SHIFT
	MQ SEL=0	;WITH COND/REG CTL
	MQM SEL=1	;WITH COND/REG CTL
FMADR/=0,3,35		; (APR4&APR5)
	AC0=0		;IR 9-12
	AC1=1		;<IR 9-12>+1 MOD 16
	XR=2		;ARX 14-17
	VMA=3		;VMA 32-35
	AC2=4		;<IR 9-12>+2 MOD 16
	AC3=5		;<IR 9-12>+3 MOD 16
	CB#=6		;IN CURRENT BLOCK, AC SELECTED BY MAGIC # FIELD
	#B#=7		;BLOCK AND AC SELECTED BY # FIELD

.TOC	"CONTROL RAM DEFINITIONS -- 10-BIT LOGIC"

SCAD/=0,3,38		; (SCD1)
	A=0
	A-B-1=1
	A+B=2
	A-1=3
	A+1=4
	A-B=5
	OR=6
	AND=7
SCADA/=0,3,41		; (SCD1)
	FE=0
	AR0-5=1		;BYTE POINTER P FIELD
	AR EXP=2	;<AR 01-08> XOR <AR 00>
	#=3		;SIGN EXTENDED WITH #00
SCADA EN/=0,1,39	; (SCD1)
	0S=1
U42/=0,1,42,D	;BIT 42 UNUSED
SCADB/=0,2,44		; (SCD1)
	SC=0
	AR6-11=1	;BYTE POINTER S FIELD
	AR0-8=2
	#=3		;NO SIGN EXTENSION
U45/=0,1,45,D	;BIT 45 UNUSED
SC/=0,1,46,D		;RECIRCULATE BY DEFAULT (SCD2)
	FE=0		;WITH SCM ALT
	SCAD=1
	AR SHIFT=1	;WITH SCM ALT ;AR 18, 28-35
FE/=0,1,47,D		;RECIRCULATE BY DEFAULT (SCD2)
	SCAD=1
U48/=0,1,48,D	;BIT 48 UNUSED
		;OTHER COMPLEX FUNCTIONS
SH/=0,2,50		; (SH1)
	SHIFT AR!ARX=0	;LEFT BY (SC)
	AR=1
	ARX=2
	AR SWAP=3	;HALVES SWAPPED
ARMM/=0,2,50		;SAME BITS AS SH CONTROL (SCD3)
	#=0		;MAGIC # 0-8 TO AR 0-8
	EXP_SIGN=1	;AR1-8 _ AR0
	SCAD EXP=2	;AR0-8_SCAD
	SCAD POS=3	;AR0-5_SCAD
U51/=0,1,51,D	;BIT 51 UNUSED
VMA/=0,2,53,D		;ALSO CONTROLLED BY SPECIAL FUNCTIONS
	VMA=0		;BY DEFAULT
	PC=1
	PC+1=2
	AD=3
TIME/=0,2,55,T		;CONTROLS MINIMUM MICROINSTRUCTION EXECUTION
			; TIME, COUNTING MBOX CLOCK TICKS (CLK)
			;ASSEMBLER GENERALLY TAKES CARE OF THIS
	2T=0		;2 TICKS
	3T=1		;3 TICKS
	4T=2		;4 TICKS
	5T=3		;5 TICKS (COND/DIAG FUNC & #00, --> .5 USEC)

.TOC	"CONTROL RAM DEFINITIONS -- MEM SPECIAL FUNCTIONS"

MEM/=0,4,59,D		; (MCL1)
;	NOP=0		;DEFAULT
	ARL IND=1	;CONTROL AR LEFT MUX FROM # FIELD
	MB WAIT=2	;WAIT FOR MBOX RESP IF PENDING
	SEC 0=3		;CLEAR VMAX
	A RD=4		;OPERAND READ
	B WRITE=5	;CONDITIONAL WRITE ON DRAM B 01
	FETCH=6		;LOAD NEXT INSTR TO ARX (CONTROL BY #)
	REG FUNC=7	;MBOX REGISTER FUNCTIONS
	A IND=10	;A-TYPE INDIRECT
	BYTE IND=11	;BYTE-TYPE INDIRECT
	LOAD AR=12
	LOAD ARX=13
	AD FUNC=14	;FUNCTION FROM AD LEFT
	BYTE RD=15	;BYTE READ TO BOTH AR AND ARX
	WRITE=16	;FROM AR TO MEMORY
	RPW=17		;LOAD AR WITH RPW CYCLE

SKIP/=0,6,65,D		;MICRO-PROGRAM SKIPS
			; 40-57 DECODED ON (CRA2)
;	SPARE=40
	even par=41	;ar parity is even
	BR0=42		;BR BIT 00
	ARX0=43		;ARX BIT 00
	AR18=44		;AR BIT 18
	AR0=45		;AR BIT 00
	AC#0=46		;IR9-12 .EQ. 0
	sc0=47		;sc bit 00
	SC .LT. 36=50
	SCAD0=51,,1	;SIGN OF SCAD OUTPUT
	SCAD#0=52,,1	;SCAD OUTPUT IS NON-ZERO
	ADX0=53,,1	;ADDER EXTENSION BIT 00
	AD CRY0=54,1	;CARRY OUT OF AD BIT -2 (BOOLE IGNORED)
	AD0=55,,1	;ADDER BIT 00
	AD#0=56,,1	;AD BITS 00-35 CONTAIN SOME ONES
;	SPARE=57
			; 60-77 DECODED ON (CON2)
	FETCH=60	;MCL VMA FETCH
	KERNEL=61	;PC IS IN KERNEL MODE
	USER=62		;PC IS IN USER MODE
	PUBLIC=63	;PC IS PUBLIC (INCLUDING SUPER)
	rpw ref=64	;middle of read-pause-write cycle
	PI CYCLE=65	;PI CYCLE IN PROGRESS
	-EBUS GRANT=66	;PI HASN'T RELEASED BUS FOR CPU USE
	-EBUS XFER=67	;NO TRANSFER RECIEVED FROM DEVICE
	INTRPT=70	;AN INTERRUPT REQUEST WAITING FOR SERVICE
	-START=71	;NO CONTINUE BUTTON
	RUN=72		;PROCESSOR NOT HALTED
	IO LEGAL=73	;KERNEL, PI CYCLE, USER IOT, OR DEVICE .GE. 740
	P!S XCT=74	;PXCT OR SXCT
	EBOX PF=75	;EBOX SHOULD HANDLE THIS PAGE FAIL
	AC REF=76	;VMA .LT. 20 ON READ OR WRITE
	-MTR REQ=77	;INTERRUPT REQUEST NOT DUE TO METER

.TOC	"CONTROL RAM DEFINITIONS -- COND SPECIAL FUNCTIONS"
;SKIP/COND FIELD CONTINUED

COND/=0,6,65,D		;NON-SKIP SPECIAL FUNCTIONS
			;0-7 DECODED ON (CTL2)
;	NOP=0		;BY DEFAULT
	LD AR0-8=1
	LD AR9-17=2
	LD AR18-35=3
	AR CLR=4
	ARX CLR=5
	ARL IND=6	;CONTROL AR LEFT, CALL, and CLEAR BITS FROM #
	REG CTL=7	;control ar load, exp tst, and mq from #
			; 10-37 DECODED ON (CON1)
	FM WRITE=10	;WRITE AR INTO CURRENTLY ADDRESSED FM LOC
	PCF_#=11	;SET PC FLAGS FROM # FIELD
	FE SHRT=12	;SHIFT FE RIGHT 1
	AD FLAGS=13	;SET PC CRY0, CRY1, OVRFLO, TRAP1 AS APPROPRIATE
	LOAD IR=14	;LATCH AD OR CACHE DATA INTO IR
	SPEC INSTR=15	;SET/CLR SXCT, PXCT, PICYC, TRAP INSTR FLAGS
	SR_#=16		;CONTROL FOR STATE REGISTER
	SEL VMA=17	;READ VMA THROUGH ADA/PC
	DIAG FUNC=20	;SELECT DIAGNOSTIC INFO ONTO EBUS
	EBOX STATE=21	;SET STATE FLOPS
	EBUS CTL=22	;I/O FUNCTIONS
	MBOX CTL=23
;	SPARE=24
;	SPARE=25
;	SPARE=26
;	SPARE=27
	VMA_#=30
	VMA_#+TRAP=31
	VMA_#+MODE=32
	VMA_#+AR32-35=33
	VMA_#+pi*2=34
	VMA DEC=35	;VMA_VMA-1
	VMA INC=36	;VMA_VMA+1
	LD VMA HELD=37	;HOLD VMA oN SIDE
U66/=0,1,66,D	;BIT 66 UNUSED

.TOC	"CONTROL RAM DEFINITIONS -- DISP/SPEC SPECIAL FUNCTIONS"

DISP/=10,5,71,D	;0-7 AND 30-37 ARE DISPATCHES (CRA1&CRA2)
	DIAG=0
	DRAM J=1
	DRAM A RD=2	;IMPLIES INH CRY18
	RETURN=3	;POPJ RETURN
	pg fail=4	;page fail type disp
	SR=5		;16 WAYS ON STATE REGISTER
	NICOND=6	;NEXT INSTRUCTION CONDITION
	SH0-3=7,,2	;16 WAYS ON HIGH-ORDER BITS OF SHIFTER
	MUL=30		;IMPLIES MQ SHIFT, AD LONG
	DIV=31		;IMPLIES MQ SHIFT, AD LONG
	SIGNS=32	;AR0*4 + BR0*2 + AD0
	DRAM B=33	;8 WAYS ON DRAM B FIELD
	BYTE=34		;FPD*4 + BR12*2 + SCAD0
	NORM=35,,2	;IMPLIES AD LONG
	EA MOD=36	;@*2 + XR
	EA TYPE=37

SPEC/=10,5,71,D		;NON-DISPATCH SPECIAL FUNCTIONS (CTL1)
;	NOP=10		;DEFAULT
	INH CRY18=11
	MQ SHIFT=12	;ENABLE MQ*2, MQ SHRT2
	SCM ALT=13	;ENABLE FE, ARSHIFT
	CLR FPD=14
	LOAD PC=15
	XCRY AR0=16	;CARRY INTO AD IS XOR'D WITH AR00
	GEN CRY18=17
	SEC HOLD=20	;INHIBIT LOADING VMAX
	CALL=21
	ARL IND=22	;# SPECIFIES ARL MIX, ENABLES, & CALL
	MTR CTL=23	;# CONTROLS METERS
	FLAG CTL=24	;FUNCTION ENCODED IN # FIELD
	SAVE FLAGS=25	;TELLS PI CYCLE TO HOLD INTRPT
	SP MEM CYCLE=26	;MEM REQUEST IS MODIFIED BY #
	AD LONG=27	;AD BECOMES 72 BIT ALU

U73/=0,3,73,D	;BITS 72-73 UNUSED

MARK/=0,1,74,D	;FIELD SERVICE "MARK" BIT

.TOC	"CONTROL RAM DEFINITIONS -- MAGIC NUMBER FIELD"

#/=0,9,83,D	;THE INFAMOUS "MAGIC NUMBERS"
	VERS=10		;MICRO-CODE VERSION NUMBER 10.EQ.0.8

;VARIOUS SPECIAL FUNCTIONS ENABLE SPECIAL DECODING OF THE
; "MAGIC #" FIELD, AS FOLLOWS:
;SPECIAL DATA PATH CONTROLS

CALL/=0,1,75		;ENABLED BY ARL IND (CTL2)
	CALL=1
AR0-8/=0,1,76		;ENABLED BY ARL IND (CTL2)
	LOAD=1
CLR/=0,4,80		;ENABLED BY ARL IND (CTL2)
	MQ=10
	ARX=4
	ARL=2
	ARR=1
	AR=3
	AR+ARX=7
	AR+MQ=13
	ARX+MQ=14
	AR+ARX+MQ=17
	ARL+ARX=6
	ARL+ARX+MQ=16
	ARR+MQ=11
ARL/=0,3,83		;ENABLED BY ARL IND (CTL2)
	ARL=0
	ARMM=0		;REQUIRES SPECIAL FUNCTION
	CACHE=1		;ORDINARILY SELECTED BY HWARE
	AD=2
	EBUS=3
	SH=4
	AD*2=5
	ADX=6
	AD*.25=7
AR CTL/=0,3,77		;ENABLED BY COND/REG CTL (CTL2)
	AR0-8 LOAD=4
	AR9-17 LOAD=2
	ARR LOAD=1
	ARL LOAD=6
EXP TST/=0,1,80		;ENABLED BY COND/REG CTL (CTL1)
	AR_EXP=1
MQ CTL/=0,2,83		;ENABLED BY COND/REG CTL (CTL2)
;	MQ=0		;WITH MQ/MQ SEL
	MQ*2=1		; "
	MQ*.5=2		; " (drops bits 0,6,12,18,24,30)
	0S=3		; "
	SH=0		;WITH MQ/MQM SEL
	MQ*.25=1	; "
	1S=2		; "
	AD=3		; "

;SPECIAL CONTROL OF EBOX FLAGS & FUNCTIONS

PC FLAGS/=0,9,83	;ENABLED BY COND/PCF_# (SCD4)
	AROV=420	;SET ARITH OVFLO & TRAP1
	FLOV=620	;SAME, PLUS FLOATING OVFLO
	FPD=100		;SET FIRST PART DONE
	TRAP2=40	;SET TRAP2 (PDL OVFLO)
	FXU=630		;FLOV + EXP UNDERFLOW
	DIV CHK=424	;NO DIVIDE + AROV
	FDV CHK=624	;FLOATING NO DIVIDE
FLAG CTL/=0,9,83	;ENABLED BY SPEC/FLAG CTL (SCD5)
	RSTR FLAGS=420	;AS IN JRSTF
	JFCL=600	;FORCE PC 00 = AROV
	JFCL+LD=620	;SECOND PART OF JFCL -- CLEAR TESTED FLAGS
	DISMISS=500	;CLEAR PI CYCLE IF SET (con5)
			; ELSE DISMISS HIGHEST PI HOLD
	HALT=440	;STOP PROCESSOR IF LEGAL (con2)
	SET FLAGS=20	;AS IN MUUO
	PORTAL=410	;CLEAR PUBLIC IF PRIVATE INSTR
	LD PUB W PRVT=622 ;PERMIT A LOAD FLAGS WITHOUT LEAVE USER
SPEC INSTR/=0,9,83	;ENABLED BY COND/SPEC INSTR
	SET PI CYCLE=704; (CON5)
	JUST SET PI CYCLE=700;DONT ISSUE "COND INSTR ABORT"
	KERNEL CYCLE=200;MAKE IO LEGAL, EXEC ADDR SPACE (CON4)
	INH PC+1=100	;TO MAKE JSR WORK IN TRAP, INTRPT (CON4)
	SXCT=40		;START SECTION XCT (MCL4)
	PXCT=20		;START PREV CONTXT XCT (MCL4)
	INTRPT INH=10	;INHIBIT INTERRUPTS (CON4)
	INSTR ABORT=4	; (CON2)
	HALTED=302	;TELL CONSOLE WE'RE HALTED (CON4)
	PXCT-KERNEL=220 ;SET PXCT & KERNEL
	CONS XCT=310	;FLAGS FOR INSTR XCT'D FROM CONSOLE
	cont=10		;INHIBIT INTERRUPTS WHILE SINGLE STEPpING
FETCH/=0,9,83		;ENABLED BY MEM/FETCH
	UNCOND=400
			;LOW 2 BITS DECODED ON (IR3)
	COMP=201,,2	;DEPENDING ON AD AND DRAM B
	SKIP=202,,2
	TEST=203,,1
	JUMP=102,,2	;AS IN JUMPX, ON AD AND DRAM B
	jfcl=103,,1	;jump on test condition

;SPECIAL CONTROLS & FUNCTIONS FOR MBOX

SP MEM/=0,9,83		;ENABLED BY SPEC/SP MEM CYCLE
	FETCH=400	;LOAD IR WHEN DATA ARRIVES (MCL5)
	USER=200	;FORCE USER OR UPT (MCL2)
	EXEC=100	;FORCE EXEC OR EPT (MCL3)
	SEC 0=40	;CLEAR VMAX (MCL4)
	UPT EN=20	;UPT IF USER EN (MCL3)
	EPT EN=10	;EPT IF NOT USER EN (MCL3)
	CACHE INH=2	; (MCL6)
	UNPAGED=1	; (MCL6)
	EPT=111
	EPT FETCH=511
	UPT=221
	UPT FETCH=621
	PT DIR RD NO PG FAIL=510
	PT RD NO PG FAIL=110 ;RD PAG TABLE DATA,ENSURE NO PAGE FAILS
	NO USR W NO PG FAIL=110
	USER W NO PG FAIL=220
	PT=31
	PT FETCH=431
MREG FNC/=0,9,83	;ENABLED BY MEM/REG FUNC (APR6)
	SBUS DIAG=7	;PERFORM SBUS DIAGNOSTIC CYCLE
	READ UBR=502	;ASK MBOX TO LOAD UBR INTO EBUS REG
	READ EBR=503	;PUT EBR INTO EBUS REG
	READ ERA=504
	READ PT=100
	NO MEM ACCESS=304
	NO MEM ACCESS BTYPE=204
	VER PTD=304
	WR REFILL RAM=505 ;DISGUISED AS A "READ REG" FUNCTION
	LOAD CCA=601	;START A SWEEP
	LOAD UBR=602	;SETUP UBR FROM VMA
	LOAD EBR=603	;SETUP EBR FROM VMA
	MAP=140		;GET PHYS ADDR CORRESPONDING TO VMA (MCL6)
MBOX CTL/=0,9,83	;ENABLED BY COND/MBOX CTL (APR5)
	SET PAGE FAIL=200
	SET IO PF ERR=100
	PT DIR WR=20,1	;WRITE PAGE TABLE DIRECTORY
	PT WR=10,1	;WRITE PAGE TABLE ENTRY SELECTED BY VMA
	NORMAL=0	;RESET PT WR SELECTION
	PT DIR CLR=1	;SELECT FOR CLEARING PT DIR (PAG3)
	CLR PT LINE=21	;CLEAR VALID FOR 8 ENTRIES
	CLR PT EVEN=32	;WR DIR & TWO ENTRIES
	CLR PT ODD=13	;WR OTHER TWO

;I/O FUNCTIONS

EBUS CTL/=0,9,83	;ENABLED BY COND/EBUS CTL (APR3)
	GRAB EEBUS=400	;"EBUS RETURN" TAKES ECL EBUS FOR EBOX
	REQ EBUS=200
	REL EBUS=100	; (CON3)
	EBUS DEMAND=60	;ASSERT DEMAND, KEEP CS, FUNC
	EBUS NODEMAND=20;DROP DEMAND, KEEP CS, FUNC
	CTL_IR=10	;SELECT F01 & F02 FROM IR
	DISABLE CS HOLD=24	;CONTROLLER SELECT OFF AND HOLD IT
	DISABLE CS=4	;TURN OFF CONTROLLER SELECT
	dataIO=2	;0 FOR conI/O
	INPUT=1		;0 FOR OUTPUT
	IO INIT=30	;ENABLE IR3-9 TO EBUS CONTROLLER SELECT,
			; IR10-12 (DECODED) TO FUNCTION
			; AND AR ONTO EBUS IF FUNCTION IS OUTPUT
	DATAO=26	;0'S TO CS, DATAO TO FCN, AND AR TO EBUS
	DATAI=27	;0'S TO CS, DATAI TO FCN
	REL EEBUS=0	;LEGGO
DIAG FUNC/=0,9,83	;ENABLED BY COND/DIAG FUNC (CTL3)
	.5 USEC=400,3		;STRETCH CLOCK TO LET EBUS SETTLE (CON?)
	LD PA LEFT=404,3	;LH PERF ANAL CONTROLS FROM RH (MTR)
	LD PA RIGHT=405,3	;RH PA CONTROLS FROM RH (MTR)
	CONO MTR=406,3		;ACCOUNTING CONTROLS (MTR)
	CONO TIM=407,3		;INTERVAL TIMER CONTROLS (MTR)
	CONO APR=414,3		; (CON3)
	CONO PI=415,3		; (CON3)
	CONO PAG=416,3		;CACHE & PAGING CTL (CON3)
	DATAO APR=417,3		;ADDRESS BREAK (CON3)
	DATAO PAG=620,3		;AC BLOCKS & PREV CONTXT (CON3)
	ld ac blks=425,3	;force loading ac blocks
	ld pcs+cwsx=426,3	;force loading prev contxt sec, cwsx
	CONI PI(R)=500,3	;PI HOLD & ACTIVE TO LH (PI)
	CONI PI(L)=501,3	;PI GEN TO LH (PI)
	CONI APR(R)=510,3	;APR INTERRUPT & PIA TO LH (APR6)
	RD TIME=510,3		;TIME BASE TO RH (MTR5)
	DATAI PAG(L)=511,3	;AC BLOCKS, PREV CONTXT TO LH (APR6)
	RD PERF CNT=511,3	;PERFORMANCE COUNT TO RH (MTR5)
	CONI APR(L)=512,3	;APR INTERRUPT ENABLES TO LH (APR6)
	RD EBOX CNT=512,3	;EBOX COUNT TO RH (MTR5)
	DATAI APR=513,3		;ADDR BREAK CONDITIONS TO LH (APR6)
	RD CACHE CNT=513,3	;CACHE COUNT TO RH (MTR5)
	RD INTRVL=514,3		;INTERVAL TIMER TO RH (MTR5)
	RD PERIOD=515,3		;PERIOD REGISTER TO RH (MTR5)
	CONI MTR=516,3		;CONTROLS & PIA TO RH (MTR5)
	RD MTR REQ=517,3	;ENCODED UPDATE REQUEST TO 20-22 (MTR5)
	coni pi(par)=530,3	;write even parity enables to rh (con1)
	CONI PAG=531,3		;CACHE & TRAP CTL TO RH (CON1)
	RD EBUS REG=567,3	;EBUS REGISTER IN MBOX (MBZ1 & MBC1)
;PARITY/=0,0,0,P		;USE ANY AVAILABLE FIELD FOR PARITY

.TOC	"DISPATCH RAM DEFINITIONS"
;FIELDS ARE ARRANGED FOR EASY READING, NOT COMPACTNESS

	.DCODE
A/=0,3,2		;OPERAND FETCH MODE
	IMMED=0		;IMMEDIATE
	IMMED-PF=1	;IMMEDIATE, START PREFETCH
	WR-TST=3	;TEST WRITABILITY
	READ=4		;READ ONLY
	READ-PF=5	;READ, THEN PREFETCH
	RD-WR=6		;READ WRITE (SEPARATE CYCLES)
	RD-P-WR=7	;READ PAUSE WRITE

B/=0,3,5		;STORE RESULTS AT--
	DBL AC=1	;DOUBLE RESULT TO AC & AC+1
	DBL BOTH=2	;MULB, DIVB, ETC
	SELF=3		;SELF MODE INSTRUCTIONS
	AC=5		;SINGLE RESULT TO AC, PREFETCH IN PROG
	MEM=6		;RESULT TO MEMORY
	BOTH=7		;SINGLE RESULT TO MEMORY AND AC

	SJC-=3		;SKIP JUMP COMPARE CONTROLS
	SJCL=2
	SJCE=1
	SJCLE=0
	SJCA=7
	SJCGE=6
	SJCN=5
	SJCG=4
B0/=0,1,3		;INVERTS VARIOUS TEST, SKIP, AND JUMP CONTROLS
	CRY0(0)=0	;TEST TST CAUSES PC SKIP IF CRY0=0
	CRY0(1)=1	; SAME IF CRY0=1
B1-2/=0,2,5		;FLOATING RESULT STORE MODE
	AC=1	;RESULT TO AC
	MEM=2	;RESULT JUST TO MEM
	BOTH=3	;RESULT TO BOTH

;PARITY/=0,1,11,P

J/=0,10,23		;EXECUTOR (40&20-BITS ALWAYS 0)
	.UCODE