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klu2_442
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define.mic
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.TOC "CONDITIONAL ASSEMBLY VARIABLE DEFINITIONS"
.NOBIN
; [COST ESTIMATES IN BRACKETS INDICATE NUMBER OF ADDITIONAL
; MICROINSTRUCTIONS REQUIRED BY TURNING ON THE FEATURE SWITCH]
.DEFAULT/TRACKS=0 ;1 ENABLES STORING PC AFTER EVERY INSTRUCTION,
; & CREATES DATAI/O PI TO READ/SETUP PC BUFFER
;ADDRESS. [COST = 21 WDS]
.DEFAULT/OP.CNT=0 ;1 ENABLES CODE TO BUILD A HISTOGRAM IN CORE
; COUNTING USES OF EACH OPCODE IN USER & EXEC
.DEFAULT/OP.TIME=0 ;1 ENABLES CODE TO ACCUMULATE TIME SPENT BY
; EACH OPCODE
.DEFAULT/SO.CNT=0 ;SECOND ORDER COUNTING IN 128K STARTING AT LOC
; 400000 NOT DEBUGED [COST = 28 WDS]
.DEFAULT/SO2.CNT=0 ;SECOND ORDER COUNTING IN 128K STARTING AT LOC
; PRESENTED AT START DOES ONE MORE ADD THAN
; SO.CNT AND HENCE AN INSTRUCTION TAKES
; 120 NS LONGER THAN SO.CNT [COST = 28 WDS]
.DEFAULT/PAGCNT=0 ;Enable code to count entries into the PFH and
; number of DATAO PAGs with bit 2 set. [Cost =
; 6 words] [327]
.DEFAULT/FPLONG=1 ;1 ENABLES KA-STYLE DOUBLE PRECISION FLOATING
;POINT INSTRUCTIONS: FADL, FSBL, FMPL, FDVL,
; UFA, DFN. [COST = 49 WDS]
.DEFAULT/MULTI=0 ;1 IF MULTIPROCESSOR SYSTEM, TO SUPPRESS CACHE
;ON UNPAGED REF'S. PAGED REF'S ARE UP TO EXEC.
.DEFAULT/MOS.MULTI=0 ;1 if we have multiported MOS memory. This hardware
;project was abandoned before it was completed.
;[Cost = 5 wds.]
.DEFAULT/SNORM.OPT=0 ;1 ENABLES FASTER NORMALIZATION OF SINGLE-
; PRECISION RESULTS WHICH HAVE SEVERE LOSS OF
; SIGNIFICANCE [COST = 4 WDS]
.IF/TRACKS ;SETUP CONTROL FOR COMMON CODE
.SET/INSTR.STAT=1
.ENDIF/TRACKS
.IF/OP.CNT
.SET/INSTR.STAT=1 ;ENABLE COMMON CODE, ERROR IF TRACKS TOO
.ENDIF/OP.CNT
.IF/OP.TIME
.SET/INSTR.STAT=1 ;ERROR IF TRACKS OR OP.CNT ALSO SET
.ENDIF/OP.TIME
.IF/SO.CNT
.SET/INSTR.STAT=1
.ENDIF/SO.CNT
.IF/SO2.CNT
.SET/INSTR.STAT=1
.ENDIF/SO2.CNT
.DEFAULT/INSTR.STAT=0 ;IF NO STATISTICS, TURN OFF COMMON CODE
.IF/INSTR.STAT
.SET/NONSTD=1 ;STATISTICS CODE IS NONSTANDARD
.SET/TRXDEF=1 ;Make sure TRX registers get defined [327]
.ENDIF/INSTR.STAT
.IF/PAGCNT
.SET/NONSTD=1 ;All statistics are nonstandard
.SET/TRXDEF=1 ;We need the TRX registers
.ENDIF/PAGCNT
.DEFAULT/TRXDEF=0 ;Normally no TRX registers needed
.DEFAULT/NONSTD=0 ;NONSTANDARD MICROCODE IS NORMALLY OFF
.DEFAULT/OWGBP=0 ;[264]
.DEFAULT/IPA20=0 ;[264]
.DEFAULT/NOCST=0 ;[264]
.DEFAULT/CST.WRITE=1 ;[314] Enable CST writable bit
.DEFAULT/BIG.PT=1 ;[333][347] Special code for big page table and Keep bit
.DEFAULT/DDT.BUG=0 ;[346] If on, enable APRID hack to move bit 23
.DEFAULT/GFTCNV=1 ;[273] GFLOAT CONVERSION INST.
.DEFAULT/EDIT=1 ;Edit is usually here ****HACK****
.TOC "HOW TO READ THE MICROCODE -- FORMATS & CONSTRUCTS"
;(1) FIELD DEFINITIONS
; THESE OCCUR AT THE BEGINNING OF THE LISTING, IN THE SOURCE FILE
; DEFINE.MIC (CONTROL AND DISPATCH RAM DEFINITIONS).
; THEY HAVE THE FORM:
; SYMBOL/=<L:R>M,J
;ANOTHER FORM ACCEPTED BY THE ASSEMBLER (FOR HISTORIC REASONS) IS:
; SYMBOL/=J,K,R,M ;THIS FORM HAS BEEN REMOVED FROM THIS CODE
; THE PARAMETER (J) IS MEANINGFUL ONLY WHEN "D" IS SPECIFIED
; AS THE DEFAULT MECHANISM, AND IN THAT CASE, GIVES THE DEFAULT VALUE OF
; THE FIELD IN OCTAL.
; THE PARAMETER (K) GIVES THE FIELD SIZE IN (DECIMAL) NUMBER
; OF BITS. THIS IS USED ONLY IN THE OUTDATED FORMAT.
; THE PARAMETER (L) GIVES THE BIT POSITION OF THE LEFTMOST BIT
;IN THE FIELD. THE SAME METHOD IS USED AS FOR (R) BELOW.
; THE PARAMETER (R) GIVES THE FIELD POSITION IN DECIMAL
; AS THE BIT NUMBER OF THE RIGHTMOST BIT OF THE FIELD. BITS ARE NUMBERED
; FROM 0 ON THE LEFT. NOTE THAT THE POSITION OF BITS IN THE MICROWORD
; SHOWN IN THE LISTING BEARS NO RELATION TO THE ORDERING OF BITS IN THE
; HARDWARE MICROWORD, WHERE FIELDS ARE OFTEN BROKEN UP AND SCATTERED.
; THE PARAMETER (M) IS OPTIONAL, AND SELECTS A DEFAULT
; MECHANISM FOR THE FIELD. THE LEGAL VALUES OF THIS PARAMETER ARE THE
; CHARACTERS "D", "T", "P", OR "+".
; "D" MEANS (J) IS THE DEFAULT VALUE OF THE FIELD IF NO EXPLICIT
; VALUE IS SPECIFIED.
; "T" IS USED ON THE TIME FIELD TO SPECIFY THAT THE VALUE OF THE
; FIELD DEPENDS ON THE TIME PARAMETERS SELECTED FOR OTHER FIELDS.
; THE VALUE OF A FIELD WITH THIS SPECIFICATION DEFAULTS TO THE
; MAX OF <SUM OF THE T1 PARAMETERS DEFINED FOR FIELD/VALUES
; SPECIFIED IN THIS MICROINSTRUCTION>, <SUM OF THE T2 PARAMETERS
; FOR THIS MICROINSTRUCTION>, <J PARAMETER OF THIS FIELD>.
; WITHIN THE KL10 MICROCODE, T1 PARAMETERS ARE USED TO SPECIFY
; FUNCTIONS WHICH DEPEND ON THE ADDER SETUP TIME, AND T2 PARAMETERS
; ARE USED FOR FUNCTIONS WHICH REQUIRE ADDITIONAL TIME FOR CORRECT
; SELECTION OF THE NEXT MICROINSTRUCTION ADDRESS.
; "P" IS USED ON THE PARITY FIELD TO SPECIFY THAT THE VALUE OF THE
; FIELD SHOULD DEFAULT SUCH THAT PARITY OF THE ENTIRE WORD
; IS ODD. IF THIS OPTION IS SELECTED ON A FIELD WHOSE SIZE (K) IS
; ZERO, THE MICRO ASSEMBLER WILL ATTEMPT TO FIND A BIT SOMEWHERE
; IN THE WORD FOR WHICH NO VALUE IS SPECIFIED OR DEFAULTED.
; "+" IS USED ON THE JUMP ADDRESS FIELD TO SPECIFY THAT THE DEFAULT
; JUMP ADDRESS IS THE ADDRESS OF THE NEXT INSTRUCTION ASSEMBLED (NOT,
; IN GENERAL, THE CURRENT LOCATION +1).
; IN GENERAL, A FIELD CORRESPONDS TO THE SET OF BITS WHICH PROVIDE
; SELECT INPUTS FOR MIXERS OR DECODERS, OR CONTROLS FOR ALU'S.
; EXAMPLES:
; AR/=<24:26>D,0 OR AR/=0,3,26,D
; THE MICROCODE FIELD WHICH CONTROLS THE AR MIXER (AND THEREFORE
; THE DATA TO BE LOADED INTO AR ON EACH EBOX CLOCK) IS THREE BITS WIDE
; AND THE RIGHTMOST BIT IS SHOWN IN THE LISTING AS BIT 26 OF THE
; MICROINSTRUCTION. IF NO VALUE IS SPECIFICALLY REQUESTED FOR THE FIELD,
; THE MICROASSEMBLER WILL ENSURE THAT THE FIELD IS 0.
; AD/=<12:17> OR AD/=0,6,17
; THE FIELD WHICH CONTROLS THE AD IS 6 BITS WIDE, ENDING ON
; BIT 17. THE FOURTH PARAMETER OF THE FIELD IS OMITTED, SO THE FIELD
; IS AVAILABLE TO THE MICROASSEMBLER (IF NO VALUE IS EXPLICITLY
; CALLED OUT FOR THE FIELD) FOR MODIFICATION TO ENSURE ODD PARITY IN THE
; ENTIRE WORD.
;
;(2) VALUE DEFINITIONS
; FOLLOWING A FIELD DEFINITION, SYMBOLS MAY BE CREATED IN THAT
; FIELD TO CORRESPOND TO VALUES OF THE FIELD. THE FORM IS:
; SYMBOL=N,T1,T2
; "N" IS, IN OCTAL, THE VALUE OF SYMBOL WHEN USED IN THE FIELD.
; T1 AND T2 ARE OPTIONAL, AND SPECIFY PARAMETERS IN THE TIME FIELD
; CALCULATION FOR MICROINSTRUCTIONS IN WHICH THIS FIELD/SYMBOL IS USED.
; THE MICROASSEMBLER COMPUTES THE SUMS OF ALL THE T1'S AND ALL THE T2'S
; SPECIFIED FOR FIELD/SYMBOL SPECIFICATIONS IN A WORD, AND USES THE MAX
; OF THE TWO SUMS AS THE DEFAULT VALUE FOR THE FIELD WHOSE DEFAULT
; MECHANISM IS "T". EXAMPLES:
; AD/=<12:17> ;FIELD DEFINITION IN WHICH FOLLOWING SYMBOLS EXIST
; XOR=31
; A+B=6,1
; HERE THE SYMBOLS "XOR" AND "A+B" ARE DEFINED FOR THE "AD" FIELD.
; TO THE ASSEMBLER, THEREFORE, WRITING "AD/XOR" MEANS PUT THE VALUE 31
; INTO THE 6-BIT FIELD ENDING ON BIT 17 OF THE MICROWORD. THE SYMBOLS
; ARE CHOSEN FOR MNEMONIC SIGNIFICANCE, OF COURSE, SO ONE READING
; THE MICROCODE WOULD INTERPRET "AD/XOR" AS "THE OUTPUT OF AD SHALL BE THE
; EXCLUSIVE OR OF ITS A AND B INPUTS". SIMILIARLY, "AD/A+B" IS READ AS
; "AD PRODUCES THE SUM OF A AND B". THE SECOND PARAMETER IN THE DEFINITION
; OF "A+B" IS A CONTROL TO THE MICRO ASSEMBLER'S TIME-FIELD CALCULATION,
; WHICH TELLS THE ASSEMBLER THAT THIS OPERATION TAKES LONGER THAN THE
; BASIC CYCLE, AND THEREFORE THAT THE TIME FIELD SHOULD BE INCREASED.
; AR/=<24:26>D,0 ;FIELD DEFINITION FOR FOLLOWING SYMBOLS
; AR=0
; AD=2
; HERE THE SYMBOLS "AR" AND "AD" ARE DEFINED FOR THE FIELD NAMED
; "AR", WHICH CONTROLS THE AR MIXER. WE COULD WRITE AR/AR TO MEAN THAT
; THE AR MIXER SELECT INPUTS WOULD BE 0, WHICH IN THE
; HARDWARE SELECTS THE AR OUTPUT FOR RECIRCULATION TO THE REGISTER. IN
; PRACTICE, HOWEVER, WE WANT THIS TO BE THE DEFAULT CASE, SO THAT AR
; DOES NOT CHANGE UNLESS WE SPECIFICALLY REQUEST IT, SO THE FIELD
; DEFINITION SPECIFIES 0 AS THE DEFAULT VALUE OF THE FIELD. IF WE
; WANT AR LOADED FROM THE AD OUTPUT, WE WRITE "AR/AD" TO SET THE
; MIXER SELECTS TO PASS THE AD OUTPUT INTO THE AR.
;
;(3) LABEL DEFINITIONS
; A MICRO INSTRUCTION MAY BE LABELLED BY A SYMBOL FOLLOWED BY COLON
; PRECEDING THE MICROINSTRUCTION DEFINITION. THE ADDRESS OF THE
; MICROINSTRUCTION BECOMES THE VALUE OF THE SYMBOL IN THE FIELD NAMED "J".
; EXAMPLE:
; FOO: J/FOO
; THIS IS A MICROINSTRUCTION WHOSE "J" FIELD (JUMP ADDRESS) CONTAINS
; THE VALUE "FOO". IT ALSO DEFINES THE SYMBOL "FOO" TO BE THE ADDRESS
; OF ITSELF. THEREFORE, IF EXECUTED BY THE MICROPROCESSOR, IT WOULD
; LOOP ON ITSELF.
;
;(4) COMMENTS
; A SEMICOLON ANYWHERE ON A LINE CAUSES THE REST OF THE LINE
; TO BE IGNORED BY THE ASSEMBLER. THIS TEXT IS AN EXAMPLE OF COMMENTS.
;
;(5) MICROINSTRUCTION DEFINITION
; A WORD OF MICROCODE IS DEFINED BY SPECIFYING A FIELD NAME,
; FOLLOWED BY SLASH (/), FOLLOWED BY A VALUE. THE VALUE MAY BE A
; SYMBOL DEFINED FOR THAT FIELD, AN OCTAL DIGIT STRING, OR A DECIMAL
; DIGIT STRING (DISTINGUISHED BY THE FACT THAT IT CONTAINS "8" AND/OR
; "9" AND/OR IS TERMINATED BY A PERIOD). SEVERAL FIELDS MAY BE SPECIFIED
; IN ONE MICROINSTRUCTION BY SEPARATING FIELD/VALUE SPECIFICATIONS WITH
; COMMAS. EXAMPLE:
; ADB/BR,ADA/AR,AD/A+B,AR/AD
; THE FIELD NAMED "ADB" IS GIVEN THE VALUE NAMED "BR" (TO
; CAUSE THE MIXER ON THE B SIDE OF AD TO SELECT BR), FIELD "ADA" HAS VALUE
; "AR", FIELD "AD" HAS VALUE "A+B", AND FIELD "AR" HAS VALUE "AD".
;
;(6) CONTINUATION
; THE DEFINITION OF A MICROINSTRUCTION MAY CONTINUED ONTO TWO OR
; MORE LINES BY BREAKING IT AFTER ANY COMMA. IN OTHER WORDS, IF THE
; LAST NON-BLANK, NON-COMMENT CHARACTER ON A LINE IS A COMMA, THE
; INSTRUCTION SPECIFICATION IS CONTINUED ON THE FOLLOWING LINE.
; EXAMPLE:
; ADB/BR,ADA/AR, ;SELECT AR & BR AS AD INPUTS
; AD/A+B,AR/AD ;TAKE THE SUM INTO AR
; BY CONVENTION, CONTINUATION LINES ARE INDENTED AN EXTRA TAB.
;
;(7) MACROS
; A MACRO IS A SYMBOL WHOSE VALUE IS ONE OR MORE FIELD/VALUE
; SPECIFICATIONS AND/OR MACROS. A MACRO DEFINITION IS A LINE CONTAINING
; THE MACRO NAME FOLLOWED BY A QUOTED STRING WHICH IS THE VALUE OF THE
; MACRO. EXAMPLE:
; AR_AR+BR "ADB/BR,ADA/AR,AD/A+B,AR/AD"
; THE APPEARANCE OF A MACRO IN A MICROINSTRUCTION DEFINITION IS EQUIVALENT
; TO THE APPEARANCE OF ITS VALUE. MACROS FOR VARIOUS FUNCTIONS
; ARE DEFINED IN "MACRO.MIC".
;
;(8) PSEUDO OPS
; THE MICRO ASSEMBLER HAS 10 PSEUDO-OPERATORS:
;.DCODE AND .UCODE SELECT THE RAM INTO WHICH SUBSEQUENT MICROCODE WILL
;BE LOADED, AND THEREFORE THE FIELD DEFINITIONS AND MACROS WHICH ARE
;MEANINGFUL IN SUBSEQUENT MICROCODE
;.TITLE DEFINES A STRING OF TEXT TO APPEAR IN THE PAGE HEADER, AND
;.TOC DEFINES AN ENTRY FOR THE TABLE OF CONTENTS AT THE BEGINNING.
;.SET DEFINES THE VALUE OF A CONDITIONAL ASSEMBLY PARAMETER,
;.CHANGE REDEFINES A CONDITIONAL ASSEMBLY PARAMETER,
;.DEFAULT ASSIGNS A VALUE TO AN UNDEFINED PARAMETER.
;.IF ENABLES ASSEMBLY IF THE VALUE OF THE PARAMETER IS NOT ZERO,
;.IFNOT ENABLES ASSEMBLY IF THE PARAMETER VALUE IS ZERO, AND
;.ENDIF RE-ENABLES ASSEMBLY IF SUPPRESSED BY THE PARAMETER NAMED.
;
;(9) LOCATION CONTROL
; A MICROINSTRUCTION "LABELLED" WITH A NUMBER IS ASSIGNED TO THAT
; ADDRESS.
; THE CHARACTER "=" AT THE BEGINNING OF A LINE, FOLLOWED BY
; A STRING OF 0'S, 1'S, AND/OR *'S, SPECIFIES A CONSTRAINT ON THE
; ADDRESS OF FOLLOWING MICROINSTRUCTIONS. THE NUMBER OF CHARACTERS
; IN THE CONSTRAINT STRING (EXCLUDING THE "=") IS THE NUMBER OF LOW-ORDER
; BITS CONSTRAINED IN THE ADDRESS. THE MICROASSEMBLER ATTEMPTS TO FIND
; AN UNUSED LOCATION WHOSE ADDRESS HAS 0 BITS IN THE POSITIONS
; CORRESPONDING TO 0'S IN THE CONSTRAINT STRING AND 1 BITS WHERE THE
; CONSTRAINT HAS 1'S. ASTERISKS DENOTE "DON'T CARE" BIT POSITIONS.
; IF THERE ARE ANY 0'S IN THE CONSTRAINT STRING, THE CONSTRAINT
; IMPLIES A BLOCK OF <2**N> MICROWORDS, WHERE N IS THE NUMBER OF 0'S
; IN THE STRING. ALL LOCATIONS IN THE BLOCK WILL HAVE 1'S IN THE ADDRESS
; BITS CORRESPONDING TO 1'S IN THE STRING, AND BIT POSITIONS DENOTED BY *'S
; WILL BE THE SAME IN ALL LOCATIONS OF THE BLOCK.
; IN SUCH A CONSTRAINT BLOCK, THE DEFAULT ADDRESS PROGRESSION IS
; COUNTING IN THE "0" POSITIONS OF THE CONSTRAINT STRING, BUT A NEW
; CONSTRAINT STRING OCCURING WITHIN A BLOCK MAY FORCE SKIPPING OVER
; SOME LOCATIONS OF THE BLOCK. WITHIN A BLOCK, A NEW CONSTRAINT
; STRING DOES NOT CHANGE THE PATTERN OF DEFAULT ADDRESS PROGRESSION, IT
; MERELY ADVANCES THE LOCATION COUNTER OVER THOSE LOCATIONS. THE
; MICROASSEMBLER WILL LATER FILL THEM IN.
; A NULL CONSTRAINT STRING ("=" FOLLOWED BY ANYTHING BUT "0",
; "1", OR "*") SERVES TO TERMINATE A CONSTRAINT BLOCK.
; EXAMPLES:
; =0
; THIS SPECIFIES THAT THE LOW-ORDER ADDRESS BIT MUST BE ZERO--
; THE MICROASSEMBLER FINDS AN EVEN-ODD PAIR OF LOCATIONS, AND PUTS
; THE NEXT TWO MICROINSTRUCTIONS INTO THEM.
; =11
; THIS SPECIFIES THAT THE TWO LOW-ORDER BITS OF THE ADDRESS MUST
; BOTH BE ONES. SINCE THERE ARE NO 0'S IN THIS CONSTRAINT, THE
; ASSEMBLER FINDS ONLY ONE LOCATION MEETING THE CONSTRAINT.
; =0*****
; THIS SPECIFIES AN ADDRESS IN WHICH THE "40" BIT IS ZERO. DUE
; TO THE IMPLEMENTATION OF THIS FEATURE IN THE ASSEMBLER, THE DEFAULT
; ADDRESS PROGRESSION APPLIES ONLY TO THE LOW-ORDER 5 BITS, SO THIS
; CONSTRAINT FINDS ONE WORD IN WHICH THE "40" BIT IS ZERO, AND DOES
; NOT ATTEMPT TO FIND ONE IN WHICH THAT BIT IS A ONE.
;THIS LIMITATION HAS BEEN CHANGED WITH NEWER ASSEMBLER VERSIONS.
;HOWEVER NONE OF THE LOCATIONS IN THE MICROCODE REQUIRE ANYTHING BUT THE
;CONSTRAINT MENTIONED ABOVE.
.TOC "MICROCODE LISTING TEMPLATE"
;HERE IS A TEMPLATE WHICH CAN BE USED WITH THE MICROCODE
; LISTING TO IDENTIFY FIELDS IN THE OUTPUT --
; ---- ---- ---- ---- ---- ---- ---- ----
; [--] [--] []!! !!!! !!!! !![] [][] ![-]
; ! ! !!! !!!! !!!! !! ! ! ! ! + # = MAGIC NUMBERS
; ! ! !!! !!!! !!!! !! ! ! ! + MARK = SCOPE SYNC
; ! ! !!! !!!! !!!! !! ! ! !
; ! ! !!! !!!! !!!! !! ! ! + CALL, DISP/SPEC = SPEC FUNCTIONS
; ! ! !!! !!!! !!!! !! ! + SKIP/COND = SPECIAL FUNCTIONS
; ! ! !!! !!!! !!!! !! !
; ! ! !!! !!!! !!!! !! + TIME, MEM = UINST TIME & MEM FUNCTION
; ! ! !!! !!!! !!!! !+ VMA = VMA INPUT SELECT
; ! ! !!! !!!! !!!! + SH/ARMM = SH FUNCTION / ARMM SELECT
; ! ! !!! !!!! !!!!
; ! ! !!! !!!! !!!+ SC, FE = SC INPUT SELECT & FE LOAD
; ! ! !!! !!!! !!+ SCADB = SELECT FOR SCAD "B" INPUT
; ! ! !!! !!!! !+ SCADA = ENABLE AND SELECT FOR SCAD "A" INPUT
; ! ! !!! !!!! + SCAD = SC/FE ADDER FUNCTION
; ! ! !!! !!!!
; ! ! !!! !!!+ FM ADR = FAST MEMORY ADDRESS SELECT
; ! ! !!! !!+ BR, BRX, MQ = LOAD BR & BRX, SEL FOR MQ
; ! ! !!! !+ ARX = SELECT FOR ARX INPUT
; ! ! !!! + AR = SELECT FOR AR INPUT
; ! ! !!!
; ! ! !!+ ADB = SELECT FOR ADDER "B" INPUT
; ! ! !+ ADA = SELECT AND ENABLE FOR ADDER "A" INPUT
; ! ! + AD = OPERATION IN ADDER AND ADDER EXTENSION
; ! !
; ! + J = BASE ADDRESS TO WHICH THIS MICROINSTRUCTION JUMPS
; !
; + LOCATION IN CRAM INTO WHICH THIS WORD IS LOADED
;
; U/V = MICRO INSTRUCTION FOR CRAM
;*******************************************************************
; D = WORD FOR DRAM
;
; + LOCATION IN DRAM INTO WHICH THIS WORD IS LOADED
; !
; ! + A = OPERAND ACCESS CONTROL
; ! !+ B = INSTRUCTION "MODE"
; ! !! + P = PARITY FOR THIS WORD
; ! !! !
; ! !! ! + J = ADDRESS OF HANDLER FOR THIS INSTRUCTION
; [--] !! ! [--]
; ---- ---- ----
.TOC "KL10 INSTRUCTION OPCODE MAP"
; 0 1 2 3 4 5 6 7
;100 (UUO) (UUO) GFAD GFSB JSYS ADJSP GFMP GFDV
;110 DFAD DFSB DFMP DFDV DADD DSUB DMUL DDIV
;120 DMOVE DMOVN FIX EXTEND DMOVEM DMOVNM FIXR FLTR
;130 (UFA) (DFN) FSC IBP ILDB LDB IDPB DPB
;140 FAD (FADL) FADM FADB FADR FADRI FADRM FADRB
;150 FSB (FSBL) FSBM FSBB FSBR FSBRI FSBRM FSBRB
;160 FMP (FMPL) FMPM FMPB FMPR FMPRI FMPRM FMPRB
;170 FDV (FDVL) FDVM FDVB FDVR FDVRI FDVRM FDVRB
; 0 1 2 3 4 5 6 7
;200 MOVE MOVEI MOVEM MOVES MOVS MOVSI MOVSM MOVSS
;210 MOVN MOVNI MOVNM MOVNS MOVM MOVMI MOVMM MOVMS
;220 IMUL IMULI IMULM IMULB MUL MULI MULM MULB
;230 IDIV IDIVI IDIVM IDIVB DIV DIVI DIVM DIVB
;240 ASH ROT LSH JFFO ASHC ROTC LSHC (UUO)
;250 EXCH BLT AOBJP AOBJN JRST JFCL XCT MAP
;260 PUSHJ PUSH POP POPJ JSR JSP JSA JRA
;270 ADD ADDI ADDM ADDB SUB SUBI SUBM SUBB
; 0 1 2 3 4 5 6 7
;300 CAI CAIL CAIE CAILE CAIA CAIGE CAIN CAIG
;310 CAM CAML CAME CAMLE CAMA CAMGE CAMN CAMG
;320 JUMP JUMPL JUMPE JUMPLE JUMPA JUMPGE JUMPN JUMPG
;330 SKIP SKIPL SKIPE SKIPLE SKIPA SKIPGE SKIPN SKIPG
;340 AOJ AOJL AOJE AOJLE AOJA AOJGE AOJN AOJG
;350 AOS AOSL AOSE AOSLE AOSA AOSGE AOSN AOSG
;360 SOJ SOJL SOJE SOJLE SOJA SOJGE SOJN SOJG
;370 SOS SOSL SOSE SOSLE SOSA SOSGE SOSN SOSG
; 0 1 2 3 4 5 6 7
;400 SETZ SETZI SETZM SETZB AND ANDI ANDM ANDB
;410 ANDCA ANDCAI ANDCAM ANDCAB SETM SETMI SETMM SETMB
;420 ANDCM ANDCMI ANDCMM ANDCMB SETA SETAI SETAM SETAB
;430 XOR XORI XORM XORB IOR IORI IORM IORB
;440 ANDCB ANDCBI ANDCBM ANDCBB EQV EQVI EQVM EQVB
;450 SETCA SETCAI SETCAM SETCAB ORCA ORCAI ORCAM ORCAB
;460 SETCM SETCMI SETCMM SETCMB ORCM ORCMI ORCMM ORCMB
;470 ORCB ORCBI ORCBM ORCBB SETO SETOI SETOM SETOB
; 0 1 2 3 4 5 6 7
;500 HLL HLLI HLLM HLLS HRL HRLI HRLM HRLS
;510 HLLZ HLLZI HLLZM HLLZS HRLZ HRLZI HRLZM HRLZS
;520 HLLO HLLOI HLLOM HLLOS HRLO HRLOI HRLOM HRLOS
;530 HLLE HLLEI HLLEM HLLES HRLE HRLEI HRLEM HRLES
;540 HRR HRRI HRRM HRRS HLR HLRI HLRM HLRS
;550 HRRZ HRRZI HRRZM HRRZS HLRZ HLRZI HLRZM HLRZS
;560 HRRO HRROI HRROM HRROS HLRO HLROI HLROM HLROS
;570 HRRE HRREI HRREM HRRES HLRE HLREI HLREM HLRES
; 0 1 2 3 4 5 6 7
;600 TRN TLN TRNE TLNE TRNA TLNA TRNN TLNN
;610 TDN TSN TDNE TSNE TDNA TSNA TDNN TSNN
;620 TRZ TLZ TRZE TLZE TRZA TLZA TRZN TLZN
;630 TDZ TSZ TDZE TSZE TDZA TSZA TDZN TSZN
;640 TRC TLC TRCE TLCE TRCA TLCA TRCN TLCN
;650 TDC TSC TDCE TSCE TDCA TSCA TDCN TSCN
;660 TRO TLO TROE TLOE TROA TLOA TRON TLON
;670 TDO TSO TDOE TSOE TDOA TSOA TDON TSON
.TOC "CONTROL RAM DEFINITIONS -- J, AD"
;FIELDS ARRANGED FOR READABILITY, NOT COMPACTNESS
; IN THE PROCESSOR, BITS ARE SCATTERED IN ANOTHER ORDER
U0/=<0:0>D,0 ;BIT 0 UNUSED
J/=<1:11>+ ;SYMBOLS WILL BE DEFINED BY TAGS (CRA1&CRA2)
;MAIN ADDER CONTROLS. Bit 0 = carry in, bit 1 = boolean operation
; Bits 2-5 are S8-S1 of the 10181 ALU chip. For normal arithmetic,
; the AD and ADX are separated unless SPEC/AD LONG or equivalent is given.
AD/=<12:17> ; (DP03, EXCEPT CARRY IN, ON CTL1)
A+1=40,1
A+XCRY=00,1
; A+ANDCB=01,1
; A+AND=02,1
A*2=03,1
A*2+1=43,1
; OR+1=44,1
; OR+ANDCB=05,1
A+B=06,1
A+B+1=46,1
; A+OR=07,1
ORCB+1=50,1
A-B-1=11,1
A-B=51,1
; AND+ORCB=52,1
; A+ORCB=53,1
XCRY-1=54,1
; ANDCB-1=15,1
; AND-1=16,1
A-1=17,1
;ADDER LOGICAL FUNCTIONS
SETCA=20
ORC=21 ;NAND
ORCA=22
1S=23
ANDC=24 ;NOR
NOR=24
SETCB=25
EQV=26
ORCB=27
ANDCA=30
XOR=31
B=32
OR=33
0S=34
ANDCB=35
AND=36
A=37
;BOOLEAN FUNCTIONS FOR WHICH CRY0 IS INTERESTING
CRY A EQ -1=60,1 ;GENERATE CRY0 IF A=1S, AD=SETCA
CRY A.B#0=36,1 ;CRY 0 IF A&B NON-ZERO, AD=AND
CRY A#0=37,1 ;GENERATE CRY0 IF A .NE. 0, AD=A
CRY A GE B=71,1 ;CRY0 IF A .GE. B, UNSIGNED; AD=XOR
.TOC "CONTROL RAM DEFINITIONS -- DATA PATH MIXERS"
ADA/=<18:20> ; (DP03)
AR=0
ARX=1
MQ=2
PC=3
ADA EN/=<18:18> ;ADA ENABLE ALSO ENABLES ADXA (DP03)
EN=0
0S=1
U21/=<21:21>D,0 ;BIT 21 UNUSED
ADB/=<22:23> ;CONTROLS ADB AND ADXB (DP03)
FM=0,,1 ;MUST HAVE TIME FOR PARITY CHECK
BR*2=1 ;ADB35 is BRX0; ADXB35 is 0
BR=2
AR*4=3 ;ADB34,35 are ARX0,1; ADXB34,35 are 0
U23/=<23:23>D,1 ;PREVENT DEFAULT SELECTION OF FM
;FORCE IT TO TAKE ONE OF THE SHORTER
;PATHS IF FM NOT NEEDED ALSO DISABLES
;PARITY CHECKING LOGIC
;REGISTER INPUTS
AR/=<24:26>D,0 ; (DP01)
AR=0
ARMM=0 ;REQUIRES SPECIAL FUNCTION
MEM=0 ;[346] MB WAIT will poke to 1 (CACHE) or 2 (AD)
CACHE=1 ;ORDINARILY SELECTED BY HWARE
AD=2
EBUS=3
SH=4
AD*2=5 ;Low bit from ADX0
ADX=6
AD*.25=7
ARX/=<27:29>D,0 ; (DP02)
ARX=0 ;[345] BY DEFAULT
MEM=0 ;[346] Gets poked by MB WAIT to 1 or 2
CACHE=1 ;ORDINARILY BY MBOX RESP
AD=2
MQ=3
SH=4
ADX*2=5 ;Low bit from MQ0
ADX=6
ADX*.25=7 ;High bits from AD34,35
BR/=<30:30>D,0 ;DEFAULT TO RECIRCULATE (DP04)
AR=1
BRX/=<31:31>D,0 ;DEFAULT TO RECIRCULATE (DP04)
ARX=1
MQ/=<32:32>D,0 ;DEFAULT TO RECIRCULATE (DP02)
SH=1 ;LOAD FROM SHIFT MATRIX
MQ*2=0 ;With SPEC/MQ SHIFT--Low bit from AD CRY -2
MQ*.25=1 ;With SPEC/MQ SHIFT--High bits from ADX34, ADX35
MQ SEL=0 ;WITH COND/REG CTL
MQM SEL=1 ;WITH COND/REG CTL
;FMADR SELECTS THE SOURCE OF THE FAST MEMORY ADDRESS,
; RATHER THAN PROVIDING THE ADDRESS ITSELF
FMADR/=<33:35> ; (APR4&APR5)
AC0=0 ;IR 9-12
AC1=1 ;<IR 9-12>+1 MOD 16
XR=2 ;ARX 14-17
VMA=3 ;VMA 32-35
AC2=4 ;<IR 9-12>+2 MOD 16
AC3=5 ;<IR 9-12>+3 MOD 16
AC+#=6 ;CURRENT BLOCK, AC+ MAGIC #
#B#=7 ;BLOCK AND AC SELECTED BY # FIELD
.TOC "CONTROL RAM DEFINITIONS -- 10-BIT LOGIC"
SCAD/=<36:38> ; (SCD1)
A=0
A-B-1=1
A+B=2
A-1=3
A+1=4
A-B=5
OR=6
AND=7
SCADA/=<39:41> ; (SCD1)
FE=0
AR0-5=1 ;BYTE POINTER P FIELD
AR EXP=2 ;<AR 01-08> XOR <AR 00>
#=3 ;SIGN EXTENDED WITH #00
SCADA EN/=<39:39> ; (SCD1)
0S=1
U42/=<42:42>D,0 ;BIT 42 UNUSED
SCADB/=<43:44> ; (SCD1)
SC=0
AR6-11=1 ;BYTE POINTER S FIELD
AR0-8=2
#=3 ;NO SIGN EXTENSION
U45/=<45:45>D,0 ;BIT 45 UNUSED
SC/=<46:46>D,0 ;RECIRCULATE BY DEFAULT (SCD2)
FE=0 ;WITH SCM ALT
SCAD=1
AR SHIFT=1 ;WITH SCM ALT ;AR 18, 28-35
FE/=<47:47>D,0 ;RECIRCULATE BY DEFAULT (SCD2)
SCAD=1
U48/=<48:48>D,0 ;BIT 48 UNUSED
.TOC "CONTROL RAM DEFINITIONS -- SHIFT, ARMM, VMA, TIME"
SH/=<49:50> ; (SH1)
SHIFT AR!ARX=0 ;LEFT BY (SC)
AR=1
ARX=2
AR SWAP=3 ;HALVES SWAPPED
ARMM/=<49:50> ;SAME BITS AS SH CONTROL (SCD3)
#=0 ;MAGIC # 0-8 TO AR 0-8
EXP_SIGN=1 ;AR1-8 _ AR0
SCAD EXP=2 ;AR0-8_SCAD
SCAD POS=3 ;AR0-5_SCAD
VMAX/=<49:50> ;SAME BITS AS SH CONTROL (VMA4)
VMAX=0 ;VMA SECTION #
PC SEC=1 ;PC SECTION #
PREV SEC=2 ;PREVIOUS CONTEXT SECT
AD12-17=3
U51/=<51:51>D,0 ;BIT 51 UNUSED
VMA/=<52:53>D,0 ;ALSO CONTROLLED BY SPECIAL FUNCTIONS
VMA=0 ;BY DEFAULT
PC=1 ;MAY BE OVERRIDDEN BY MCL LOGIC TO LOAD FROM AD
LOAD=1 ; IF WE KNOW IT WILL BE OVERRIDDEN, USE THIS
PC+1=2
AD=3 ;ENTIRE VMA, INCLUDING SECTION
TIME/=<54:55>T ;CONTROLS MINIMUM MICROINSTRUCTION EXECUTION
; TIME, COUNTING MBOX CLOCK TICKS (CLK)
;ASSEMBLER GENERALLY TAKES CARE OF THIS
2T=0 ;2 TICKS
3T=1 ;3 TICKS
4T=2 ;4 TICKS
5T=3 ;5 TICKS (COND/DIAG FUNC & #00, --> .5 USEC)
.TOC "CONTROL RAM DEFINITIONS -- MEM SPECIAL FUNCTIONS"
MEM/=<56:59>D,0 ;(MCL1, except MB WAIT on CON5 and CLK4)
;
; Note: MB WAIT is implicit whenever bit 58 is set.
;
; NOP=0 ;DEFAULT
ARL IND=1 ;CONTROL AR LEFT MUX FROM # FIELD
MB WAIT=2 ;WAIT FOR MBOX RESP IF PENDING
RESTORE VMA=3 ;AD FUNC WITHOUT GENERATING A REQUEST
A RD=4 ;OPERAND READ and load PXCT bits
B WRITE=5 ;CONDITIONAL WRITE ON DRAM B 01
FETCH=6 ;LOAD NEXT INSTR TO ARX (CONTROL BY #)
REG FUNC=7 ;MBOX REGISTER FUNCTIONS
AD FUNC=10 ;FUNCTION LOADED FROM AD LEFT
EA CALC=11 ;FUNCTION DECODED FROM # FIELD
LOAD AR=12
LOAD ARX=13
RW=14 ;READ, TEST WRITABILITY
RPW=15 ;READ-PAUSE-WRITE
WRITE=16 ;FROM AR TO MEMORY
IFET=17 ;UNCONDITIONAL instruction FETCH
.TOC "CONTROL RAM DEFINITIONS -- SKIP/COND SPECIAL FUNCTIONS"
SKIP/=<60:65>D,0 ;MICRO-PROGRAM SKIPS
; 40-57 DECODED ON (CRA2)
; SPARE=40
EVEN PAR=41,,1 ;AR PARITY IS EVEN
BR0=42 ;BR BIT 00
ARX0=43 ;ARX BIT 00
AR18=44 ;AR BIT 18
AR0=45 ;AR BIT 00
AC#0=46 ;IR9-12 .EQ. 0
SC0=47 ;SC BIT 00
PC SEC0=50
SCAD0=51,,1 ;Sign of SCAD output--WRONG ON OVERFLOW FROM BIT 1!!!
SCAD#0=52,,1 ;SCAD OUTPUT IS NON-ZERO
ADX0=53,1 ;ADDER EXTENSION BIT 00
AD CRY0=54,1 ;CARRY OUT OF AD BIT -2 (BOOLE IGNORED)
AD0=55,1 ;ADDER BIT 00
AD#0=56,1 ;AD BITS 00-35 CONTAIN SOME ONES
-LOCAL AC ADDR=57 ;VMA18-31 =0 ON LOCAL REF IN SEC >1
; 60-77 DECODED ON (CON2)
FETCH=60 ;VMA FETCH (LAST CYCLE WAS A FETCH)
KERNEL=61 ;PC IS IN KERNEL MODE
USER=62 ;PC IS IN USER MODE
PUBLIC=63 ;PC IS PUBLIC (INCLUDING SUPER)
RPW REF=64 ;MIDDLE OF READ-PAUSE-WRITE CYCLE
PI CYCLE=65 ;PI CYCLE IN PROGRESS
-EBUS GRANT=66 ;PI HASN'T RELEASED BUS FOR CPU USE
-EBUS XFER=67 ;NO TRANSFER RECIEVED FROM DEVICE
INTRPT=70 ;AN INTERRUPT REQUEST WAITING FOR SERVICE
-START=71 ;NO CONTINUE BUTTON
RUN=72 ;PROCESSOR NOT HALTED
IO LEGAL=73 ;KERNEL, PI CYCLE, USER IOT, OR DEVICE .GE. 740
P!S XCT=74 ;PXCT OR SXCT
-VMA SEC0=75 ;VMA SECTION NUMBER (13-17) IS NOT ZERO
AC REF=76,,1 ;VMA .LT.20 ON READ OR WRITE
-MTR REQ=77 ;INTERRUPT REQUEST NOT DUE TO METER
;SKIP/COND FIELD CONTINUED
COND/=<60:65>D,0 ;NON-SKIP SPECIAL FUNCTIONS
;0-7 DECODED ON (CTL2)
; NOP=0 ;BY DEFAULT
LD AR0-8=1
LD AR9-17=2 ;Gates VMAX into ARMM (see VMA4)
LD AR18-35=3
AR CLR=4
ARX CLR=5
ARL IND=6 ;CONTROL AR LEFT, CALL, AND CLEAR BITS FROM #
REG CTL=7 ;CONTROL AR LOAD, EXP TST, AND MQ FROM #
; 10-37 DECODED ON (CON1)
FM WRITE=10 ;WRITE AR INTO CURRENTLY ADDRESSED FM LOC
PCF_#=11 ;SET PC FLAGS FROM # FIELD
FE SHRT=12 ;SHIFT FE RIGHT 1
AD FLAGS=13 ;SET PC CRY0, CRY1, OVRFLO, TRAP1 AS APPROPRIATE
LOAD IR=14 ;LATCH AD OR CACHE DATA INTO IR, load PXCT bits
SPEC INSTR=15 ;SET/CLR SXCT, PXCT, PICYC, TRAP INSTR FLAGS
SR_#=16 ;CONTROL FOR STATE REGISTER and PXCT bits (CON3, MCL4)
SEL VMA=17 ;READ VMA THROUGH ADA/PC
DIAG FUNC=20 ;SELECT DIAGNOSTIC INFO ONTO EBUS
EBOX STATE=21 ;SET STATE FLOPS
EBUS CTL=22 ;I/O FUNCTIONS
MBOX CTL=23
; SPARE=24
LONG EN=25 ;THIS WORD CAN BE INTERPRETED AS LONG INDIRECT
; SPARE=26
; SPARE=27
VMA_#=30
VMA_#+TRAP=31
VMA_#+MODE=32
VMA_#+AR32-35=33
VMA_#+PI*2=34
VMA DEC=35 ;VMA_VMA-1
VMA INC=36 ;VMA_VMA+1
LD VMA HELD=37 ;HOLD VMA ON SIDE
CALL/=<66:66>D,0 ;CALL function--May not coexist with DISP/RETURN
CALL=1 ;GOOD TO 15 LEVELS IN MODEL B
.TOC "CONTROL RAM DEFINITIONS -- DISP/SPEC SPECIAL FUNCTIONS"
DISP/=<67:71>D,10 ;0-7 AND 30-37 ARE DISPATCHES (CRA1&CRA2)
DIAG=0
DRAM J=1
DRAM A RD=2 ;IMPLIES INH CRY18
RETURN=3 ;POPJ return--may not coexist with CALL
PG FAIL=4 ;PAGE FAIL TYPE DISP
SR=5 ;16 WAYS ON STATE REGISTER
NICOND=6 ;NEXT INSTRUCTION CONDITION (see NEXT for detail)
SH0-3=7,,1 ;[337] 16 WAYS ON HIGH-ORDER BITS OF SHIFTER
MUL=30 ;FE0*4 + MQ34*2 + MQ35; implies MQ SHIFT, AD LONG
DIV=31,,1 ;FE0*4 + BR0*2 + AD CRY0; implies MQ SHIFT, AD LONG
SIGNS=32,1 ;ARX0*8 + AR0*4 + BR0*2 + AD0
DRAM B=33 ;8 WAYS ON DRAM B FIELD
BYTE=34,,1 ;FPD*4 + AR12*2 + SCAD0--WRONG ON OVERFLOW FROM BIT 1!!
NORM=35,2 ;See normalization for details. Implies AD LONG
EA MOD=36 ;(ARX0 or -LONG EN)*8 + -(LONG EN and ARX1)*4 +
;ARX13*2 + (ARX2-5) or (ARX14-17) non zero; enable
;is (ARX0 or -LONG EN) for second case. If ARX18
;is 0, clear AR left; otherwise, poke ARL select
;to set bit 2 (usually gates AD left into ARL)
SPEC/=<67:71>D,10 ;NON-DISPATCH SPECIAL FUNCTIONS (CTL1)
; NOP=10 ;DEFAULT
INH CRY18=11
MQ SHIFT=12 ;ENABLE MQ*2, MQ SHRT2
SCM ALT=13 ;ENABLE FE, ARSHIFT
CLR FPD=14
LOAD PC=15
XCRY AR0=16 ;CARRY INTO AD IS XOR'D WITH AR00
GEN CRY18=17
STACK UPDATE=20 ;CONTROL CRY18 IF LOCAL STACK
; SUBR CALL=21 ;Obsolete--model A only
ARL IND=22 ;# SPECIFIES ARL MIX, ENABLES, & CALL
MTR CTL=23 ;# CONTROLS METERS
FLAG CTL=24 ;FUNCTION ENCODED IN # FIELD
SAVE FLAGS=25 ;TELLS PI CYCLE TO HOLD INTRPT
SP MEM CYCLE=26 ;MEM REQUEST IS MODIFIED BY #
AD LONG=27 ;AD BECOMES 72 BIT ALU
U73/=<72:73>D,0 ;BITS 72-73 UNUSED
MARK/=<74:74>D,0 ;FIELD SERVICE "MARK" BIT
.TOC "CONTROL RAM DEFINITIONS -- MAGIC NUMBER FIELD"
#/=<75:83>D,0 ;THE INFAMOUS "MAGIC NUMBERS"
MAJVER/=<75:80> ;[356] Major version number
MINVER/=<81:83> ;[356] Minor version number
;
; Options bits, designating different assemblies from the same sources
;
KLPAGE/=<75:75> ;KLPAGING
OPTIONS=1
LONGPC/=<76:76> ;LONG PC FORMAT AS IN EXTENDED ADDRESSING
OPTIONS=1 ;(The model A used a different format due
; to space limitations)
NONSTD/=<77:77> ;NONSTANDARD (EG DIAGNOSTIC) MICROCODE
.IF/NONSTD
OPTIONS=1
.IFNOT/NONSTD
OPTIONS=0
.ENDIF/NONSTD
PV/=<78:78> ;MODEL B - PV CPU
OPTIONS=1
PMOVE/=<79:79> ;[435] Physical memory move instructions
OPTIONS=1
ISTAT/=<83:83> ;STATISTICS GATHERING CODE (IE TRACKS)
.IF/INSTR.STAT
OPTIONS=1
.IFNOT/INSTR.STAT
OPTIONS=0
.ENDIF/INSTR.STAT
PXCT/=<75:77> ;(MCL4) Loaded by CON/SR_#, CON/LOAD IR, and MEM/A RD
;Bit 0 enables the VMAX to not come from the AD when
; VMA/AD (allowing local AC refs, for example). Bits
; 1 and 2 select which PXCT bits a memory reference
; will select for possible previous context.
ACB/=<77:79> ;AC block number. Used with FMADR/#B#
PAGB=6 ;AC block used for KL paging registers
MICROB=7 ;AC block for general microcode scratch
AC#/=<80:83> ;AC number used with ACB or AC-OP (below)
;
; Warning: when AC-OP is used with COND/FM WRITE, the previous micro-
; instruction must have the same # field as the current one. Otherwise
; the address lines won't make it in time for the write pulse. [210]
;
AC-OP/=<75:79> ;CONTROLS AC #. AD functions < 40 all work
AC+#=6
#=32 ;JUST AC#
OR=33 ;AC <OR> AC#
;VARIOUS SPECIAL FUNCTIONS ENABLE SPECIAL DECODING OF THE
; "MAGIC #" FIELD, AS FOLLOWS:
;SPECIAL DATA PATH CONTROLS
;CALL/=<75:75> ;ENABLED BY ARL IND (CTL2)--Model A only
; CALL=1
AR0-8/=<76:76> ;ENABLED BY ARL IND (CTL2)
LOAD=1
CLR/=<77:80> ;ENABLED BY ARL IND (CTL2)
MQ=10
ARX=4
ARL=2
ARR=1
AR=3
AR+ARX=7
AR+MQ=13
ARX+MQ=14
AR+ARX+MQ=17
ARL+ARX=6
ARL+ARX+MQ=16
ARR+MQ=11
ARL/=<81:83> ;ENABLED BY ARL IND (CTL2)
ARL=0
ARMM=0 ;REQUIRES SPECIAL FUNCTION
CACHE=1 ;ORDINARILY SELECTED BY HWARE
AD=2
EBUS=3
SH=4
AD*2=5
ADX=6
AD*.25=7
AR CTL/=<75:77> ;ENABLED BY COND/REG CTL (CTL2)
AR0-8 LOAD=4
AR9-17 LOAD=2 ;Gates VMAX into ARMM (see VMA4)
ARR LOAD=1
ARL LOAD=6
EXP TST/=<80:80> ;ENABLED BY COND/REG CTL (CTL1)
AR_EXP=1
MQ CTL/=<82:83> ;ENABLED BY COND/REG CTL (CTL2)
; MQ=0 ;WITH MQ/MQ SEL
MQ*2=1 ;WITH MQ/MQ SEL--Low bit is ADX0
; MQ*.5=2 ; " (DROPS BITS 0,6,12,18,24,30)
0S=3 ; "
SH=0 ;WITH MQ/MQM SEL
MQ*.25=1 ;WITH MQ/MQM SEL--High bits are ADX34, ADX35
1S=2 ; "
AD=3 ; "
;SPECIAL CONTROL OF EBOX FLAGS & FUNCTIONS
PC FLAGS/=<75:83> ;ENABLED BY COND/PCF_# (SCD4)
; OVERF=400 ;Any arithmetic overflow
; FLOVERF=200 ;Floating overflow
FPD=100 ;SET FIRST PART DONE
TRAP2=40 ;SET TRAP2 (PDL OVFLO)
TRAP1=20 ;SET TRAP1 (ARITH OVFLO)
; EXPUND=10 ;Exponent underflow
; NO DIV=4 ;No divide
AROV=420 ;SET ARITH OVFLO & TRAP1
FLOV=620 ;SAME, PLUS FLOATING OVFLO
FXU=630 ;FLOV + EXP UNDERFLOW
DIV CHK=424 ;NO DIVIDE + AROV
FDV CHK=624 ;FLOATING NO DIVIDE
FLAG CTL/=<75:83> ;ENABLED BY SPEC/FLAG CTL (SCD5)
RSTR FLAGS=420 ;AS IN JRSTF
JFCL=602 ;FORCE PC 00 = AROV
JFCL+LD=622 ;SECOND PART OF JFCL -- CLEAR TESTED FLAGS
DISMISS=502 ;CLEAR PI CYCLE IF SET (CON5)
; ELSE DISMISS HIGHEST PI HOLD
DISMISS+LD=522 ;LOAD FLAGS AND DISMISS
HALT=442 ;STOP PROCESSOR IF LEGAL (CON2)
SET FLAGS=20 ;AS IN MUUO
PORTAL=412 ;CLEAR PUBLIC IF PRIVATE INSTR
SPEC INSTR/=<75:83> ;ENABLED BY COND/SPEC INSTR
SET PI CYCLE=714; (CON5)
KERNEL CYCLE=200;MAKE IO LEGAL, EXEC ADDR SPACE (CON4)
INH PC+1=100 ;TO MAKE JSR WORK IN TRAP, INTRPT (CON4)
SXCT=40 ;START SECTION XCT (MCL4)
PXCT=20 ;START PREV CONTXT XCT (MCL4)
INTRPT INH=10 ;INHIBIT INTERRUPTS (CON4)
INSTR ABORT=4 ; (CON2)
HALTED=302 ;TELL CONSOLE WE'RE HALTED (CON4)
CONS XCT=310 ;FLAGS FOR INSTR XCT'D FROM CONSOLE
CONT=0 ;RESTORE NORMAL STATE FOR CONTINUE
FETCH/=<75:83> ;ENABLED BY MEM/FETCH
UNCOND=400
;LOW 2 BITS DECODED ON (IR3)
COMP=201,2 ;DEPENDING ON AD AND DRAM B
SKIP=202,2
TEST=203,1
JUMP=502,2 ;AS IN JUMPX, ON AD AND DRAM B
JFCL=503,1 ;JUMP ON TEST CONDITION
;SPECIAL MEMORY REQUEST FUNCTIONS
EA CALC/=<75:83> ;SPECIFIC CONTROLS FOR MEM/EA CALC
; LOAD AR=400
; LOAD ARX=200
; PAUSE=100 ;Freeze memory--always use with 040
; WRITE=040 ;SET VMA WRITE
; PREV EN=20 ;PREV CONTXT SELECTED BY SR AND PXCT
; INDIRECT=10 ;PREV CONTXT FOR EA CALC
; EA=2 ;RESTORATION OF ORIGINAL EA CONDITIONS
; STACK=1 ;PREV CONTXT SELECTED BY PXCT B12
A IND=230 ;INDIRECT AT FIRST EA CALC TIME
BYTE LD=420 ;Read byte data to AR only [337]
BYTE RD=620 ;READ BYTE DATA TO AR & ARX
BYTE RD PC=621 ;READ BYTE DATA TO AR & ARX WITH PC SECTION
BYTE RPW=760 ;Read byte data to AR, ARX, write test, pause [312]
BYTE IND=610 ;INDIRECT AT BYTE EA CALC TIME
PUSH=041 ;STORE TO STACK
POP AR=421 ;READ FROM STACK TO AR
POP ARX=221 ;READ FROM STACK TO ARX
POP AR-ARX=621 ;POP TO BOTH
WRITE(E)=042
LD AR(EA)=402 ;LOAD AR GLOBAL/LOCAL AS IN EA
LD AR+WR=440 ;LOAD AR, TEST WRITABILITY
LD ARX+WR=240 ;LOAD ARX, TEST WRITABILITY
SP MEM/=<75:83> ;ENABLED BY SPEC/SP MEM CYCLE
FETCH=400 ;LOAD IR WHEN DATA ARRIVES (MCL5)
USER=200 ;FORCE USER OR UPT (MCL2)
EXEC=100 ;FORCE EXEC OR EPT (MCL3)
SEC 0=40 ;CLEAR VMAX (MCL4)
UPT EN=20 ;UPT IF USER EN (MCL3)
EPT EN=10 ;EPT IF NOT USER EN (MCL3)
CACHE INH=2 ; (MCL6)
UNCSH+UNPAGE=103;UNCACHED AND UNPAGED
UNPAGED+CACHED=101 ;physical reference with cache enabled.
.IFNOT/MULTI
UNPAGED=101 ; (MCL6)
EPT=111
EPT CACHE=111 ;[260]
EPT FETCH=511
UPT=221
UPT FETCH=621
PT=31
PT FETCH=431
.IF/MULTI
UNPAGED=103 ; (MCL6)
EPT=113
EPT CACHE=111 ;[260]
EPT FETCH=513
UPT=223
UPT FETCH=623
PT=33
PT FETCH=433
.ENDIF/MULTI
;MBOX CONTROLS
MREG FNC/=<75:83> ;ENABLED BY MEM/REG FUNC (APR6)
SBUS DIAG=407 ;PERFORM SBUS DIAGNOSTIC CYCLE
READ UBR=502 ;ASK MBOX TO LOAD UBR INTO EBUS REG
READ EBR=503 ;PUT EBR INTO EBUS REG
READ ERA=504
WR REFILL RAM=505 ;DISGUISED AS A "READ REG" FUNCTION
LOAD CCA=606 ;START A SWEEP
LOAD UBR=602 ;SETUP UBR FROM VMA
LOAD EBR=603 ;SETUP EBR FROM VMA
MAP=140 ;GET PHYS ADDR CORRESPONDING TO VMA (MCL6)
MBOX CTL/=<75:83> ;ENABLED BY COND/MBOX CTL (APR5)
SET PAGE FAIL=200
SET IO PF ERR=100
CLR PT LINE(NK)=61,,1;[333] Clear valid if no Keep bit set
PT DIR CLR(NK)=41;Enable clear of PT DIR for non keep entries
CLR PT LINE=31,,1;CLEAR VALID FOR 4 ENTRIES (new pager board) [342]
PT DIR WR=20,1 ;WRITE PAGE TABLE DIRECTORY
PT WR=10,1 ;WRITE PAGE TABLE ENTRY SELECTED BY VMA
PT DIR CLR=1 ;SELECT FOR CLEARING PT DIR (PAG3)
NORMAL=0 ;RESET PT WR SELECTION
MTR CTL/=<81:83> ;FUNCTION DECODING FOR METERS (MTR3)
CLR TIME=0 ; USUALLY USED WITH DIAG FUNC
CLR PERF=1
CLR E CNT=2
CLR M CNT=3
LD PA LH=4
LD PA RH=5
CONO MTR=6
CONO TIM=7
;I/O FUNCTIONS
EBUS CTL/=<75:83> ;ENABLED BY COND/EBUS CTL (APR3)
GRAB EEBUS=400 ;"EBUS RETURN" TAKES ECL EBUS FOR EBOX
REQ EBUS=200
REL EBUS=100 ; (CON3)
EBUS DEMAND=60 ;ASSERT DEMAND, KEEP CS, FUNC
EBUS NODEMAND=20;DROP DEMAND, KEEP CS, FUNC
; CTL_IR=10 ;SELECT F01 & F02 FROM IR
; DISABLE CS=4 ;TURN OFF CONTROLLER SELECT
; DATAIO=2 ;0 FOR CONI/O
; INPUT=1 ;0 FOR OUTPUT
IO INIT=30 ;ENABLE IR3-9 TO EBUS CONTROLLER SELECT,
; IR10-12 (DECODED) TO FUNCTION
; AND AR ONTO EBUS IF FUNCTION IS OUTPUT
DATAO=26 ;0'S TO CS, DATAO TO FCN, AND AR TO EBUS
DATAI=27 ;0'S TO CS, DATAI TO FCN
REL EEBUS=0 ;LEGGO
DIAG FUNC/=<75:83> ;ENABLED BY COND/DIAG FUNC (CTL3)
.5 USEC=400,3 ;STRETCH CLOCK TO LET EBUS SETTLE (CON?)
LD PA LEFT=404,3 ;LH PERF ANAL CONTROLS FROM RH (MTR)
LD PA RIGHT=405,3 ;RH PA CONTROLS FROM RH (MTR)
CONO MTR=406,3 ;ACCOUNTING CONTROLS (MTR)
CONO TIM=407,3 ;INTERVAL TIMER CONTROLS (MTR)
CONO APR=414,3 ; (CON3)
CONO PI=415,3 ; (CON3)
CONO PAG=416,3 ;CACHE & PAGING CTL (CON3)
DATAO APR=417,3 ;ADDRESS BREAK (CON3)
DATAO PAG=620,3 ;AC BLOCKS & PREV CONTXT (CON3)
LD AC BLKS=425,3 ;FORCE LOADING AC BLOCKS
LD PCS+CWSX=426,3 ;FORCE LOADING PREV CONTXT SEC, CWSX
CONI PI(R)=500,3 ;PI HOLD & ACTIVE TO LH (PI)
CONI PI(L)=501,3 ;PI GEN TO LH (PI)
CONI APR(R)=510,3 ;APR INTERRUPT & PIA TO LH (APR6)
RD TIME=510,3 ;TIME BASE TO RH (MTR5)
DATAI PAG(L)=511,3 ;AC BLOCKS, PREV CONTXT TO LH (APR6)
RD PERF CNT=511,3 ;PERFORMANCE COUNT TO RH (MTR5)
CONI APR(L)=512,3 ;APR INTERRUPT ENABLES TO LH (APR6)
RD EBOX CNT=512,3 ;EBOX COUNT TO RH (MTR5)
DATAI APR=513,3 ;ADDR BREAK CONDITIONS TO LH (APR6)
RD CACHE CNT=513,3 ;CACHE COUNT TO RH (MTR5)
RD INTRVL=514,3 ;INTERVAL TIMER TO RH (MTR5)
RD PERIOD=515,3 ;PERIOD REGISTER TO RH (MTR5)
CONI MTR=516,3 ;CONTROLS & PIA TO RH (MTR5)
RD MTR REQ=517,3 ;ENCODED UPDATE REQUEST TO 20-22 (MTR5)
CONI PI(PAR)=530,3 ;WRITE EVEN PARITY ENABLES TO RH (CON1)
CONI PAG=531,3 ;CACHE & TRAP CTL TO RH (CON1)
RD EBUS REG=567,3 ;EBUS REGISTER IN MBOX (MBZ1 & MBC1)
PARITY/=0,0,0,P ;USE ANY AVAILABLE FIELD FOR PARITY
.TOC "DISPATCH RAM DEFINITIONS"
;FIELDS ARE ARRANGED FOR EASY READING, NOT COMPACTNESS
.DCODE
A/=<0:2> ;OPERAND FETCH MODE
IMMED=0 ;IMMEDIATE
IMMED-PF=1 ;IMMEDIATE, START PREFETCH
ADDR=2 ;FULL EFFECTIVE ADDRESS
WR-TST=3 ;TEST WRITABILITY
READ=4 ;READ ONLY
READ-PF=5 ;READ, THEN PREFETCH
RD-WR=6 ;READ WRITE (SEPARATE CYCLES)
RD-P-WR=7 ;READ PAUSE WRITE
B/=<3:5> ;STORE RESULTS AT--
DBL AC=1 ;DOUBLE RESULT TO AC & AC+1
DBL BOTH=2 ;MULB, DIVB, ETC
SELF=3 ;SELF MODE INSTRUCTIONS
AC=5 ;SINGLE RESULT TO AC, PREFETCH IN PROG
MEM=6 ;RESULT TO MEMORY
BOTH=7 ;SINGLE RESULT TO MEMORY AND AC
SJC-=3 ;SKIP JUMP COMPARE CONTROLS
SJCL=2
SJCE=1
SJCLE=0
SJCA=7
SJCGE=6
SJCN=5
SJCG=4
B0/=<3:3> ;INVERTS VARIOUS TEST, SKIP, AND JUMP CONTROLS
CRY0(0)=0 ;TEST TST CAUSES PC SKIP IF CRY0=0
CRY0(1)=1 ; SAME IF CRY0=1
B1-2/=<4:5> ;FLOATING RESULT STORE MODE
AC=1 ;RESULT TO AC
MEM=2 ;RESULT JUST TO MEM
BOTH=3 ;RESULT TO BOTH
PARITY/=<11:11>P
;
; The J field is the starting location of the microroutine to
; execute the instruction. Note that the 40 and 20 bits must
; always be zero. Also, even-odd pairs of DRAM J fields may
; differ only in the low order three bits. (Someone thought he
; was being very clever when he designed the machine this way.
; It probably reduced our transfer cost by at least five dollars,
; after all, and the microcode pain that occurred later didn't cost
; anything, in theory.)
;
J/=<14:23> ;EXECUTOR
.UCODE
.BIN